JPS5910084A - Data transfer device - Google Patents

Abstract

PURPOSE:To shorten the transfer time and to improve the transfer efficiency, by transferring continuously and in one time the picture element data in a quadrangle enclosed by the lateral and longitudinal axes of a screen by a set-up of an address in one time. CONSTITUTION:When the picture element data in a quadrangle enclosed by the lateral and longitudinal axes of a screen is transferred, the lower (n) bits of an address of a memory 61 are changed successively from the lower (n) bits of a start address corresponding to an apex of the quadrangle through the lower (n) bits of an end address corresponding to the apex opposite to an apex of the tetragon. The successive change is repeated for the lower (n) bits of the address of the memory 61 every time the upper (q-n) bits of the address of the memory 61 are changed successively from the upper (q-n) bits of the start (or end) address through the upper (q-n) bits of the end (or start) address. Thus the address is supplied to the memory 61. In such a way, the picture element data can be transferred continuously and in one time by a set-up of the number of start addresses and picture element data.

Description

[Detailed description of the invention] By dividing into ≠ publication code; ≠ bits and repeating the sequential change of the lower n bits every time the upper (CI-11) bits are changed sequentially, By setting up the address, the pixel data of the quadrilateral area surrounded by the horizontal and vertical axes of the screen can be transferred continuously at one time.
An object of the present invention is to provide a data transfer device that can shorten transfer time and improve transfer efficiency.

Generally, when displaying an image on a display using digital image processing, an analog video signal is A-1) converted to, for example, luminance and two chromaticities for each pixel.

An 8-bit digital 1g signal is used for the entire search, 4t of digital signals are sequentially loaded into the memory, and if necessary, the digital signals are sequentially read out from this memory and converted from D to A, resulting in an analog video signal. The process of displaying images on a display is often used. Here, as shown in Figure 1, one screen has IVI (2+1≦M≦2'') pixels in the vertical direction, m is a positive integer, and N pixels (2°-1+1≦N≦2n, n positive) in the horizontal direction. arrangement a
) pixels, and when writing the 8-bit digital value of each pixel (hereinafter referred to as [pixel data DMNJ) into memory, the pixel data D! ! , and so on, the pixel data on the first line of the screen up to N is written 1 time, and then the pixel data D2 . , hereafter j
At the same time, the pixel data on the second line is stored, and the two-dimensional position information of the pixel data DMN is converted into a one-dimensional address in the memory in the same manner. Therefore, i*j (i+j is a positive integer, 1≦1) of the quadrilateral in the shaded area A in Figure 1.
≦M, 1≦j≦N) pixel data is stored in the memory by dividing j bytes of continuous pixel data into i blocks every N bytes, as shown in Figure 2. There is.

To transfer data from this memory, a direct memory access (hereinafter referred to as rDMA) method is used to shorten the transfer time. Figure 1 shows an example of a data transfer device using the conventional DMA method. The block system diagram is shown below. In the figure, 1 is a central processing unit (hereinafter referred to as rcPtJJ), and 2 is a 64-byte memory, for example.

At the same time as the CPU starts executing the input/output instructions regarding memory 2 in the program, it supplies and sets the 16-bit start address and load instruction of the transfer data to the counter 3, and then sets the 16-bit start address and load instruction of the transfer data. A load instruction is supplied to register 4 and set. After this, CPU1 issues a DMA start command (DMAST
) is supplied to l) the MA control circuit 5. DMA control circuit 5
In response to this, the DMA request number M (DMAR
EQ) is supplied to CPUIK, and CPU1 outputs the ``1'' tonal DMA enable signal (DMAAcK) to DMA.
The signal is supplied to the control circuit 5 and the address bus driver 6, and the data bus 6 is also abandoned during the period when the DMA request signal is "1".

The DMA control circuit 5 outputs C when the DMA enable signal becomes “1”.
D synchronized with the clock pulse (CLK) from PU 1
An MA timing pulse is generated and supplied to the counter 3 to count up the counter.

The counter 3 supplies its 16-bit count value as an address signal to one input terminal of an address bus driver 6 and a comparator 7. This address bus driver 6 is a CPU
While the DMA enable signal supplied from address bus 8 is "1", a 16-bit address signal from address counter 3 is supplied to memory 2 via address bus 8. Further, the comparator 7 compares the address signal from the counter 3 with the end address constantly supplied from the register 4, and supplies a match signal (EQ) to the DMA control circuit 5 when the two match. Due to this coincidence signal, the l)MA request signal output from the IJMA control circuit 5 becomes "0", which causes the CPU to
The DMA enable signal output by I becomes "0". Therefore,
Continuous addresses from the start address to the end address are supplied to the memory 2, and the part of the memory 2 at these addresses is written into or read out.

Here, IJMA transfer is a data transfer between the memory 2 and an input/output device (not shown) without going through the CPU 1, but the DMA transfer time is determined by the set-up time of the start address and end address, and the actual When CPtJt is an 8-bit microprocessor, the memory access time is approximately 1 μs per byte, while the setup time is approximately 30 to 30 μs per byte.
It takes 60 μs. In the conventional device shown in FIG. 3, one DMA transfer can only perform consecutive addresses, and considering the transfer efficiency when the blocks are divided into i blocks as shown in FIG. 2, for example, J ” 2 + ' ``500,
Assuming that the setup time is 50μs, this 1000
The data transfer time of bytes is 2600 (=(2X1 +
The setup time of 50) x 500) μS occupies about 96% of this time, resulting in a very poor transfer efficiency.

The present invention eliminates the above-mentioned drawbacks, and each embodiment thereof will be described with reference to FIG. 4 and subsequent figures.

The present invention considers memory addresses that store pixel data as two-dimensional addresses corresponding to rows and columns on the screen,
All pixel data of the shaded area in FIG. 1 is transferred in one set-up. For example, one screen is 256 (-28) II! in the horizontal (X) direction! II element, vertical (Y) direction 256
When dividing into pixels, the horizontal direction is an 8-bit X address,
The vertical direction is treated as an 8-bit X address, and the X address is the lower 8 bits and the X address is the upper 8 bits.16
A 64K (=216) byte memory is accessed using a bit XX address.

FIG. 4 shows a circuit diagram of a first embodiment of a data transfer device according to the present invention. In the figure, 10 is an input terminal to which an 8-bit address signal from the CPU (not shown) is input;
At the same time as the input/output instruction is executed, the PU supplies the lower 8 bits of the 16-bit start address (for example, roooooloooJ for jo in FIG. 1) to the input terminal 10, and also issues a load instruction (xs'i'p). It is supplied to the input terminal 11. Load command (XSTP) is inverter 1'2
After being inverted at , it is supplied to the load terminal of register 13,
The lower 8 bits of the start address are latched into the register 13. This register 13 supplies the latched 8-bit signal to an 8-bit counter 14 consisting of 4-bit counters 14a and 14b, and the load command (XSTP) from the inverter 12 is sent to the inverter 1.
5. OR circuit 1? , is slightly delayed and further inverted by the inverter 17, and is supplied to the load terminal of the counter 14, and the lower 8 bits of the start address are set in the counter 14. After this, the CPU issues a load instruction (XENP
) is supplied to the input terminal 18, and the lower 8 bits of the end address (for example, roooo
onIJ), and this 8-bit signal is sent to register 1.
It is latched to 9. Next, the CPU issues a load command (YS'l
"P) is supplied to the input terminal 20, and the upper 8 bits of the start address (for example, rooooooo-1) are supplied to the input terminal 20, and the upper 8 bits of the start address (for example, rooooooo-1) are supplied to the input terminal 20, and this is input to the 8-bit counter consisting of the 4-bit counters 21a and 21b. Set the counter 21, and then issue a load command (YENP).
is supplied to the input terminal 22, and the upper 8 bits of the end address (corresponding to 11 in FIG. 1, for example, roooooo
lol J) and causes it to be latched into register 23. After this, D shown in CPUtriM5 diagram (A)
M A, , < p-to instruction (DMA5', [')
is supplied to the input terminal 24.

This D M A start opposite (4A8T to D) is D
It is supplied to the preset terminal of a flip-flop 26 that constitutes the M A control circuit 25 and is cleared when the power is turned on, and this flip-flop 26 is preset so that the Q terminal output becomes "1" and becomes "L". The Q terminal output is the DMA request signal (1) & IAREQ shown in Figure 5).
) is output from the output terminal 27 to the C'PU. As a result, when the process being executed by the CPU is completed, the DMA enable signal (DMAACK) shown in FIG. 5 is supplied to the input terminal 28 as 11''. 1, the input terminal 29 is supplied with a clock pulse (CLK) shown in FIG. The inverted clock signal (CLK) shown in FIG. 5 (1ml) is supplied to the clock terminal of the flip-flop 32. 30 is supplied to the D terminal,
From the rising edge of the clock pulse (CLK) immediately after this, the Q output of the flip-flop 30 is activated.
DMAACK2) Ham 5 becomes "1" as shown in Figure (F)K. This DMA request signal is synthesized with the inverted clock signal from the inverter 34 in the NAND circuit 33 to generate the DMA timing pulse (DM
ATIMINO) and is supplied to one input terminal of the NAND circuit 35. Further, the Q output of the flip-flop 30 is inverted and then sent to the 8-bit address bus driver 36.
．． 3? are supplied to respective control input terminals. This address bus driver 37, 36 receives a DMA request signal (DMAAC).
When K 2 ) becomes "1", the count values supplied from the counters 21 and 14 are divided into the top 8 bits) roooooool
l J, lower 8 bits r 00000100 J, total 16 bit address signal r000000110000
0100 J from the output terminal 38 to a memory (not shown).

The comparator 39 is supplied with the lower 8 bits of the end address from the register 19 to the other input terminal, and compares the inputs. A comparison signal (XCMP) which becomes "1" when a match is generated is generated and the flip-flop 32
and a 4-bit comparator 418, 4 in the NAND circuit 4o.
The comparator 41 is supplied with the upper 8 bits of the end address from the register 23 to the other input terminal, and compares the inputs thereof. A comparison signal (YCMP) which becomes "1" when there is a match is generated and supplied to the other input terminal of the NAND circuit 4o.

In the above state, the comparison signals of comparators 39 and 41 are both Kr0.
Therefore, the flip-flop 32 is connected to the older brother n1lJ, and the NAND circuit 35 which supplies this Q terminal output outputs the DMA timing pulse (I)M.
A, T I M I MG ) is output, which is inverted by the inverter 42 and becomes the runt-up signal (XCN1'T, JP ) shown in FIG. 5(H), and the counter 1
/I can be supplied to the counting input terminal. Therefore, the count value of the counter 14 is counted up and the man's 1 bit (
XCNTI), second bit (XCNT2).

8 (33 bits (XCNT3) are shown in Figure 5 (I) and (
J) and (K). Here, counter 1
When the count value output of 4 becomes rooooollJ, the 5th
The comparison signal (XCMP) of the Hinakuki 39 shown in Figure (L) is “
1'', and the flip-flop 32 shown in FIG. 5(M)
The Q laminate A child output (JJCMP) becomes “0” and D
The MA timing pulse is no longer output from the NAND circuit 35, and the count-up of the counter 14 is stopped.

At this time, the Q terminal output of the flip-flop 32 is "1"
The load signal -q(, xt, u) shown in FIG.
) becomes IIJ, and an OR circuit 16. Through the inverter 17, it is further inverted with a slight delay and is supplied to the load terminals of the counters 14a and i4b.
The lower 8 pits of the start address supplied by r 0
When 0000100J is set, the comparison signal (XCMP) of the comparator 39 becomes "0".

At the same time, the load signal (xL7i5) is inverted by the inverter 44 and supplied to the count input terminal of the counter 21 as a count amplifier signal (YCNTUP) shown in FIG. 5(0). This allows the counter 21 to count up. By the above operation, 12
Address signals necessary to transfer 47 minutes of pixel data are supplied to the memory from the output terminal 38.

As a result, the count value of the counter 21 changes as the first bit (YCNTl), second bit (YCNT2), and third bit (YcN'll"3) each time the count up signal (YCNTUP) is supplied. Figure 5 (P)
, (Q).

(R), and in the same way as above,
Address signals for each line are outputted in llffffl order.

The count value output of this counter 21 is r 00000101
J, the comparison signal (YCMP) of the comparator 41 shown in FIG. 5(8) becomes "1". Thereafter, the last address signal r0000010100000111J is output from the output terminal 38, and the output signal of the NAND circuit 40 becomes "0" as shown in FIG. At the same time as the 8-bit address signal is set, the output signal of this NAND circuit 40 becomes "1". As a result, the flip-flop 26 is reset and the DMA request signal (DMA EQ) becomes "0".
", the DMA enable signal (DMAACK2) output from the flip-flop 30 becomes "0", the address bus drivers 36 and 37 stop supplying address signals to the memory from their output terminals, and the data transfer ends.

In this way, by setting up the start address and end address once, the pixel data shown in the shaded area A in FIG. 1 can be transferred continuously at one time. For example, in FIG. 21i=5001 upper 21i=
Assuming that the backup time is 50 μs, the data transfer time for this 1000-'ite is 1050 (=50+2X500)
μs, which is significantly shorter than the conventional 2600 μs, and the ratio of setup time to less than 0.5%, greatly improving transfer efficiency.

FIG. 6 shows a block system diagram of a second embodiment of the apparatus of the present invention. In the figure, the CPU 50 starts executing the input/output command, and then calculates the number of 8-bit horizontal pixels of the transfer data (jK in Figure 1).
This number of pixels in the horizontal direction is set by supplying a load command which is "1" and "1" to the register 51, and then the lower 8 bits of the start address (corresponding to jo in FIG. 1) and "1" are supplied to the register 51.
1" is supplied to the register 52 to set the lower 8 bits of this start address. This load command to the register 52 is sent via the OR circuit 53 to the load terminal of the counter 54, which is supplied with the 8-bit output signal of the register 51, and to the load terminal of the counter 55, which is supplied with the 8-bit output signal of the register 52. The signal is supplied to the load terminal, and the number of pixels in the horizontal direction and the lower 8 bits of the start address are set in counters 54 and 55, respectively. Next, C.P.
U50 supplies the 8-bit vertical pixel count (corresponding to i in Figure 1) and a load command of "1" to the counter 56 to set it, and also supplies the upper 8 bits of the start address (corresponding to i in Figure 1) to the counter 56 and sets it. io) and a load instruction to the counter 57 to set it.

These counters 55 and 57 each supply the set 8-bit count value to the address bus driver 58.

After this, the CPU 50 issues a DMA start command (Ryota ST)
is supplied to the DMA control circuit 58. I-) The M A control circuit 59 receives this and supplies a D bi A request signal (]) MAREQ) which becomes "1" to the CPU 50.
U3O thereby supplies the DMA control circuit 59 and the address bus driver 58 with a DMA enable signal (to Kokusho) that becomes "1", and at the same time, the DMA request signal becomes "1".
”, the data bus 60 is abandoned for a period of time. While the DMA enable signal is "1", the address bus driver 58
The 8-bit count value from the address counter 55 is
A total of 16-bit address signals are supplied to the memory 61, with the 8-bit count value from the address counter 57 being the upper 8 bits. Furthermore, when the J)MA enable signal from the CPU 50 becomes "1", the DMA control circuit 59 generates a 1H]A timing pulse (DMAT IN) synchronized with the clock pulse (CLK) that is fully supplied from the CPU 50.
I NG ) is generated and supplied to the counting terminals of the counters 54 and 55, respectively. Counter 55 counts up D by 4A timing pulse and supplies the 8-bit count value to address bus driver 58.

Further, the counter 54 is cooled to count by the DMA timing pulse, and the count value is roooo 0OO
When OJ is reached, that is, when the address signal of one horizontal line is supplied to the memory 61, a carry down signal (BORROW) which becomes "1" is generated and this is sent to the counters 56 and 5.
7, and an OR circuit 53.
The load terminals of the counters 54155 are supplied through the counters 54155. As a result, the counter 57 counts up,
The 8-bit count value is supplied to the address bus driver 58, and the counter 56 counts down.
The 8-bit output signals of the registers 51 and 52 are set again in the counters 54 and 55, and the next line of address signals can be supplied to the memory 61. In this way, when the count value of the counter 56 becomes roooo 0OOOJ, that is, when the address signal of the last 1u/f is supplied to the memory 61, the counter 56 outputs a signal below the digit that is "°1". (BOILROVv) is generated and supplied to the LIMA control circuit 59. When the downshift signal from the counter 56 becomes "1", the DMA control circuit 59 sets the DMA request signal to "0", thereby causing the CPU 50 to output the DMA enabled No. 8 HrOJ. The address bus driver 58 stops supplying the address signal to the memory 61, and the data transfer ends.

In this embodiment as well, by setting up the start address and the number of pixel data only once, pixel data as shown in the shaded area A in FIG. 1(5) can be continuously transferred at one time.

In the above embodiment, the start address is the vertex (lo, Jo) in FIG. 1, and the end address is the vertex (j+, J
+), but the start address is another m point C'o +
J+) + (It + Jo) + (1+ +J+
), and in this case, the end address is the vertex opposite to the start address, which is the - vertex of the quadrilateral in the shaded area A, and each counter may be counted up or down accordingly. , but is not limited to the above embodiments.

In addition, in the above embodiment, the address is m=n=8゜q=16
However, this may be m 4 = n, and
95m -1-n, and is not limited to the above embodiment.

As described above, the data transfer device according to the present invention has pixel data of one screen that is divided into 'l (m is a positive integer) pixels or less in the vertical direction and into 2 (n is a positive integer) pixels or less in the horizontal direction. q
In a data transfer device that writes to or reads from a memory that is accessed using (q≧m+n) bit addresses, the address of the memory is lower n
The bits are sequentially changed from the lower n bits of the start address corresponding to the m points of the quadrilateral to the lower n bits of the end address corresponding to the peak of the quadrilateral, and the upper n bits of the memory address (q -n) bits are sequentially changed from the upper (q −n) bits of the start address (or end address) to the upper (q−n) bits of the end address (or start address), the lower n bits of the above memory address are changed sequentially. In order to transfer pixel data by supplying addresses to the memory by repeating sequential changes, multiple lines of pixel data are consecutively set up with a start address and an end address, or a start address and the number of pixel data. It has the advantage that it can be transferred in one go, the transfer time can be shortened, and the transfer efficiency can be improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the arrangement of pixel data constituting one screen,
FIG. 2 is a diagram schematically showing the arrangement of pixel data in the shaded area shown in FIG. 1 on the memory, FIG. 3 is a block diagram of an example of a conventional data transfer device, and FIG. The circuit diagram of the first embodiment, FIG. 5(8) to G) are waveform diagrams of various parts of the device shown in FIG. 4, and FIG. 6 is a block system diagram of the second embodiment of the device of the present invention. 10.11, 18, 20, 22, 24, 28°29...
・Input terminal, 12, 15, 17, 31, 34°42.4
4... Inverter, 13, 19.23°51.52.
...Register, 14,21.54-57...Counter, 25.59...DMA control circuit, 26°30.32
...Flip-flop, 27.38...Output terminal,
33.35.40.43... NAND circuit, 36.37
．． 58...Address bus driver, 39°41...
Hikyoki, 53...OR circuit, 61...memory. Figure 1 Figure 2

Claims (1)

[Claims] A pixel take of one screen divided into 2 m (m is a positive integer) pixels or less in the vertical direction and 2° (n is a positive integer) pixels in the 4V4 direction is accessed with a q (q≧m+n) bit address. When transferring pixel data of a quadrilateral area surrounded by the horizontal and vertical axes of the screen in a data transfer device that writes or outputs data into a memory, the lower n addresses of the memory are transferred to the quadrilateral area. From the lower n bits of the start address corresponding to the vertex of - to the lower n bits of the end address corresponding to the vertex opposite to the vertex of -, the upper (q-n) bits of the memory address are Every time the upper (qll) bits of the start address (or end address) are changed sequentially to the upper (qn) bits of the end address (or start address), the lower 1 bit of the memory address is sequentially changed. A data transfer device characterized in that pixel data is transferred by repeatedly supplying an address to the memory.