JPH01305769A - Picture reducing device - Google Patents

Abstract

PURPOSE:To obtain a reduced picture at high speed by storing neighboring lines to form a picture as scattering them over plural memories, and accessing the memories at a time in a case to read them out for reduction. CONSTITUTION:The lines 1-1024 to form the picture are stored in the memories 1-4, and a picture read-out device 9 outputs an address 12 to an address bus 11 and permission signals 1-4 to an output permission signal controller 10 in order to read out the lines at a time. Accordingly, the data of the lines 1-4 are outputted at a time to the outputs 1-4 of the memories 1-4. A reducing device 106 receives the data of these lines 1-4 at a time, and outputs result data 107. Next, the device 9 outputs the address 108 to the bus 11, and outputs the permission signal to the controller 10, and the result data is obtained. Thus, the number of times of addressing is decreased, and the reduced picture is obtained at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image reduction device that performs reduction operations on an original image and outputs a reduced image.

[Summary of the invention]

The present invention includes a plurality of memories for storing images, an image readout device that generates an address for reading the memories, and an output permission signal controller that generates a permission signal to permit output of the plurality of memories. , a reduction device that performs reduction operations on multiple image data output from multiple memories and outputs a reduced image, and reads out adjacent line images distributed and stored in multiple memories simultaneously in one memory cycle. An image reduction device that is characterized by being able to quickly obtain reduced images by performing reduction operations.
It is.

[Conventional technology]

The configuration of the image memory in a conventional image reduction device is as follows:
It consisted of a block diagram as shown in FIG. 3, and operated according to a time chart as shown in FIG.

A conventional image reduction device will be described below with reference to FIGS. 3 and 4.

The signals shown in FIG. 4 have the same signal names and numbers as the signals shown in FIG.

Conventionally, an original image before reduction is divided into lines that make up the image, and adjacent lines are stored in the same memory. For example, line I (35) at the beginning of the image,
Line 2 (36), Line 3 (37), Line 4
(38) was stored in the same memory 1 (31).

Therefore, when attempting to reduce these four lines, the output permission signal controller 39 uses memory 1 (31
), and as shown in Figure 4, address a (41) to access line 1 (35), line 2
Address b (42) for accessing (36),
Address c for accessing line 3' (37)
(43).

Address d( to access line 4 (3B)
44) is sequentially generated by the image reading device (45) on the image address bus (46). The output data according to this is the line l data (4B) on the image data bus (47).
.

Line 2 data (49) Line 3 data (50),
Line 4 data (51) is output sequentially, and these are sent to register 1 (52) and register 2 (53), respectively.
, register 3 (54), register 4 (55)
These total outputs r1 output (56), r2 output (57), r 3 (58), r 4 output (5
9) is received by a reduction device (60), which performs a reduction operation to obtain a result output (61).

That is, according to the conventional technology, when attempting to read and reduce multiple image data line by line, memory access for the number of lines is required, and for example, when reducing 4 lines to 1 line, 4 times as many memory accesses are required. It required memory cycles to operate.

A similar operation is performed when a microprocessor performs a reduction operation.

[Problem to be solved by the invention]

For this reason, in the conventional apparatus, in order to reduce an image, it always takes a memory cycle time equal to the number of read lines, so it was not possible to reduce the image at high speed.

An object of the present invention is to provide a configuration in which memory addressing, which conventionally had to be done multiple times for reduction, can be done only once or by a fraction of the conventional amount.

[Means to solve the problem]

In order to achieve the above object, the image reduction device of the present invention has the following features:
Adjacent lines constituting an image are stored in a distributed manner on a plurality of memories, and these memories are configured so that they can be accessed simultaneously when reading for reduction.

[Effect]

Therefore, in the present invention, adjacent lines constituting an image can be read out simultaneously, and a reduced image can be obtained at high speed.

〔Example〕

Hereinafter, the present invention will be explained in detail based on FIGS. 1 and 2.

FIG. 1 is a block diagram of the present invention, and FIG. 2 is a time chart of an embodiment of the present invention.

Note that the signal names and numbers used in FIG. 2 are made to match the signal names and numbers in FIG. 1.

Lines 1 to 1024 that make up the image as shown in Figure 1
are sequentially stored in the memory Ifll, the memory H2+, the memory 3 (31, and the memory 4 (4)).The image reading device 9 reads the line 1 (51, Line 2t61. Line 3f7
1. A permission signal, permission 1 (13), which outputs address a (12) to the image address bus 11 in order to simultaneously read line 4 (8), and also allows the output permission signal controller 10 to output all memory, permission 1 (13), permission 2(
14), permission 3 (15), and permission 4 (16).

Then, output 1 (17) of memory 1 (1) to memory 4 (4)
), output 2 (18), output 3 (19), output 4 (10
0), line 1 data (101), line 2 data (102), line 3 data (103), and line 4 data (104) are output simultaneously as shown in FIG.

The reduction device (106) converts these line 1 data (10
1) ~ Line 4 data (104) are simultaneously received and result data 105 is output to result output 107.

Next, the image reading device 9 outputs the address a+1 (10B) onto the image address bus 11, and continues to operate the output permission signal controller 10 to permit output of the entire memory. By continuing the operations as explained above, the reduction result data of the entire screen is obtained.

In this embodiment, the lines constituting the image are distributed and stored in four memories, but the present invention is not limited by the number of memories. Furthermore, even when attempting to reduce 8 lines by using 4 memories, for example, only 2 memory cycle times are required, which is still superior to the conventional method.

〔Effect of the invention〕

As explained above, in the present invention, by distributing and storing adjacent lines constituting an image in a plurality of memories in advance, the multiple memory cycles required to create a reduced image can be saved in one time or in the conventional method. Since the reduction can be reduced to a fraction of -, a high-speed image reduction device can be constructed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram of an embodiment of the present invention, FIG. 3 is a block diagram of a conventional technique, and FIG. 4 is a time chart of a conventional technique. 1, 2.3.4... Memory 9... Image reading device 10... Output permission signal controller 106.
...Applicant for reduction devices and above Seiko Electronic Industries Co., Ltd. Patent attorney Keinosuke Hayashi

Claims (1)

[Scope of Claims] A plurality of memories for storing images, an image reading device that generates an address for reading the memories, and an output permission that generates a signal for simultaneously permitting output of the plurality of memories. Consisting of a signal controller and a reduction device that performs reduction calculations on a plurality of image data simultaneously output from the plurality of memories and outputs a reduced image, and converts adjacent line images distributed and stored in the plurality of memories. An image reduction device characterized in that a reduced image can be obtained at high speed by simultaneously performing reading and reduction calculations.