JP2938226B2 - Image scaling processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image magnification processing apparatus such as a digital copying machine which executes real-time enlargement / reduction processing of an input image signal in a main scanning direction. The present invention relates to an image scaling processing apparatus such as a digital copying machine that executes enlargement / reduction processing in the main scanning direction and italic processing using the same line memory.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram showing a basic configuration example of a conventional main-scanning direction variable-magnification processing apparatus. In the figure, reference numeral 801 denotes a reduction processing unit for reducing an input image; Reference numeral denotes an enlargement processing unit that reads out image data from the line memory 102, performs enlargement processing, and then outputs an image.

[0003] The conventional main-scanning-direction magnification changing device configured as described above stores an input image signal in a line memory 1.
When writing to the line 02, reduction processing including the same magnification is performed by the reduction processing unit 801, and when reading from the line memory 102, enlargement processing including the same magnification is executed by the magnification processing unit 802 to output an image. Further, in the above-described main scanning direction magnification change processing apparatus, in order to realize real-time switching of enlargement / reduction processing, switching between the same magnification / reduction processing at the time of writing and switching between the same magnification / reduction processing at the time of reading are performed. Had to be controlled independently of each other.

FIG. 9 is an explanatory diagram specifically showing an example of the above image processing. First, as shown in (a), an image signal obtained by raster-scanning an original and reading is input. Next, the input image signal is processed in a state where enlargement processing and reduction processing in the main scanning direction are mixed as shown in FIG.
In this case, in order to obtain a desired image signal, as shown in the time chart of FIG.
The switching of the reduction processing is executed, and the image signal of the format shown in the intermediate state is written to the line memory 102, and the magnification / expansion processing is performed by the enlargement control signal when reading the image signal.

FIG. 10 is a block diagram showing a configuration example of a conventional main-scanning-direction variable-magnification processing apparatus and an italic processing apparatus. In the figure, reference numeral 1001 denotes a scaling processor that executes scaling processing for reduction / enlargement of an input image signal, 1002 denotes a line memory for the scaling processor 1001 that stores an image signal, and 1003 denotes writing in the line memory 1002. And an address control unit for controlling reading.

Reference numeral 1004 denotes an italic processing apparatus for executing italic processing, 1005 denotes a line memory for the italic processing apparatus 1004 for storing image signals, and 1006 denotes a line memory 1
005 is an address control unit that controls writing and reading.

In the conventional main-scanning direction magnification processing device and the oblique processing device configured as described above, when the magnification processing is performed, the address control unit 1 is controlled by the magnification processing device 1001.
At 003, the image signal of the line memory 1002 was written and read based on the instruction to execute the reduction / enlargement magnification processing. Further, when performing the italic processing, the italic processing apparatus 1004 writes and reads the image signal of the line memory 1005 based on the instruction of the address control unit 1006 to execute the italic processing.

[0008]

However, in the above-described main-scanning-direction variable-magnification processing apparatus, switching of processing in the reduction processing unit including the same magnification and enlargement of the enlargement processing unit including the same magnification are performed. Since the switching of the processing is controlled independently, there is a problem that the control is complicated.

Further, in the conventional main-scanning-direction variable magnification processing apparatus and italic processing apparatus as described above, the main-scanning-direction variable magnification processing apparatus and the italic processing apparatus are each constituted by separate devices. Since each process is performed by each device, there is a problem that the configuration becomes highly redundant and the circuit configuration becomes complicated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and enables easy enlargement and reduction processing and real-time switching of a magnification ratio when image processing in which enlargement / reduction processing is mixed is performed in real time. This is the first object.

Further, the present invention has been made in view of the above, and an object of the present invention is to make it possible to execute scaling processing and italic processing in the main scanning direction with a configuration having no redundancy and a simple circuit configuration. This is the purpose of 2.

[0012]

According to the present invention, in order to achieve the above object, a line memory for storing an input image signal and an enlargement / reduction process are executed when the image signal is read from the line memory. An image scaling processing device comprising: a reciprocal output unit that outputs a reciprocal of a preset scaling ratio;
Address generating means for accumulating the output of the reciprocal output means and outputting a read address signal using a value obtained by accumulative addition, wherein the address generating means outputs a read address signal based on the read address signal output from the address generating means. By reading the image signal from the line memory, the enlargement / reduction processing is executed, and every time the pixel synchronization signal is input, the address generation means outputs the read address signal using the value obtained by the cumulative addition. Performing a process of cumulatively adding the output of the reciprocal output means, and initializing the value obtained by the cumulative addition each time a line synchronization signal is input, using an arbitrary initial value. , A process of accumulating the output of the reciprocal output means is performed, and a different value can be used as the initial value each time the line synchronization signal is input. It is intended to provide some image scaling processing apparatus.

According to the present invention, there is provided an image scaling process comprising: a line memory for storing an input image signal; and a scaling unit for executing a scaling process when reading the image signal from the line memory. A magnification change output means for outputting a preset magnification, and a first change amount for changing a magnification in the main scanning direction as the sub-scanning direction progresses. First adding means for cumulatively adding the outputs of the first change amount output means and outputting the addition result each time the first change amount output means and the line synchronization signal are input, and / or the main scanning direction The output of the second change amount output means for outputting a second change amount for changing the magnification in the main scanning direction and the output of the second change amount output means each time the pixel synchronization signal is input Add A reciprocal output for adding the outputs of the second addition means for outputting the calculation result, the scaling ratio output means, the first addition means and / or the second addition means, and obtaining and outputting the reciprocal of the addition result Means, address generating means for cumulatively adding the output of the reciprocal output means, and outputting a read address signal using a value obtained by the cumulative addition;
And an image scaling processing device that executes the enlargement / reduction processing by reading an image signal from the line memory based on a read address signal output from the address generating means.

Further, according to the present invention, the variable magnification output means includes:
The output magnification can be changed at an arbitrary timing, the first change amount output means can change the output first change amount at an arbitrary timing, and the second change amount output unit can change the output first change amount at an arbitrary timing. Is an image scaling processing apparatus capable of changing the output second change amount at an arbitrary timing.

Further, according to the present invention, each time the address generation means inputs a pixel synchronization signal, the address generation means outputs a read address signal using the value obtained by the cumulative addition, and outputs the output of the reciprocal output means. A process of performing cumulative addition is performed, and each time a line synchronization signal is input, a value obtained by performing the cumulative addition is initialized using an arbitrary initial value, and an output of the reciprocal output unit is output with respect to the initial value. It is an object of the present invention to provide an image scaling processing device that performs a process of accumulating and that can use a different value as the initial value each time the line synchronization signal is input.

Further, according to the present invention, the scaling processing means further includes an address setting means for setting an address serving as an effective image area, an address set by the address setting means, and an output from the address generating means. Comparing the read address signal with a read address signal, and determining whether an address represented by the read address signal corresponds to an image signal outside the effective image area. It is an object to provide an image scaling processing device that outputs a white image signal when it is determined that the image signal corresponds to an outside image signal.

[0017]

In the above arrangement, the input image signal is written to the line memory. The image signal written in the line memory is subjected to enlargement / reduction processing by the scaling processing means when it is read next, and is output. Specifically, a reciprocal of a predetermined magnification is calculated, the obtained reciprocal is cumulatively added, and a read address signal is output using the value obtained by the cumulative addition. Then, by reading the image signal from the line memory based on the read address signal, it is possible to output the image signal subjected to the enlargement / reduction processing. At this time, every time a pixel synchronization signal is input,
A read address signal is output using the value obtained by the cumulative addition, and a process of cumulatively adding the reciprocal of the scaling factor is executed. Here, every time a line synchronization signal is input, a process of initializing a value obtained by cumulative addition using an arbitrary initial value is performed, and based on this value, an output process of a read address signal and a scaling factor A process of cumulatively adding the reciprocal is performed. As the initial value, a different value can be used each time a line synchronization signal is input. If a different initial value is set for each line, italic processing can be realized.

Further, the first change amount for changing the magnification in the main scanning direction as the line advances in the sub-scanning direction is cumulatively added every time the line synchronization signal is input, and / or the main amount changes in the main scanning direction. The second change amount for changing the magnification in the scanning direction is cumulatively added every time a pixel synchronization signal is input, the cumulatively added value and an arbitrary predetermined magnification are added, and the reciprocal of the result of the addition is added. Is output. The output reciprocals are cumulatively added, and a read address signal is output using a value obtained by the cumulative addition.

Also, the scaling ratio output by the scaling ratio output means,
The first change amount output by the first change amount output unit and the second change amount output by the second change amount output unit can be changed at any timing, and the magnification of the image can be changed arbitrarily. Can be done.

Each time a line synchronizing signal is input, a process for initializing a value obtained by cumulative addition using an arbitrary initial value is performed, and based on this value, an output process of a read address signal and a change are performed. Processing for cumulatively adding the reciprocal of the magnification is executed. At this time, a different value can be used as the initial value every time the line synchronization signal is input. If a different initial value is set for each line, italic processing can be realized.

Further, the address which becomes the effective image area set by the address setting means is compared with the read address signal output from the address generation means, and a white image signal is output.

[0022]

An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a main configuration example of an image scaling processing device according to the present invention. In the figure, 10
Reference numeral 1 denotes an equal-magnification processing unit that performs an equal-magnification process on an input image signal and outputs the same; 102, a line memory for writing an image signal output from the equal-magnification processing unit 101; An enlargement / reduction processing unit that executes magnification / reduction scaling processing when reading out a signal and outputs an image.

The image scaling processing apparatus configured as described above performs predetermined processing on the image signal by the equal-size processing unit 101 and then writes the image signal into the line memory 102. When the image signal written in the line memory 102 is read next, the enlargement / reduction processing unit 103 simultaneously performs enlargement / reduction processing on the image signal, and outputs the image signal. As described above, the image signal input from the outside is written in the line memory 102 as it is, and the address when the image signal is read from the line memory 102 is obtained from the result of accumulating the reciprocal of the scaling factor.
Image processing such as enlargement / reduction corresponding to the variable magnification can be performed.

FIG. 2 is a circuit diagram showing a detailed configuration example of the image scaling processing apparatus according to the present invention.
And 202 are buffers for temporarily storing input image signals, 203 and 204 are selectors for outputting read address signals and write address signals, and 205 and 206
Is an SRAM (static RAM) capable of storing image signals for one line or more, 207 is an F / F (flip-flop) operated by the line synchronization signal LS, and 208 is cleared by the line synchronization signal LS and counts the pixel synchronization signal CK 209 is a write address signal, 209
10 is a read address signal, 211 is S by a signal S2.
A selector for outputting an image signal output from the RAM 206 to the outside.

Numeral 212 denotes a variable-magnification output circuit for outputting the reciprocal of the magnification, and numeral 213 denotes an address generating circuit which operates according to the output of the variable-magnification output circuit 212 and outputs a read address signal 210. Numeral 214 denotes a scaling register for outputting a fixed scaling ratio. A plurality of scaling ratio data is set in advance by a SET signal from a CPU (not shown), and this data is stored in an area control unit (not shown). Selected by the signal A1 output from the
4 is output. 215 is an image frame synchronization signal F
The accumulator circuit 216 for accumulating and adding the output of the sub-scanning direction tilt register 216 every time the line synchronization signal LS is input after being cleared by S outputs a change amount when the main scanning direction magnification is changed in the sub-scanning direction. A plurality of change amount data is set in advance by a SET signal from a CPU (not shown), and this data is selected by a signal A2 output from an area control unit (not shown). , From the sub-scanning direction tilt register 216.

An accumulation circuit 217 is cleared by the line synchronization signal LS and accumulates and adds the output of the main scanning direction tilt register 218 every time the pixel synchronization signal CK is input. This is a main scanning direction inclination register for outputting a change amount when the magnification is changed. A plurality of change amount data are set in advance by a SET signal from a CPU (not shown), and these data are stored in an area control circuit. (Not shown) and is output from the main scanning direction tilt register 218.

An adder 219 adds the data output from the scaling register 214, the accumulating circuit 215 and the accumulating circuit 216 and outputs an actual scaling factor, and 220 denotes a scaling factor output from the adder 219. This is a division circuit that outputs a reciprocal. Reference numeral 221 denotes a selector for selecting a shift amount (initial value) signal SH output from a CPU (not shown) to the address generation circuit 213; 222, an F / F (flip-flop) of the address generation circuit 213; This is an adder that performs cumulative addition each time the pixel synchronization signal CK is input to the address generation circuit 213.

Numeral 224 denotes an erase control circuit for judging the outside of the image area. Numeral 225 designates a minimum address value indicating an effective range in the main scanning direction in an input image set by a SET signal from a CPU (not shown). The minimum value register 226 stores the maximum address value indicating the effective range of the input image in the main scanning direction in SE from the CPU (not shown).
The maximum value register 227 set by the T signal determines that the read address signal 210 is outside the image area when the read address signal 210 is smaller than the set value of the minimum value register 225.
A comparator 228 that outputs a signal outputs a H signal that determines that the read address signal 210 is out of the image area when the read address signal 210 is larger than the set value of the maximum value register 226, and a comparator 229 outputs an H signal that is output from the comparators 227 and 228. An OR gate that performs a logical sum (OR) process on the H signal indicating the outside of the image area to be output.

The operation of the circuit diagram of the image scaling processing device according to the present invention configured as described above will be described. In the figure,
When the signal S1 of the buffers 201 and 202 is H and the signal S2 is L, the image signal input from the outside is output to the SRAM 205 by the buffer 201. The output of the buffer 202 is in a Hi impedance state. Since the counter 208 is cleared by the line synchronization signal LS and counts the pixel synchronization signal CK, its outputs, the write address signal 209 and the read address signal 21 are output.
0 is input to the selector 203 and the selector 204, respectively.

The selector 203 outputs a write address signal 209 to the SRAM 205 according to the signal S1. SRAM
205 writes the image signal output from the buffer 201 to the address indicated by the write address signal 209 by the OR output of the pixel synchronization signal CK and the signal S2. In addition, SRAM2
The output of 05 becomes Hi impedance state by the signal S1.

The selector 204 outputs a read address signal 210 to the SRAM 206 according to the signal S2. As a result, the SRAM 206 is enabled to output by the signal S2, and the SRAM 206 outputs the image signal of the address indicated by the read address signal 210 to the selector 211. The selector 211 outputs the image signal output from the SRAM 206 to the outside in response to the signal S2.

In the above, when the signal S1 is L and the signal S2 is H, the operation is the reverse of that described above. That is, the image signal input from the outside is transferred to the SRAM 20 via the buffer 202.
6 is written to the address indicated by the write address signal 209. Further, the image signal of the address indicated by the read address signal 210 is read from the SRAM 205,
Output to the outside via the selector 211.

The read address signal 210 is output from an address generation circuit 213 that operates in response to the output of the magnification output circuit 212 and the like. A plurality of magnification data are written in advance in the magnification output circuit 212 by a signal SET from a CPU (not shown) for controlling the entire apparatus, and these data are output from an area control unit (not shown). It is selectively output by the signal A1.

The data output from the scaling register 214, the accumulating circuit 215 and the accumulating circuit 217 are added to an adder 219.
And the actual scaling factor is obtained, and the reciprocal of the scaling factor output from the adder 219 is obtained by the dividing circuit 220.

The reciprocal of the magnification output from the magnification output circuit 212 is determined by the selector 22 of the address generation circuit 213.
Each time the pixel synchronizing signal CK is input by the F / F 222 and the adder 223, they are cumulatively added. However, at this time, when the line synchronization signal LS is input, the selector 221 sets C
A shift amount (initial value) signal SH output from a PU (not shown) is selectively output, and the accumulated value held in the F / F 222 is initialized by the shift amount (initial value) signal SH. The output as the read address signal 210 is for the integer part of the accumulation result.

As described above, the image signal input from the outside is written to the line memory 102 as it is, and the address when the image signal is read out from the line memory 102 is obtained from the result obtained by accumulating the reciprocal of the scaling factor. Image processing such as enlargement / reduction corresponding to the magnification can be performed. Switching between the enlargement / reduction processing can be performed by indirectly selecting the reciprocal of the magnification ratio by selecting the output of the magnification ratio register 214. Furthermore, since the read address is calculated every time the pixel synchronization signal CK is input, real-time scaling processing can be performed.

The address generation circuit 21 shown in FIG.
No. 3, since the accumulated value of the read address is initialized to the shift amount (initial value) signal SH by the line synchronization signal LS,
The CPU (not shown) dynamically controls the shift amount (initial value) signal SH to realize the italic processing.

Next, the erase control circuit 224 is a circuit for judging the outside of the image area. The erase control circuit 224 supplies the minimum address value indicating the effective image range in the main scanning direction of the image input to the minimum value register 225 and the maximum value register 226. The maximum address value is set in advance by a signal SET from a CPU (not shown).

The comparator 227, the comparator 228, and the OR gate 229 provide an effective image when the read address signal is smaller than the minimum address set in the minimum value register 225 and the maximum address register 226 or larger than the maximum address. It determines that the signal is out of the area and outputs an H signal to the selector 211. Thus, when the output of the OR gate 229 becomes H, the selector 211 outputs a white image signal regardless of other inputs.

In the circuit shown in FIG.
12 and the shift amount (initial value) signal SH, there is a possibility that the effective image range in the main scanning direction in the output image changes for each line. In this circuit, as described above, the effective image range from the SRAM 205 or the SRAM 206 is changed. When reading an image signal outside the area, the erase control circuit 2
Since a white image signal is output by the selector 24 and the selector 211, the image outside the effective image area is subjected to the erasing process and output. This eliminates the need to add a circuit for controlling the amount of erase in the main scanning direction for each line.

The accumulating circuit 215 and the accumulating circuit 217 in the scaling output circuit 212 shown in FIG. 2 execute the cumulative addition every time the pixel synchronizing signal CK is inputted. May be configured to perform cumulative addition each time a signal obtained by thinning out the above signal is input.
In this case, the same function can be obtained even if the number of bits of data set in the sub-scanning direction tilt register 216 and the main scanning direction tilt register 218 is reduced, or the calculation accuracy of the accumulating circuits 215 and 217 is lowered. . As a result, the circuit can be simplified.

FIG. 3 is an explanatory diagram showing the output format of the division circuit 220 according to the present invention. As shown in FIG.
The signal output by 0 is output as signed fixed-point data.

FIGS. 4A and 4B are explanatory diagrams showing the reduction / enlargement processing according to the present invention. FIG. 4A shows the reduction processing, and FIG. 4B shows the enlargement processing. In the reduction processing of FIG. 4A, the reciprocal 1 / xa of the scaling factor is 1 / xa> 1, and the read address for accumulatively adding the reciprocal 1 / xa has a higher traveling speed with respect to the input image. As a result, the output image is smaller than the input image, and the reduction process is realized.

Also, in the enlargement processing of FIG. 4B, the reciprocal 1 / xb of the scaling factor becomes 1 / xb <1, and the reciprocal 1 / xb
The read address for cumulatively adding b has a slower moving speed with respect to the input image. As a result, the output image is larger than the input image, and the enlargement process is realized. still,
The scaling factors in this case are xa and xb, respectively.

Also, in FIG.
Since the reciprocal of the scaling factor output from 2 can take both positive and negative values, the address generation circuit 213 for cumulatively adding the reciprocal of the scaling factor output from the scaling output circuit 212 outputs the read address signal 210 to be output. You can proceed in the minus direction. Thereby, mirror image processing is realized by reversing the arrangement of the input image signal in the main scanning direction and outputting the image signal to the outside.

FIG. 5 is an explanatory diagram showing a processing example of the accumulation circuit 215 and the sub-scanning direction tilt register 216 according to the present invention. In the figure, (a) shows the original to be scaled, (b) sets the output of the scaling register 214 to 50% for this original, and the sub-scanning direction tilt register 216
4 shows an output image when the processing is performed with the output of δ set to δ (δ> 0). As a result, an image is obtained in which the magnification in the main scanning direction is linearly increased as the processing proceeds in the sub-scanning direction.

FIG. 5 (c) shows the processing of the above (b),
It is a trapezoidal image obtained by adding an operation performed by a CPU (not shown) to control the shift amount (initial value) signal SH. If the output δ of the sub-scanning direction tilt register 216 is set to a negative value and the processing is performed, the magnification can be linearly reduced as the processing proceeds in the sub-scanning direction. FIG. 5D shows an output image when two types of data are set in the sub-scanning direction tilt register 216 and these are switched during the processing.

Also, as shown in FIG. 2, in the circuit of the image scaling processing device, the scaling factor is obtained by the adder 219 and then converted into the reciprocal by the dividing circuit 220, so that the scaling factor can be linearly increased or decreased. It has become. On the other hand, an image obtained by processing with the configuration in which the division circuit 220 is removed is shown in FIG.
(E), and a non-linear (proportional to 1 / x) gradient scaling process is realized. Further, by switching the function of the division circuit 220, image processing as shown in FIGS. 5A to 5E becomes possible.

FIG. 6 is an explanatory view showing an example of tilt magnification and mirror image processing according to the present invention. The accumulating circuit 217 and the main scanning direction tilt register 218 enable tilting magnification change as the processing proceeds in the main scanning direction as described above. FIG. 6 (a)
For example, by setting the output of the scaling ratio register 214 to 25% and setting the output of the main scanning direction tilt register 218 to δ (δ> 0),
The magnification is changed according to the progress of the processing in the main scanning direction as shown in FIG. 6B, and the image shown in FIG. 6C is output.

In the above description, the scaling ratio register 21
4 is set to 150%, and the output of the main scanning direction tilt register 218 is set to δ (δ <0), so that the magnification is changed as shown in FIG. An image which becomes a mirror image during output as shown is obtained.

FIG. 7 is a timing chart of each part showing the operation corresponding to the circuit diagram of the image scaling processing apparatus shown in FIG.

As described above, according to the image scaling processing apparatus of the present invention shown in FIG. 2, the switching of the scaling ratio by the scaling ratio register 214, the accumulation circuit 215 and the sub-scanning direction tilt register 216 are performed. To change the tilt in the sub-scanning direction and switch the tilt. In addition, accumulation circuit 2
17 and the main scanning direction tilt register 218 can perform tilting magnification changing in the main scanning direction and switching processing thereof, and can execute italic processing based on the shift amount (initial value) signal SH and mirror image processing using the sign of the reciprocal of the scaling factor. . Furthermore, by combining and controlling them arbitrarily, special scaling processing of various kinds of images is realized.

[0053]

As described above, according to the image scaling processing apparatus of the present invention, when the input image signal is written to the line memory and then the image signal is read from the line memory, the enlargement / reduction processing is performed. Since the switching of the enlargement / reduction processing can be centrally managed by executing the processing, it is possible to easily perform the enlargement / reduction processing and to switch the real-time magnification in the case where the image processing including the enlargement / reduction processing is performed in real time.

Further, by controlling the writing and reading of the input image signal to and from the line memory, the scaling process and the oblique process in the main scanning direction are performed using the same line memory, and the input image signal is When the image signal is read from the line memory to be stored, the address signal is controlled to perform the scaling process, and the shift amount (initial value) of the address signal is set for each line to execute the italic process. It is possible to execute the scaling processing and the italic processing in the main scanning direction with a simple configuration and a simple circuit configuration. Specifically, an arbitrary shift amount set every time a line synchronization signal is input is set as an initial value, and a read address signal is obtained by cumulatively adding a reciprocal of a scaling factor to the initial value to obtain a read address signal. Since a different value can be used for each line, a simple circuit configuration is used to read / enlarge an image signal from a line memory.
Reduction processing and italic processing can be executed.

Further, the first change amount for changing the magnification in the main scanning direction as the scanning advances in the sub-scanning direction is cumulatively added every time the line synchronization signal is input, and / or the main control unit changes in the main scanning direction. The second change amount for changing the magnification in the scanning direction is cumulatively added every time a pixel synchronization signal is input, the cumulatively added value and an arbitrary predetermined magnification are added, and the reciprocal of the result of the addition is added. Are accumulated to obtain a read address signal. Therefore, with a simple circuit configuration, when reading an image signal from a line memory,
A reduction process and a deformation process to a desired shape can be executed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main configuration of an image scaling processing device according to the present invention.

FIG. 2 is a block diagram showing a detailed circuit configuration of the image scaling processing device according to the present invention.

FIG. 3 is an explanatory diagram showing an output format of the division circuit shown in FIG.

FIG. 4 is an explanatory diagram showing reduction and enlargement processing according to the present invention.

FIG. 5 is an explanatory diagram showing a processing example of an accumulation circuit 215 and a sub-scanning direction tilt register 216 shown in FIG. 2;

FIG. 6 is an explanatory diagram showing an example of tilt magnification and mirror image processing according to the present invention.

FIG. 7 is a timing chart illustrating the operation of each unit corresponding to the circuit configuration of the image scaling processing apparatus illustrated in FIG. 2;

FIG. 8 is a block diagram showing a basic configuration of a conventional main-scanning direction variable magnification processing apparatus.

FIG. 9 is an explanatory diagram showing a conventional example of image processing control.

FIG. 10 is a block diagram showing a schematic configuration of a conventional main-scanning direction variable-magnification processing apparatus and an italic processing apparatus.

[Explanation of symbols]

102 line memory 103 enlargement /
Reduction processing unit 210 Read address signal 212 Variable magnification output circuit 213 Address generation circuit 214 Variable magnification register 219 Adder 220 Divider circuit 223 Adder 224 Erase control circuit 225 Minimum value register 226 Maximum value register 227 Comparator 228 Comparator

Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) G06T 3/40 H04N 1/387-1/393 G09G 5/36 B41J 2/485-2/52

Claims (5)

(57) [Claims] 1. An image scaling processing apparatus comprising: a line memory for storing an input image signal; and scaling processing means for executing a scaling process when reading the image signal from the line memory. The scaling processing means includes a reciprocal output means for outputting a reciprocal of a preset scaling factor, and an output of the reciprocal output means being cumulatively added, and outputting a read address signal using a value obtained by the cumulative addition. Address generating means, and reads an image signal from the line memory based on a read address signal output from the address generating means,
The enlargement / reduction processing is executed. Each time a pixel synchronization signal is input, the address generation means outputs a read address signal using the value obtained by the cumulative addition and outputs the output of the reciprocal output means. A process of performing cumulative addition is performed, and each time a line synchronization signal is input, a value obtained by performing the cumulative addition is initialized using an arbitrary initial value, and an output of the reciprocal output unit is output with respect to the initial value. An image scaling processing device which performs a process of accumulating and adding a different value each time the line synchronization signal is input as the initial value. 2. An image scaling processing apparatus comprising: a line memory for storing an input image signal; and scaling processing means for executing a scaling process when reading the image signal from the line memory. The scaling processing means includes a scaling output means for outputting a preset scaling, and a first output for outputting a first change amount for changing the scaling in the main scanning direction as the scanning proceeds in the sub-scanning direction. A first adding means for cumulatively adding the outputs of the first change amount output means and outputting the addition result each time the change amount output means and the line synchronizing signal are inputted, and / or a main addition means in the main scanning direction. The second change amount output means for outputting a second change amount for changing the magnification in the scanning direction and the output of the second change amount output means are cumulatively added each time a pixel synchronization signal is input. Output result Reciprocal output means for adding the outputs of the scaling factor output means, the first addition means and / or the second addition means, and obtaining and outputting the reciprocal of the result of the addition; Address generating means for accumulating the output of the reciprocal output means and outputting a read address signal using the value obtained by accumulative addition, wherein the line is generated based on the read address signal output from the address generating means. An image scaling processing device which executes the enlargement / reduction processing by reading an image signal from a memory. 3. The variable magnification output means can change the variable magnification to be output at an arbitrary timing, and the first change amount output means can change the first variable to be output at an arbitrary timing. 3. The image according to claim 2, wherein the second change amount output unit can change the output second change amount at an arbitrary timing. 4. Variable magnification processing device. 4. A process in which the address generating means outputs a read address signal using the value obtained by the cumulative addition every time a pixel synchronization signal is input, and also cumulatively adds the output of the reciprocal output means. And a process of initializing the value obtained by the cumulative addition using an arbitrary initial value each time a line synchronization signal is input, and cumulatively adding the output of the reciprocal output means to the initial value. 4. The image scaling processing apparatus according to claim 2, wherein a different value can be used as the initial value each time the line synchronization signal is input. 5. The variable magnification processing means further comprises: an address setting means for setting an address serving as an effective image area; an address set by the address setting means; and a read address signal output from the address generation means. Comparing means for determining whether an address represented by the read address signal corresponds to an image signal outside the effective image area. 2. A white image signal is output when it is determined that the above condition is satisfied.
5. The image scaling processing device according to any one of items 1-4.