JP3244687B2 - Image signal processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing device that performs image processing using image data read from an image memory.

[Conventional technology]

For image data input for each line, for example,
In order to perform an edge enhancement process or a smoothing process, an image data line to be processed and image data of a line before or after the image data line are stored, and by reading out the stored image data of a plurality of lines, a target image to be processed is stored. The image data of the pixel and the image data of the pixel near the target pixel are obtained.

That is, this type of image processing apparatus conventionally uses the same number of memory ICs 20, 21, and 22 as the number of lines that need to be stored in order to perform image processing, as shown in FIG. In the configuration of FIG. 8, it is assumed that image processing is performed by matrix operation using four pixels A, B, C, and D that are closer to the target pixel X than one line before and after as shown in FIG. Assuming that the line where the pixels C and D are present is on the (n + 2) th line, the image data latched to the D flip-flops 26 and 28 as the data of the pixels C and D is sampled by the clock as shown in FIG. The data is input to the arithmetic processing unit 41. As the X data, the image data which is stored in the memory 20 by the write signal E in the (n + 1) th line and is currently read out from the memory 20 on the (n + 1) th line and which is latched to the D flip-flop 30 as shown in FIG. Is selected by the selector 39 and input to the arithmetic processing unit 41. Similarly, A,
As shown in FIG. 9, the B data is stored in the memory 22 on the nth line in response to the two write signals, and is latched to the D flip-flops 35 and 37 of the image data two lines before currently read from the memory 22. The selected image data is selected by the selectors 40 and 38 and input to the arithmetic processing unit 41. The data processed by the processing unit 41 is f (A, B, C, D, X)
Is output as

The currently input image data of the (n + 2) th line is stored in the memory 21 by a write signal as shown in FIG. 9, and is processed as X data of the (n + 3) th line and A and B data of the (n + 4) th line. You. In FIG. 8, 27, 29, 31, 32 to 34, 36 are D flip-flops, and 23 to 25.
Is a tri-state buffer for controlling input of input image data to the memories 20 to 22, and 42 is a D flip-flop 26 to 37.
, A read / write address for the memories 20 to 22, a control signal for the tri-state buffers 23 to 25, a control signal for the selectors 38 to 40, and the like.

[Problems to be solved by the invention]

However, the conventional example described above is satisfactory in terms of image processing performance, but has some problems as follows.

(1) The circuit scale is large and the circuit is complicated.

(2) Since one memory IC is used for the image memory for one line, the use efficiency of the memory is low and the cost is high. (Example: In order to process image data with a resolution of 8 bits and 2.5K pixels, three general-purpose ICs require three 8 × 8 Kbit memories.) (3) Separate data for each memory Since the connection is made by a bus, the number of pins is large even if LSI is considered, which is difficult.

[Means for solving the problem]

According to a first aspect of the present invention, there is provided an image memory for performing writing and reading of image data continuously input in units of lines in accordance with an address signal, and processing means for performing a matrix operation using the image data read from the image memory. Address output means for outputting the address signal to the memory, while the address output means, while outputting a certain address, read the pixel data already stored at that address, Before the address output means updates the address, control means for writing pixel data of a succeeding line at the same pixel position as the read pixel data; and The pixel data necessary for the matrix operation, including pixel data of a subsequent line and pixel data read from the memory, And a holding means for holding the several lines of pixel data, the processing means, the pixel data for a plurality of lines held in said holding means for matrix operation.

Further, according to claim 2 of the present invention, a processing means for performing image processing of a pixel at a certain pixel position and a pixel located at a periphery of the pixel position; A number N required for use in the memory, a memory for storing, and address output means for outputting an address to the memory, the address output means, for each pixel position of the predetermined unit image data, Allocate an address group having N consecutive addresses,
When writing input image data to the memory,
For one predetermined unit, the address group is changed each time the pixel position changes, and each time the next predetermined unit is reached, the address in the address group is cyclically changed and the address is output. When reading from the memory, all the addresses of one group are output continuously, and then all the addresses of the next group are output.

EXAMPLES Hereinafter, the present invention will be described based on the configuration of a preferred example.

FIG. 2 is a schematic diagram of a document reading apparatus applied to the present invention.

In the figure, 401 is a platen glass, 402 is a bar-shaped light source such as a halogen lamp or a fluorescent lamp, 403 is a first mirror, 404 is a second mirror,
405 is a third mirror, 406 is a lens, 407 is a one-dimensional solid-state image sensor (image sensor) such as a CCD line sensor, and 408 is a white reference plane for shading correction.

The operation of the document reading apparatus will be described.
The original placed on top is illuminated by a rod-shaped light source 402 and scans (sub-scans) the original by a first mirror 403, a second mirror 404,
An image is formed on the image sensor 407 by the lens 406 via the third mirror 405. The main scanning direction of the image sensor 407 is a direction perpendicular to the drawing.

The rod-shaped light source 402 and the first mirror 403 are supported (not shown).
And scans the document surface while moving in the direction F in the figure by a guide rail (not shown) (sub-scanning). The second mirror 404 and the third mirror 405 are integrated by a support (not shown), and move in the same direction as the first mirror 403 at a speed that is half the moving speed of the first mirror 403 (not shown). (Shown).

Rod-shaped light source 402, first mirror 403, second mirror 404, third
Each of the mirrors 405 is located at a position (402 ', 40
3 ', 404', 405 '). At this time, the optical path length from the document table 401 to the lens 406 through the mirrors 403, 404, 405 is always maintained.

Therefore, if the signals from the light receiving elements of the image sensor 407 are read out in order during the sub-scanning, a sequential signal obtained by raster-scanning the document surface can be obtained.

FIG. 1 is a block diagram of an image processing circuit according to an embodiment of the present invention, and 1 is an image sensor 407 such as a CCD line sensor.
Memory for storing the image data and the shading correction data from the camera, 2 and 3 are tri-state buffers,
4 is an arithmetic processing section for performing various image processing, 5 to 13 are D flip-flops, 14 and 15 are AND gates, 16 is an OR gate, 17 is a shading correction processing section for correcting shading distortion, and 18 is a memory. Address signal E, write signal F, latch signal D flip-flop b, c
A timing clock generator for generating a switching signal for switching the shading correction data, 19
Is an analog-to-digital converter that converts an analog image signal from the image sensor 407 into a digital image signal.

An address signal E and a write signal are applied to the memory 1 from the timing clock generator 18, and the write signal is applied to the memory 1.
At the time of the Low level, data is written to the address position of the address signal E applied at that time, and
When the write signal is at the high level, data is read from the address position of the address signal E applied at that time.

A write signal applied to the memory 1 is similarly applied to the tristate buffers 2 and 3, and the write signal is applied to the tristate buffers 2 and 3.
When low level, input data is supplied to the memory 1.

Therefore, when the write signal is high, the data is read in accordance with the address signal E. Thereafter, if the write signal is set to low before the update of the address signal, the tristate buffer is moved to the address position where the data was read immediately before. 2
And 3 are written.

The memory 1 is an IC memory RAM having a capacity capable of storing two lines of 8-bit data per pixel. In this embodiment, of the 8-bit D0 to D7, the D0 bit is used as the shading data. 7 bits D1 to D7 are used for storing data representing the density of each pixel. Therefore, if a certain address is given to the memory 1 when the write signal is at the low level, the shading data and the image data stored at that address are read simultaneously.

Next, in the above configuration, the operation of storing the shading correction data will be described first. Usually, storage of the shading correction data is performed prior to reading of the original by the image sensor 407, and the white reference surface 408 by the image sensor is stored.
The shading correction data is obtained based on the output at the time of reading, and is stored in the memory 1. Then, when the original is read by the image sensor, the stored correction data is read, and shading correction is performed on the original read data.

FIG. 3 is a diagram showing the configuration of the shading correction processing section 17 shown in FIG. An analog image signal from the image sensor 407 is input to the shading correction processing unit 17, and an A / D conversion reference signal Y of the A / D converter 19 is output. In the present embodiment, the shading distortion included in the read data of the original image is removed by changing the reference signal Y of the A / D converter 19 based on the shading correction data obtained by reading the white reference surface 408. is there.

 The operation of FIG. 3 will be described.

As shown in FIG. 3, after the output of the image sensor 407 is amplified by an amplifier (not shown), a peak hold circuit 323 is provided.
And one input terminal of the comparator 341. The output signal line 323a of the peak hold circuit 323 is connected to one of the contacts of the analog switch 335. The other contact of the analog switch 335 is grounded, and a charge / discharge circuit including a resistor 337 and a capacitor 339 is connected to the common contact. The output of this charge / discharge circuit is connected to the + input terminal of
The voltage is divided by 3,345 and used as a reference signal for the A / D converter 19. That is, the voltage corresponding to the charged pressure of the capacitor 339 is A
It is supplied to the / D converter 19.

On the other hand, the output signal line 341a of the comparator 341 is connected to the AND gates 15, 14 and the OR gate 16 shown in FIG.
Are connected to the gate circuit. That is, the output of the comparator 341 is connected to one input terminal of the AND gate 15, and the output data of the memory 9 is input to one input terminal of the AND gate 15. The AND gates 15, 14 are gated by a switching signal from the timing clock generator 18. At this time, AN
Since the gate input of D gate 14 is inverted, one of AND gates 15, 14 is closed when one is open. The outputs of the AND gates 15 and 14 are input to the OR gate 16, and the logical sum thereof is used as the data input of the D flip-flop 13.

Therefore, when the switching signal is at the high level, the output 341a of the comparator 341 is selected and output from the OR gate 16, and conversely, when the switching signal is at the low level, the output of the memory 1 is selected and the OR gate 16 outputs Is output. Note that the timing clock generation unit 18 reads the white reference surface 408,
That is, the switching signal is output when measuring the shading distortion data.
Set to High level and set to Low level when reading the original.

The D flip-flop 13 is latched by a latch signal さ れ る output in synchronism with every one bit read of the image sensor 407. The output of the D flip-flop 13 is input to the memory 1 via the tri-state buffer 3, and is output as an analog switch 33 as a switch signal.
5 is connected to the control terminal. Here, it is assumed that the analog switch 35 is connected to the upper signal line 323a when the signal is low. The read / write timing of the memory 1 is controlled by the write signal as described above.
The address control of reading / writing of the memory 1 is performed by an address signal E.

That is, when the image sensor 407 reads the reference member 408, the output of the D flip-flop 13 is stored in the memory 1 according to the address value of the address signal E. On the other hand, when reading a document, the stored shading distortion data is read from the memory 1 in synchronization with the reading operation of the image sensor 407 according to the address value of the address signal. Thus, the shading distortion data stored in the memory 1 is a binary signal output from the D flip-flop 13.

When reading the shading distortion data, the comparator 341 compares the voltage charged in the capacitor 339 via the peak hold circuit 323, that is, the voltage of the connection point 341b, with the output power of the image sensor 407.

Accordingly, the comparator 341 can detect a change in the output of the image sensor 407 with respect to the charging voltage of the capacitor 339. Since the charging voltage of the capacitor 339 changes following the output of the image sensor 407 as described later, the comparison operation of the comparator 341 causes the current output of the image sensor 407 to change to the output corresponding to the immediately preceding pixel. In contrast, it can be determined whether it has fluctuated or is distorted. This makes it possible to detect nonuniformity of the output of the image sensor 407 due to shading distortion.

The waveform of the output signal line 341a of the comparator 341 becomes high when the output of the image sensor 407 is lower.

At this time, that is, at the time of measuring the shading distortion data, the switching signal is at the high level, and the signal line 34
The data 1a is latched on the D flip-flop 13 in synchronization with the latch signal #.

When the voltage of the image sensor 407 is higher than the connection point 341b, the output of the D flip-flop 13 goes low in synchronization with the latch signal ヲ.
35 is connected to the signal line 323a. Therefore, the capacitor 339 is charged via the resistor 337 by the peak value held by the peak hold circuit 323, and as a result, the connection point 34
The voltage of 1b rises.

On the other hand, when the voltage of the image sensor 407 is lower than the connection point 341b, the analog switch 33
5 is switched to the ground side, so the capacitor 339
It is discharged via 337, and the voltage at the node 341b is lowered.

Thus, by increasing or decreasing the charging voltage of the capacitor 339 according to the output of the comparator 341,
The charge voltage of the capacitor 339 can follow the output of the image sensor 407.

By the operation described above, a waveform corresponding to the output of the image sensor 407 appears at the connection point 341b. In the above operation, the output data of the D flip-flop 13 is stored in the memory 1 for one line for each pixel by the address control of the address signal E.

In this way, the output of the D flip-flop 13 for one line is stored in the memory 1 as data indicating a change point for approximately representing a change in the output obtained by reading the white reference plane 408 by the image sensor 407. Is done.

As described above, when storing the shading correction data, the switching signal is set to the low level as shown in FIG. 4, and the correction data output from the shading correction processing unit 17 is ANDed.
D flip-flop 13 through gate 15 and OR gate 16
And the data is latched by the latch signal ヲ. The Q output of the D flip-flop 13 is written to the memory 1 via the tri-state buffer 3 by a write signal. At this time, the address E of the memory 1 is "2" like k + 1, k + 3, k + 5, etc. for 1 bit of the shading correction data.
It is incremented by one. Therefore, the correction data is sequentially written to the odd addresses of the memory 1.

When data for one main scan is written in this way, during the next one main scan, the address E of the memory 1 is output with the even numbers and the odd numbers reversed (that is, φ, 1,2,3, 4) are replaced by 1, φ, 3,2,5,4, ...) and the signal of
By setting the level to the h level, the correction data read out and output from the odd address of the memory 1 is input to the D flip-flop 13 via the AND gate 14 and the OR gate 16, and the data is latched by the clock of 、. Similarly, data is written to the memory 1 in accordance with the addresses of k + 2, k + 4, k + 6,. With the above operation, the same correction data is written to both the even and odd addresses of the memory 1, and the shading correction data storage operation is completed.

On the other hand, in the shading distortion correction processing for the image signal obtained by reading the original image, the switching signal line is set to the low level so that the output signal of the memory 1 is input to the D flip-flop 13. Then, a read address is given corresponding to the read position of the image sensor 407. As a result, the analog switch 335 is switched in accordance with the data read from the memory 4 in the same pattern as when reading the shading distortion data, and the capacitor 339 is charged and discharged. At this time, the peak hold circuit 32
Since the output (323a) of 3 changes according to the density of the white (background or background) portion of the original, the connection point
The voltage of 341b changes almost in the same manner as when scanning the white reference surface 408. That is, a voltage waveform substantially similar to the read output of the white reference surface 408 is reproduced at the connection point 341b.

Therefore, a voltage change at the connection point 341b according to the shading distortion data is given to the A / D converter 19 via the voltage dividing resistors 43 and 45, and the A / D conversion reference is changed.

As a result, the A / D conversion reference value used for A / D-converting the read output of the original image by the image sensor 407 becomes a value corresponding to the shading distortion, and therefore, image data correction according to the shading distortion is performed. A / D
From the converter 19, a digital image signal from which shading distortion has been removed can be obtained.

Next, the operation at the time of reading a document will be described with reference to an example in which image processing is performed by a matrix operation shown in FIG.

That is, the previously input image data for the two lines (the (n, n + 1) th line) is stored in the memory 1, and the n + 2
N, n + 1 from memory 1 when inputting the image data of the line
The image data of the line is read out, and the arithmetic processing unit 4 executes a matrix operation. As this matrix operation, processes such as edge enhancement, smoothing, and image discrimination are executed.

The timing clock generator 18 outputs two addresses corresponding to one pixel of the input image data, and outputs k, k + 1, k
+2..., And addresses in which even and odd addresses are replaced by k, k−1, k + 2, k + 1...

As shown in FIG. 5, in accordance with the input of the image data of the n-th line, an address e which is sequentially increased by two addresses for one pixel is applied to the memory 1. That is, the timing clock generator 18 outputs addresses k + 1 and k + 2 corresponding to the image data of the m-th pixel, and outputs addresses k + 3 and k + 4 corresponding to the image data of the m + 1-th pixel.
Address k + 5, corresponding to the image data of the second pixel
Outputs k + 6. Further, the timing clock generator 18 sends the write signal to the address e at k + 2, k + 4, k + 6.
In the case of ..., it is set to Low level. As a result, the n-th line
The m, m + 1, m + 2nd image data is the address k of the memory 1.
+2, k + 4, and k + 6, respectively.

In addition, when the image data of the (n + 1) th line is input, the data obtained by exchanging the even number and the odd number is applied to the memory 1 as the address E. That is, the timing clock generator 18 generates addresses k + 2 and k + 1 corresponding to the image data of the m-th pixel.
Are output at addresses k + 4, k + 3 corresponding to the image data of the (m + 1) th pixel, and at addresses k + 6, k + 5 corresponding to the image data of the (m + 2) th pixel. Further, the timing clock generator 18 sets the write signal to the low level when the address E is k + 1, k + 3, k + 5,. As a result, the m, m + 1, m + 2nd image data of the (n + 1) th line is stored at addresses k + 1, k + 3, k + 5 of the memory 1, respectively.

Therefore, the image of the n-th line is stored at addresses k, k + 2, k + 4, k + 6,... Of the memory 1, and the addresses k + 1, k + 3, k +
The image data of the (n + 1) th line is stored in 5, k + 7.

When inputting the image data of the (n + 2) th line, the same address as in the case of the (n + 1) th line is applied to the memory 1 as an address e.

It is assumed that the line where the pixels C and D are present is at the (n + 2) th line. On the (n + 2) th line, the address E is as follows:... K, k + 1, k + 2,.
It is incremented by one. The image data currently input as C and D data is converted to D according to the pixel clock.
The data sampled by the flip-flops 5 and 7 is input to the arithmetic processing unit 4. Here, the pixel positions of C and D in the main scanning direction are set to m and m + 2. The image data of the (n + 2) th line is stored in the memory 1 in accordance with the addresses of... K, k + 2, k + 4, k + 6. Address… k, k + 2, k
The image data of the n-th line is stored at +4, k + 6,... As described above. However, as shown in FIG.
After latching the data of the n-th line read from the address to the D flip-flop 10 with the latch signal B, the write signal is changed to the low level without updating the address, and n + 2
Since the data of the line is stored at the same address,
After reliably extracting previously stored data, new data is stored at the same address.

Attention is paid to the data of X when the data corresponding to the pixels C and D is latched to the D flip-flops 5 and 7. This is data read from the memory 1 at the memory address k + 3 and latched to the D flip-flop 9 by the pixel clock. As described above, this data is stored in m + 1 on the (n + 1) th line.
The (+1) th pixel data is stored at address k + 3 of the memory 1 by a write clock. In addition, n +
In the first line, the address E is given to the memory 1 as an even number and an odd number inverted,..., K, k−1, k + 2, k + 1, k + 4.

Next, paying attention to the data of A and B, these are read out from the memory 1 at the memory addresses k + 2 and k + 6, respectively, and the D flip-flops 10 and 1 are read by the pixel clock.
This is the data latched to 2. As described above, the m, m + 2nd pixel data is written in the n-th line as described above, and the data is written to the memory 1 at the memory address k + 2, k of the memory 1.
+6. In the n-th line, the address E is sequentially incremented similarly to the (n + 2) -th line. By the above operation, the address e corresponding to the input image data of the (n + 2) th line is given to the memory 1, whereby the already stored image data of the (n, n + 1) th line is read out and the (n + 2) th line is read out. Image data is stored.

Then, each image data of the matrix shown in FIG. 7 is supplied to the arithmetic processing unit 4, and the data f (A, B, C, D, X) processed by the arithmetic processing unit 4 is output to the unit. By repeatedly performing the above operations, arithmetic processing is performed on all images.

When attention is paid to the shading correction data, data from even and odd addresses are alternately read and output line by line. As described above, the same data is stored in both the even and odd addresses when storing the shading correction data. Since the data read at the even (odd) address is written again to the odd (even) address, the same correction data for each line is output to the image data at the same pixel position. .

In this embodiment, as shown in FIG. 3, the memory addresses of the n-th line are | k + 1, k + 2, | k + 3, k + 4 |, and the n + 1-th line is | k + 2, k + 1, | k + 4, k + 3 | .., And the even addresses and the odd addresses are exchanged for each line and accessed alternately. However, the present invention is not limited to an even number and an odd number, and is similarly realized by accessing an integer number of memory addresses in one pixel. That is, in the embodiment, the access of the even number and the odd number alternately indicates that the access was performed by inverting the lowest address of the memory address line to one pixel, and the second address line was replaced by one pixel. When inverted, the n-th line is | 2 (j), 2 (j + 1), | 2
(J) +1,2 (j + 1) +1, | 2 (j + 2), 2 (j + 3)
And the (n + 1) th line is | 2 (j + 1), 2
(J), | 2 (j + 1) +1,2 (j) +1, | 2 (j + 3), 2
Although the address changes as (j + 2) |, the operation of accessing the same address every two lines is the same.

In this embodiment, the address in one pixel is switched between even and odd for each line and accessed for every two lines. However, in another embodiment, the address is changed as shown in FIG. The same line address is accessed, and the read / write timing of data to / from the memory 1 by the write clock is changed for each line.
The same effect can be obtained by switching and accessing an odd number.

The memory capacity of the memory 1 is set to be equal to or more than three lines, the number of addresses corresponding to one pixel of the image data is increased, and the number of flip-flops is changed. Needless to say, this is possible.

Further, in this embodiment, during the shading waveform storage operation, the correction data stored in the odd address in the first main scan is read out from the odd address in the second main scan, and the same data is written in the even address in the second main scan. Although it was stored at an odd address, the switching signal is set to the low level also in the second main scanning, so that the correction data from the image sensor 407 is also subjected to the shading correction processing unit in the second main scanning similarly to the first main scanning. The same effect can be obtained by writing the correction data to an even address.

Further, when the same address is accessed for each line, the read / write timing of data is changed for each line, the access is switched between even and odd, and the correction data is always accessed from the same address. May be stored in even addresses for one main scan.

Further, even when the image data to be stored for the arithmetic processing is, for example, one line, it can be easily realized by selecting the memory capacity in accordance with it.

As described above, according to the configuration of the present embodiment, the cost can be reduced by using the memory IC efficiently, the size can be reduced by a simple circuit configuration, the cost can be reduced, and the number of pins can be reduced when considering an LSI. -It is possible to reduce the number of line memories by performing writing.

That is, conventionally, to perform 2500-bit image processing with a resolution of 8 bits, three 8 × 8 kbit memory ICs were required.
According to the configuration of the present embodiment, it can be realized with one 8 × 8 kbit memory IC.

In addition, by storing correction data to be stored prior to reading a document at a plurality of addresses in the same pixel,
The correction data and the image data at the time of reading the original can be stored in the same memory, which has the effect of reducing the number of memories and reducing the cost and the size of the apparatus.

Also, the image data and the data for the shading correction process are stored in the same memory by once reading out the data for the shading correction process previously stored in the memory so as to store the correction data in a plurality of addresses of the memory and storing the data again. This has the effect of reducing costs and reducing the size of the device by reducing the number of memory ICs.

〔The invention's effect〕

According to claim 1 of the present invention, processing means for performing a matrix operation using image data read from an image memory;
While outputting the address in the memory, the pixel data already stored at the address is read out, and then, before the address is updated, the subsequent pixel data at the same pixel position as the read pixel data is read out. Control means for writing pixel data of a predetermined unit to be performed, and the pixel data of the subsequent line directly input without passing through the memory,
And holding means for holding a plurality of lines of pixel data necessary for the matrix operation, including the pixel data read from the memory, wherein the processing means comprises a plurality of lines of pixel data held by the holding means. Since pixel data is subjected to a matrix operation, in a buffer control for performing a matrix operation on line-by-line image data continuously input from the line sensor, every time one address is updated, pixel data of a line already stored is stored. And the pixel data of the succeeding line is replaced, and the memory capacity of the memory can be saved as compared with the conventional apparatus in which reading is performed from another line memory while writing is performed on one line memory.

In addition, since both reading and writing of pixel data are performed each time one address is updated, compared to a conventional device that performs only one of reading and writing of pixel data each time one address is updated. In addition, the number of times of address switching can be reduced. As a result, in consideration of the case where the address switching speed is the same, the input / output of image data is performed with respect to a conventional apparatus which performs only one of reading and writing of pixel data every time one address is updated. Speed can be doubled.

According to the second aspect of the present invention, in an image signal processing apparatus for performing image processing of a pixel at a certain pixel position and a pixel located around the pixel position, the image signal processing device When assigning an address group having N consecutive addresses and writing input image data to the memory, the address group is changed every time the pixel position changes for one predetermined unit, and the next Each time the unit becomes a predetermined unit, the address in the address group is changed cyclically and the address is output.
When image data is read from the memory, all addresses of one group are continuously output, and then all addresses of the next group are output. A certain number of N pixels can be continuously read from the memory, and a certain pixel and its peripheral pixels can be continuously output. As a result, in the present invention, the address update is controlled by controlling the address update, as compared with a conventional device having a plurality of memories and writing image data at different lines and at the same pixel position to the same address of each memory. As a result, the number of memories can be reduced, and accordingly, the number of data buses can be reduced and the device can be downsized. For example, the size of an element can be reduced when implementing an LSI.

[Brief description of the drawings]

FIG. 1 is a block diagram of an image processing circuit to which the present invention is applied.
FIG. 2 is a schematic diagram of a document reading apparatus, FIG. 3 is a block diagram of a shading correction processing section, FIG. 4 is a timing chart of a storing operation of shading correction data, FIG. 5 is a timing chart of an image processing operation, 6 is another timing chart of the image processing operation, FIG. 7 is a diagram showing a matrix of the image processing, FIG. 8 is a block diagram of a conventional image processing circuit, and FIG. 9 is a conventional image processing operation. Numeral 1 is a memory, numeral 2 and 3 are tri-state buffers, numeral 4 is an arithmetic processing unit, numerals 5 to 13 are D flip-flops, and numeral 17 is a shading correction processing unit.

Continuation of front page (56) References JP-A-60-196855 (JP, A) JP-A-61-153784 (JP, A) JP-A-62-145444 (JP, A) JP-A-62-146064 (JP) , A) JP-A-63-46581 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06T 1/00-1/60 G06F 12/00-12/06

Claims (2)

(57) [Claims] 1. An image memory for writing and reading image data continuously input in units of lines in accordance with an address signal, and processing means for performing a matrix operation using the image data read from the image memory. Address output means for outputting the address signal to the memory; and while the address output means is outputting a certain address, reads out pixel data already stored at that address, A control unit that writes pixel data of a subsequent line at the same pixel position as the read pixel data before the output unit updates the address; and the subsequent line that is directly input without passing through the memory. Pixel data read from the memory and pixel data read from the memory, And a holding means for holding a minute pixel data, the processing means, the image signal processing apparatus characterized by the pixel data for a plurality of lines held in said holding means for matrix operation. 2. A processing means for performing image processing of a pixel at a certain pixel position and a pixel located at a periphery of the pixel position, and a unit of image data comprising a plurality of pixels for use in the image processing. A required number N, a memory for storing, and address output means for outputting an address to the memory, wherein the address output means is configured to output N consecutive N pixels for each pixel position of the predetermined unit image data. When an address group having an address is assigned and input image data is written to the memory, the address group is changed every time the pixel position changes for one predetermined unit,
In addition, every time the next predetermined unit is reached, the address in the address group is cyclically changed and the address is output. On the other hand, when the image data is read from the memory, all the addresses of one group are continuously output. And then outputting all the addresses of the next group.