JPS58116860A - Longitudinal and lateral converting circuit for image array of image memory system - Google Patents

Abstract

PURPOSE:To convert an image array with a simple circuit constitution and to set the area of a character generator and a work area at the same time, by processing row addresses and/or inversion addresses successively without altering on address arithmetic system and the access system of an image memory. CONSTITUTION:The image memory 1 consists of a real memory 2 and an address arithmetic circuit 3 which calcultes the number M and storage location A of the memory 2 from a row address (i) and a column address (j). Further, a longitudinal and lateral converting circuit 4 is provided with a data selector 8 which selects a signal A for indicating row and column mutual conversion and a signal (t) for indicating modification of format by a memory mode signal MM and a rotation mode signal MM. By the output of the selector 8, the indication of longitudinal and lateral conversion is supplied to row and column data selectors 5 and 6 to apply a row address i'11-0 and a column address j'11-0, and also to apply a signal A and/or -A to the circuit 3, converting an image array through the simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to image processing equipment such as printers and facsimile machines. An image memory system for the storage of image information, and in particular an image array that allows image information in portrait and landscape formats to be arbitrarily exchanged and stored from one format to another. Related to vertical/horizontal conversion circuits.

(2) Technical background Recent printers are A4. There are many systems that allow printing in any format, such as 9 characters vertically or horizontally, on paper of a specified size such as B5. In printers of this type, there are cases where it is desired to output an image in a portrait format onto a landscape paper, or vice versa. The image buffer in the printer is usually used as the image buffer in the printer.
As shown in b), the format B4, which has the maximum size both vertically and horizontally, can be accepted to meet output requests in any format. For example, a memory with a rectangular address space of 4095×4095 is prepared.

However, such a memory with a rectangular address space has a lot of wasted area, as shown by the it line in FIG. 1, and the efficiency of memory element utilization is also poor. especially.

The image buffer is typically 2x to speed up processing.
This is even more so since they are provided on both sides and are used by switching between them.

Therefore, as an improvement measure, as shown in Figure 2.

Fix the image storage area in the image memory to the image array position of the maximum vertical size on the left.

The remaining right side area is used for a 9-character generator (C, G), an area for storing control instructions, a work area, etc.

A method has been proposed in which the lower part is left unused and no memory element is mounted thereon.

In this case, depending on the format size.

It becomes necessary to convert a horizontally long or vertically long format into a vertically long or horizontally long format, respectively. This conversion is a 90-degree rotation of the coordinate axes, and simply exchanging the row address and column address will cause the image to be inverted and 90-degree rotation cannot be achieved. It is sufficient to have an address calculation system and an access system that rotate the coordinate axes of the entire memory by 90 degrees, but for this purpose, it is necessary to prepare two sets of address calculation systems and access bases for normal access processing. , the burden on the hardware increases.

On the other hand, image memory systems of the type disclosed in 9% Publication No. 54-39098 (Memory System for Image Processing - Chimney IBM) and Japanese Patent Application No. 56-101498 filed by the same applicant, In order to speed up the process, a plurality of image points called an image array are distributed to the same number of storage modules, and successive output/writing is executed simultaneously. Third
The figure shows an example of such an image subarray. Using image point 1 (i, j) at the top position as a base point, an image sub-array of either P pit, pxit or IXP, is selected. In this case, it is necessary to switch the designation of the image sub-array at the same time as the image array is rotated.

(3) Object of the Invention It is an object of the present invention to provide an image memory system using the image sub-array processing format described above, in which a single character generator area and a It is an object of the present invention to provide an image array vertical/horizontal conversion circuit having a simple configuration and capable of setting four areas at the same time.

(4) Structure of the Invention As shown in FIG. 4, when the row address i and column address j of the image R in <a) of the same figure are simply exchanged, The image R is reversed as shown,
At this time, if the value obtained by subtracting the first column address j from the maximum column address jmaz is the new row address i', then the same figure (C
), it is possible to realize a simple vertical/horizontal conversion circuit by focusing on the fact that the image R is flipped over and the correct vertical/horizontal conversion is performed. Thereby, the present invention comprises a row address i and a column address j for selecting an image point in an image array, and P images that can be sequentially read or written simultaneously in a single memory cycle. In an image memory system whose access is controlled by signal means t specifying points with either a subarray of lxP or Pxl.

A signal means RM that specifies either the vertical or horizontal format of the image array, a signal means A that instructs mutual conversion between the 9th row address i and the column address j, and the signal means RM changes the format specification. Then, the signal means t is inverted to I, and the signal means A is inverted to make the 1st row address i a new column address j', and the 9th column address j is the maximum column address value j of the image array.
A value obtained by subtracting column address j from mat is set as a new row address i', and the apparatus further comprises means for supplying the inverted optical signal means T and the new row address j' and column address j' to the image memory. It is characterized by the fact that

(5) Examples of the invention The present invention will be explained below based on two examples.

FIG. 5 is an explanatory diagram of the structure of the image memory used in the two embodiments, and FIG. 6 is an explanatory diagram of signals of an external register that controls the vertical/horizontal conversion circuit of the embodiment.

FIG. 7 is a configuration diagram of this embodiment.

In FIG. 5, <a> shows the image array before vertical/horizontal conversion, and ψ) in the same figure shows the image array after conversion. row 9
Each column has 4095 address locations.

Row address 111-0 and column address jn for each 12 pits
−.

Toyo) Select image point 1 (i, j). The image sub-array has a 16-bit configuration, and using the sub-array type designation signal t, the Px1 type shown in FIG. 3 is set to l=l, I
The XP type is represented by t=Q.

In Figure 6, (σ) is for each format) B4/
A4. For BS/A5, 9-rotation mode signal R that instructs whether to use vertical or horizontal image arrangement.
Indicates M. For example, as shown in FIG. 5(a), A4
If you want to use the /B4 format in landscape orientation, the image must be rotated and stored in portrait orientation in the image memory, as shown in FIG. RM=“
1". Also, when A4/B4 is used in portrait orientation, there is no need for rotational conversion, so RM="θ".

In the case of A5/B5 format, a relationship opposite to A4/B4 holds true. In this way, when RM="1", the vertical/horizontal conversion process must be activated.

In FIG. 6 φ), the memory mode signal MM is.

Indicates whether the image memory access request is for a single character generator or work area (-"0") or for an image buffer area (="1"). Further, the access mode signal t sets the access type 1xP of the image sub-array to horizontal mode (="0"), PXl
is specified as vertical mode (="1"). And address inversion mode signal person.

Indicates whether or not to replace the ninth row address 1u-o and column address ju-o in image array rotation conversion.

Next, the embodiment circuit shown in FIG. 7 will be explained.

In the figure, 1 is an image memory, 2 is a real memory with a module configuration, and 3 is a storage module number M, such as row address i and column address j in the image memory space.
This is an address calculation circuit that calculates (j, j) and its storage location A(i, j).

4 is a vertical/horizontal conversion circuit; 5.6 is a data selector that exchanges addresses between rows and 1 column; 7 is a subtraction circuit that subtracts jn-o from the maximum column address value jrnax; 8 is a data selector; 9 is a NAND gate,
10 to 12 are inverters for generating inverted signals.

In operation, the memory mode signal MM
Takes a value of '1' indicating buffer processing operation.

When the rotation mode signal RM takes a value of 1'' indicating that format rotation storage is required, the output of the NAND gate 9 becomes 10''.

The data selector 8 selects and outputs,λ,1,among the human inputs,A,λ,t,7,.

The signal λ instructs the data selectors 5 and 6 to transpose the addresses of rows and columns in vertical and horizontal conversion.

As a result, the data selector 6 outputs the 1st row address isH to the column address j (u-o,
is outputs j max -jll-6 from the subtraction circuit 7 to the row address 1111.

On the other hand, Kaguto = 10” which is not image buffer processing
), or when image buffer processing does not require vertical/horizontal conversion processing (aM="0").

The output of the NAND gate 9 becomes "1", and the data selector 8 selects and outputs inputs A and t. In this case, p'llo is i in data selector 5.6.
'u-oK* So, ju-o- is output as is to A-o. These signals are respectively supplied to the address calculation circuit 3.

(6) Effects of the Invention As described above, the image memory 1 has a conventional configuration 11 and receives an input signal 1/1- of the same form as the conventional one.

It is only necessary to process jsl-o, and it becomes possible to use the memory efficiently with a simple circuit.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the conventional image memory usage state, FIG. 2 is an explanatory diagram of the improved image memory usage state,
FIG. 3 is an explanatory diagram of an image subarray. FIG. 4 is an explanatory diagram of the vertical/horizontal conversion process in the present invention. FIG. 5 is a configuration diagram of the image memory of the embodiment, FIG. 6 is an explanatory diagram of signals for controlling the vertical/horizontal conversion operation of the embodiment, and FIG. 7 is a configuration diagram of the embodiment. In the figure, 1 is an image memory, 4 is an vertical/horizontal conversion circuit, 5, 6.8 are data selectors, 7 is a subtraction circuit, 9 is a NAND gate, and 10 to 12 inverters. Patent Applicant: Fujitsu Limited, Representative Patent Attorney, Necessity Statement: Hiroshi f'3ffi (a) (b)
((1) Ya now (＾) (Tonzai 6)

Claims (2)

[Claims] (1) Row address i and column address j for selecting an image point in the image array and a single memory
In an image memory system having an image memory whose access is controlled by signal means t specifying P image points which can be read or written simultaneously in a cycle in a sub-array of either IXP or PXl. A signal means RM that specifies either the vertical or horizontal format of the image array, a signal means RM that instructs mutual conversion between the 9th row address i and the column address j, and the signal means RM changes the format specification. Then, the signal means t is inverted to t, the signal means A is inverted, the first row address i becomes a new column address j', and the second column address j becomes the maximum column address value j of the image array.
A value obtained by subtracting column address j from max is set as a new row address i', and means for supplying the inverted signal means t and the new row address i' and column address j' to the image memory. An image array vertical/horizontal conversion circuit characterized by: (2) Row address i and column address j for selecting an image point in the image array and a single memory
An image memory having an image memory whose access is controlled by signal means t and K for specifying P image points which can be successively read or written simultaneously in a cycle by a sub-array of either IXP or pxt. In the system. A signal means RM for specifying the horizontal or vertical 7-original format of the image array, and a signal means MM for specifying whether the information to be accessed in the memory is an image sub-array or other information.
Signal means A for instructing mutual conversion between row address i and column address j, and when said signal means RM changes the format designation and when said signal means MM performs image sub-array, said signal means t. is inverted and set to t, and the signal means A is inverted. The row address i becomes a new column address j', and for the second column address j, the maximum column address value jw of the white line image array
The value obtained by subtracting the column address j from m is the new row address i
', and further comprising means for supplying said inverted signal means t and new row addresses i' and column addresses j' to said image memory.