JPH061449B2 - Image memory for image editing - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION INDUSTRIAL FIELD OF APPLICATION The present invention relates to any sub-array of images (1 × p ² or px).
p, where p is the number of bits), relates to an image memory for image editing in which access from a random access memory of word organization can be performed with a simple structure.

[Conventional technology]

As a conventional image memory for image editing, for example, there is a word organization image memory used for processing a digital image using binary values of 0 and 1, but at the time of access, it is the same as the memory of a normal microcomputer system. And the access method are adopted. That is, w
In the case of word organization of bits, the image data is r × ws
It becomes a two-dimensional arrangement. Since the access in this case is 1 × w unit, it is possible to specify every row in the row direction, but there is an inconvenience that it can be performed only every w bits in the column direction. .

As a solution to this problem, Japanese Patent Publication No. 54-39098 "Memory System for Image Processing" has been proposed.

In such a system, there are pq recording modules, each numbered 0, 1, ... Pq−1, these modules being rp × sq consisting of a plurality of image points I (i, j). Image array is stored (where i is 0 ≦ i <
rp and j is in the range 0 ≦ j <sq) and the image point I (i, j)
To a storage module M (i, j) = (iq + j) // pq and further from there to another (where (iq + j) // pq is (iq + j)
Is the remainder integer when p is divided by pq). In addition, p,
q, r, and s are design parameters and take arbitrary integer values within a reasonable range. Further, in cooperation with the transfer means, the image point I (i, j) is stored in or read out from the storage device A (i, j) = i / p × s + j / q of the storage module M (i, j). It comprises address calculation means and control means for simultaneously storing or reading out pq image points in any 1 × pq or p × q sub-array of the image array.

According to the above configuration, a pq-bit word organization can be obtained, and access can be performed in units of 1 × pq or p × q, and the starting point of access is designated for each bit in both the row and column directions. It becomes possible.

[Problems to be solved by the invention]

However, in Japanese Patent Publication No. 54-39098, since it is necessary to control the address for each memory module, there is the inconvenience that the amount of hardware becomes large and the address control becomes very complicated. Further, in image editing processing such as image cutout, movement, rotation, composition, enlargement, reduction, etc., it is not always necessary to specify the starting point of access in 1-bit units in both the row direction and the column direction. Memory is desired.

[Means and Actions for Solving Problems]

The present invention has been made in view of the above, and in order to enable memory access by 1 × p ² or p × p with a simple configuration, p memory modules capable of reading and writing p bits are the same. It provides an image memory for image editing which is accessed by an address value.

〔Example〕

Hereinafter, the image memory for image editing according to the present invention will be described in detail.

FIG. 2 shows an embodiment of an image editing apparatus constructed by using the image memory of the present invention, in which an image of an original is read using a CCD or the like and a pseudo halftone obtained by using a binary image or a dither method or the like. An image input device 1 for inputting an image, a ROM 2 storing a program for causing the CPU 3 to perform image processing and data transfer control, a CPU 3 for executing image processing control and the like according to the program of the ROM 2, and an image input device The image memory 4 for storing the pseudo halftone image input by 1 and the data after the image processing, the image output device 5 for making a hard copy of the edited contents and the like, and the contents during the editing process are monitored. A CRT display 6, an input device 7 such as a keyboard for inputting various commands for processing, and the above-mentioned members are mutually connected to exchange data. Composed of a bus are placed 8.

In the above configuration, the image data from the image input device 1 is stored in the image memory 4, and the CPU 3 accesses the image memory 4 according to the present invention in accordance with the processing content command given by the input device 7 to execute the processing. .
The processing results are sequentially displayed on the CRT display 6 and hard-copied if necessary.

FIG. 1 shows an embodiment of the present invention, which is a one-dimensional mode and a two-dimensional mode.
Multiple memory selectors for access 13 according to the dimension mode
_The address decoder 11 for selecting one of _{-0 to} 13 _-3 and 14 _{-0 to} 14 _-3 and the 1 × p ² mode (one-dimensional mode) or p ² mode (two-dimensional mode) for the address decoder 11. When the combination of the designated flip-flop 12 and the 2p type selected by the address decoder 11 is the p type of the one-dimensional mode, one of them is selected and p memory modules (16
_{-00 to} 16 _-33 ), and one-dimensional access memory selectors 13 _{-0 to} 13 _-3 that generate chip select signals for
A two-dimensional access memory selector 14 _-0 which, when the combination of 2p types selected by the address decoder 11 is the p type in the two-dimensional mode, selects one of them to generate a chip select signal for p memory modules. ~ 14 _-3 ,
C × p so that data from the data bus can be input to the memory module corresponding to the image array as shown in FIG.
P ² for shifting bits (where 0 ≦ C <P <−1)
Circular shift circuit 15 for bits, memory modules 16 _{-00 to} 16 _-33 each of which has a structure of p bits x rs words, and p x p of the same, and shifted memory modules 16 _-00 to _16-33 cyclic shift circuit 17 of ² bits which shifts the data stored in the reverse direction to the original state and outputs it, and the output data of the cyclic shift circuit 17 is inputted as a signal. It is composed of a bus driver 18 which sometimes outputs to the data bus 8.
Memory module 16 _-00 to 16 _-33 may also be configured using an element of p bits × rs word structure, 1-bit × rs
It is also possible to configure p word-wise elements in parallel. Either static RAM or dynamic RAM can be used for each element.

FIG. 3 shows the details of the cyclic shift circuits 15 and 17, and the CPU
The buffer gate 21 that opens the gate when the address A ₀ given by 3 is at the “L” level and the buffer gate 22 that opens the gate when the address A ₁ is at the “L” level
And an inverter 23 that inverts and outputs the signal of address A ₀
And an inverter 24 that inverts and outputs the signal of address A _1.
And a 4-bit cyclic shift circuit 25 that shifts and outputs input data by 4 bits when a gate signal is given from the inverter 23, and shifts and outputs input data by 8 bits when a gate signal is given from the inverter 24. It is composed of an 8-bit cyclic shift circuit 26.

FIG. 4 shows the access processing according to the present invention with P = 4, r = 4.
This is an example in which design parameters of s = 2 are used, and a unit of 1 × p ² (1 × 16 in the example of the figure) as shown in the figure A or a unit of p × p (4 × 4 in the example of the figure) as shown in the figure B It is accessed by. FIG. 5 shows the positional correspondence between the two-dimensional image array as shown in FIG. 4 and the memory modules 16 _{-00 to} 16 _-33 . 00,01,02,03,10,11,12,13,20,21,2 in the figure
Each 2,23,30,31,32,33 is a memory module number corresponds to the lower case numbers of the memory module 16 _-00 to 16 _-33 indicated by Figure 1. As is apparent from the figure, each memory module stores 4 bits in the row direction, and the same address is supplied to one group of 00 to 33 (range of the frame in the figure). (In general, the memory module number ab is set to 0 ≦ a <p, 0 ≦ b <p.) The image memory 4 stores the image point I (i, j) (where 0
Rp × sp consisting of ≦ i <rp and 0 ≦ j <sp ² ).
² (16 × 32 in the example of FIG. 3) image array can be stored, and the above-mentioned p ² image points of 1 × p ² or p × p can be stored in a single memory cycle. It is a word organization type random access memory that is read or written, and comprises p ² memory modules (16
_-00 to 16 _-33) are each can be stored in different storage positions prs number of image points. Then, only p storage modules can be accessed by one access, and p bits can be read from one storage module.
Can write. When the configuration of image points accessed at one time is 1 × p ² , [I (k, lp ² ) I (k, lp ² +1) ... I (k, (l + 1) p ² -1)] can be read and written in units of p ² and the image point configuration is p × p, Can be performed in p ² units. (However, 0 ≦ k <
rp, 0 ≦ l <s, 0 ≦ m <r, and 0 ≦ n <p. )
In either case, the address values input to each memory module are all the same value.

In the configuration of FIG. 1, the size of the image to be edited is A
If the size is 4 (210 mm × 297 mm) and the image reading density is 16 dots / mm, the number of image points is about 16 × 10 ⁶ (accurately 15,966,720). In this case, r ≧ 1188 = 2 = 7 × 16 / P, S ≧ 210 = 21
0 × 16 / P ² P = 4 [or r ≧ 840 = 210 × 16 / P, S ≧ 279
= 297 × 16 / P ² ], and rs ≧ 249,480. Therefore, the capacity of the memory module is 4 × 256
You can use the one with kW (1 × 256kw for commercial products)
4 dynamic RAMs (DRAM) may be used.

When reading a document and printing it out, one-dimensional scanning is performed line by line. That is, as image points, data in which the column number is increased by 1 in the same row is required.
At this time, if the memory is set to the one-dimensional mode, one word may be transferred to the memory every time 16-dot scanning is input, or one word may be transferred from the memory every 16-dot scanning output. In order to operate in the one-dimensional mode, first, a flip-flop is used by an external circuit (not shown).
Input signal to 12 and output “L”
Keep level. This is a normal 1x from CPU3 etc.
exactly it looks similar to the memory system of word structure of p ^2. The address decoder 11 outputs Lφ in response to the 2 bits of the address and the output of the mode setting flip-flop 12.
Either S~L3S one of terminals of the one-dimensional access memory selector 13 _-0 to 13 _-3 enabled becomes "L" level. When the memory selector 13 _-0 to 13 _-3 which is configured by the three-state buffer G terminal becomes "L" level, the input data is output. In this case, input A
_{Since 0 to} A ₃ are grounded, the output also becomes L level and the corresponding memory modules (plurality of 16 _{-00 to} 16 _-33 ) are accessed. One-dimensional access memory selector 13 _-0 ~
The output of 13 _-3 is 13 _-0 φ of the memory module matrix
Lines correspond to 13 _-1 to 1 line, 13 _-2 to 2 lines and 13 _-3 to 3 lines. (Note that the read / write signal and the address signal defining the depth direction in the memory module are omitted in the figure.) The cyclic shift circuits 15 and 17 correctly output data on the data bus 8 in the two-dimensional access mode. It is provided so that it can be done. This shift circuit 15 and 17
The number of shift bits is 1 and the same address signal as that input to the address decoder circuit 11 is input.

The configuration of the cyclic shift circuits 15 and 17 is as shown in FIG. 2, but when the address A ₀ = “H” level and A ₁ = “L” level, the 4-bit cyclic shift circuit 25 and the buffer gate 22 are It becomes valid and the input is shifted by 4 bits and output to the memory module side. Similarly, 8 bits are shifted when A = L and B = H, and when A = H and B = H.
Bits are shifted. The input shift circuit and the output shift circuit may have opposite shift directions, but in the embodiment, the input shifts right and the output shifts left.

Therefore, when A and B = L, the data is not shifted at the time of writing and is written in the φ-th row of the memory module matrix consisting of 16 _{−00 to} 16 ₋₃₃ . Further, at the time of reading, data is also read from the φ-th row and is not shifted and is output to the data bus 8.

When A = H and B = L, the data is right-shifted by 4 bits and written in the first row at the time of writing. That 0 bit to 3-bit data memory module 16 _-11 words,
It is written in the 1st row and 1st column. Further, at the time of reading, the data in the first row is shifted left by 4 bits and output. Therefore, the data input to the image memory 4 is returned to the original bit position and output.

Next, the case of accessing in the two-dimensional mode during the image editing process will be described. In this case, first input the ▲ ▼ signal to the flip-flop 12 for mode setting,
Set the output to "H" level. As a result, the address decoder 11 outputs the outputs Sφs to S according to the addresses A ₀ and A ₁ .
Either 3s is valid, one of terminals of the two-dimensional access memory selector 14 _-0 to 14 _-3 becomes "L" level. The memory selectors 14 _{-0 to} 14 _-3 are composed of three-state buffers, and the output of the selected selector is "L".
A level is reached, and four memory modules are simultaneously accessed. That is, when the addresses A ₀ and A ₁ are both at the “L” level, the memory modules 16- _-00 , 16 _-11 , 16 _-22 , 16
_{If -33} is accessed, A ₀ is "L" level and A ₁ is "H" level, _16--01 , 16 _-12 , 16 _-23 , 16 _-30 are accessed and A ₀ is "H". If A ₁ is “L” level, _16--02 , 16 _-13 , 16 _-20 , 16 _-31 is accessed, and if both A ₀ and A ₁ are “H” level, 1
6 _-03, 16 _-10, 16 _-21, 16 _-32 is accessed. Since the operations of the cyclic shift circuits 15 and 17 are the same as those in the one-dimensional mode, description thereof will be omitted. As described above, the four memory modules that are simultaneously accessed at one time are not arranged on the same column but are arranged diagonally because each bit of the memory modules on the same column is connected by the same data line. This is so that it can be done.

Writing and reading in the two-dimensional mode are as follows.

When the address A ₀ = A ₁ = “L” level, the data is not shifted and the data is not shifted in the memory module 16 when writing.
_-00 DI _0-3 output from the cyclic shift circuit 15 is written to, likewise 16 _-11 DI _4-7, 16 _-22 to DI _8-11, each DI _12-15 16 _-33 Written. When reading, the same bit order is output. Next, A ₀ = “H” level, A
When writing with ₁ = "L" level, it is shifted to the right by 4 bits and goes to 16 _-01 to DI _0-3 , 16 _-12 to DI _4-7 , 16 _-23 to DI _8-11 , and 16 _-30 . DI _12-15 are written respectively. On the other hand, at the time of reading, the data read from the same memory module is shifted to the left by 4 bits and output.
This output data comes to the original bit position.

Next, a case will be described where the data written in the one-dimensional mode is read in the two-dimensional mode, or conversely, the data written in the two-dimensional mode is read in the one-dimensional mode.

The internal address supplied to each memory module is the address input to the memory modules other than the address decoder 11 among the addresses input to the image memory 4. When this address is the same for each memory module, each memory module corresponds to an image point as shown in FIG. The two-digit number in the frame represents the memory module number. First, 1
When four words are read in the two-dimensional mode after writing four words in the two-dimensional mode, the data is written as shown in Table 1.

On the other hand, upon reading, the data is read from each memory module as shown in Table 2. As is clear from Tables 1 and 2, the memory module configurations and bit order of the above-mentioned operation modes are the same.

When writing in two dimensions and reading in one dimension, it is sufficient to write as shown in Table 2 and read as shown in Table 1.

Here, if the correspondence between the image points and the memory module is shown by a formula, it is as follows. Replace the memory module with M (a,
b) (provided that 0 ≦ a, b <p), a = i // p b = (i // p + [(j // p ² ) / p]) // p []: Gauss symbol It is the largest integer that does not exceed the number in [].

(However, i // p is the remainder obtained by dividing i by p.).

In the above description, the memory access is 1 × p ² or p ×
Although the unit of p is used, the memory access unit is set to 1 × p or 1 × p or rs (word) instead of p (bit) × rs (word). It can be done with p × 1. This makes it possible to configure a parallel access memory.

Also, when accessing with 1 × p ² , conventionally, the row direction is 1
It was possible to specify for each bit, but in the column direction, access could be specified only in units of p ² bits. In other words, when clipping an image, the starting point of clipping can be specified only for each p ² . However, if the access unit is p × p as in the present invention, access can be specified in p-bit units in both the row direction and the column direction, and cutouts and the like can be specified with 1 / p of the conventional method, which improves editing accuracy. can do.

Further, in the case where the image to be stored and edited is a pseudo halftone image by the dither method or the like, the image quality is deteriorated unless the image is edited for each pixel of the dither method. However, by using the p × p access mode of the present invention, if the pixels of the dither are p × p, it is possible to process one pixel at a time, which makes editing very easy.

Further, regardless of whether the image is a binary image or a dither image, the image can be rotated by 90 ° easily because the access unit is p × p. That is, when the data read from the image memory 4 is output to the data bus 8, it can be realized only by changing the wiring of the data bus buffer so that the bit position should be output when 90 rotations are made.

〔The invention's effect〕

As described above, according to the pixel editing image memory of the present invention, the p ² bit of the 1 × p ² or p × p sub-array is accessed at one time, and the address for each memory module is the same. Such hardware enables high-speed access in 1 × p ² or p × p units.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of an image editing apparatus using an image memory according to the present invention, and FIG. 3 shows details of a cyclic shift circuit according to the present invention. FIG. 4 is a block diagram, FIG. 4 is an explanatory view of an access unit targeted by the present invention, FIG. 5 is an explanatory view showing correspondence between an image array and a memory module in the present invention, and FIG. 6 is an image designated by the same internal address. Explanatory drawing which shows the correspondence of a point and a memory module. Explanation of symbols 1 ... Image input device 3 ... CPU 4 ... Image memory 5 ... Image output device 11 ... Address decoder 12 ... Flip-flop 13 _{-0 to} 13 _-3 , 14 _{-0 to} 14 _-3 ... Access memory selector 15, 17 Circular shift circuit 16 _{-00 to} 16 _-33 Memory module 18 Bus driver 21, 22 Buffer gate 23, 24 Inverter 25 4 bit circular shift circuit 26 ... 8-bit circular shift circuit

Claims (1)

[Claims] 1. An image point I (i, j) having a Boolean value with p, r and s as design parameters (where 0 ≦ i <r
p, and an rp × sp ² image array consisting of 0 ≦ j <sp ² ) can be stored, and p ² image points in a 1 × p ² or p × p sub-array of said image array are single. In a word organized random access memory system that can be read or written in one memory cycle, each can store prs image points in different storage locations, each capable of writing and reading p bits. In the 1 × p ² array, the storage means is composed of p ² storage modules, and the p storage modules can be accessed. [I (k, lp ² ) I (k, lp ² +1) ... I (k, (l + 1) p ² -1)], and in the case of the p × p array, (However, 0 ≦ k <rp, 0 ≦ l <s, 0 ≦ m <r, 0 ≦ n <
p. The image memory for image editing is provided with an access means for accessing the configuration of the p ² image points indicated by) by giving the same address value to each of the storage modules.