JP2548286B2 - Image data processor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image data processing device for processing a two-dimensional image in bit units.

(Prior Art) Generally, in information processing devices, character data and numeric data are processed using so-called code data. on the other hand,
The two-dimensionally imaged data needs to be processed bit by bit on the memory.

FIG. 2 shows a block diagram of a conventional image data processing device.

This apparatus is provided with an image data memory 1 for storing two-dimensional image data of 4n bits in the X direction and m bits in the Y direction. Normally, the data in memory is
For example, reading or writing is performed in units of data of one word having a 4-bit or 8-bit structure. Therefore, this image data, as shown in the figure,
It is divided into strips with a width of n bits in the X direction.

Now, let us consider a case of processing an image a, b, or c, d consisting of a series of pixels as shown in the figure, among the images stored in the image data memory 1.

In this case, for example, it is only necessary to directly read the data of width n bits including the images a and b. However, the data reading is performed only in a unit divided in advance with a width of n bits as shown in the figure. Therefore, the image data memory is divided into two memory blocks 21 and 22, and the striped areas of the image data are divided into 11, 12 and 1, respectively.
3 and 14, the area 11 and the area 13 are set to the memory block 21.
And the areas 12 and 14 are stored in the memory block 22.

First, the reading of the images a and b will be described.
As shown in the memory blocks 21 and 22, n-bit data including the image a is stored in the memory block 21, and n-bit data including the image b is stored in the memory block 22. As for the images c and d, data are stored separately from the corresponding areas as in the memory blocks 21 and 22, respectively.

The data bus selection circuit 3 is a circuit for selecting a total of n bits designated by the processor 4 out of n bits + n bits of 2n bits of data input from the memory blocks 21 and 22 and outputting the selected bits. Therefore, when the image signal as shown in the data bus selection circuit 3 is input as shown in the figure, the image signals corresponding to the images b and a as shown in are output to the read rotator 51 side. When an image signal as shown in (1) is input to the data bus selection circuit 3, an image signal corresponding to the images d, c as shown in (3) is output. The image signal shown in
The arrangement is the reverse of the original images a and b that are to be read. Then, the rotator 51 sequentially shifts the data bit by bit in the direction of arrow 5'in the figure, and outputs the image signal corresponding to the images a and b as shown in the figure.

The same applies to the image signal shown in, and the rotator
Reference numeral 51 shifts the data one bit at a time in the direction of arrow 5'in the figure, and outputs image signals corresponding to the images c and d as shown in the figure.

As described above, the processor 4 can read an arbitrary one-word image from the two-dimensionally expanded image data and execute a predetermined process. or,
When the processor 4 attempts to write an image signal corresponding to such an image in the image data memory 1, the image signal corresponding to this is input to the writing rotator 52, and the image data memory 1 is reversed in the reverse order. Store the data in.

(Problems to be Solved by the Invention) When processing image data, a similar processing request is made for an image in which image signals are arranged in the Y direction. However, in the conventional image data processing apparatus as shown in FIG. 2, if the image to be processed does not consist of image signals arranged in the X direction, it can be read by one access. Can not. That is, in the case of image processing in which image signals are arranged in the Y direction, complicated processing is required if the image data memory is accessed n times and the data is rotated 90 degrees. Such a circuit has a drawback in that it takes much more time to process the image signals arranged in the Y direction than to process the image signals arranged in the X direction.

Therefore, the present inventor has developed an apparatus as shown in FIG. 3 so that the image data can be processed at high speed in both the X and Y directions (Japanese Patent Application No. 61-183484).

FIG. 3 shows an image data memory 1 for storing two-dimensional image data of 4 × 4 bit structure for simplification.
showed that.

The image data memory 1 stores image signals numbered 0 to 15 as shown in the figure. The X-direction and Y-direction in this figure represent the X-direction and Y-direction of the image as they are, and the pixels are arranged according to this image signal.

The processor 4 extracts four pixels arranged in the X direction or four pixels arranged in the Y direction from the image.
The reading process is performed as one word.

For this reading process, first, the buffer memory 5
Prepare 3,54,55,56. These buffer memories 53-56
Are memory devices each having an address capacity of 1 bit in width and 4 bits in depth. That is, each buffer memory 53-56
Can write or read pixel signals one bit at a time, and can store a total of four bits of image signals in the order of their addresses. The writing or reading can be performed by the address signal output from the address generation circuit 50. Controlled.

The pixel signals from the image data memory 1 are input to the buffer memories 53 to 56 as shown by the arrows. However, as shown in FIG. The image signals are rearranged so that the pixels lined up in 1 are sequentially shifted in the X direction by one pixel.

That is, the image signals arranged in the image data memory 1 in the order of 0, 1, 2, 3 are stored in the buffer memories 53 to 56 in that order, that is, 0, 1, 2, 3 The image signals stored in the memory 1 in the order of 4,5,6,7 are stored in the buffer memories 53 to 56 in the order of 7,4,5,6 so as to be shifted to the right by one bit. Has been done. The next image signals 8, 9, 10 and 11 are stored in the buffer memories 53 to 56 with a further shift of 1 bit, and the last image signals 12, 13, 14 and 15 are shifted with a shift of 3 bits. .

When the address generation circuit 50 outputs an address signal to each of the buffer memories 53 to 56 and an image signal is read out from each of the buffer memories 53 to 56, a signal such as (1) in the figure is read out.

In the figure, the case where the image signals 0, 1, 2, and 3 are directly read from the buffer memories 53 to 56 is shown.

In the figure, the image signals from the buffer memories 53 to 56
The case where 6 is read is shown. This is X when compared with the state where it is actually stored in the image data memory 1.
Since it is deviated by 1 bit in the direction, it is rotated by 1 bit as shown by the arrow in FIG. This processing is performed by the rotator shown in FIG.

In the figure, the case where the image signals corresponding to the pixels arranged in the Y direction are read out is shown. The image signal 0, 4, 8, 12 is read as it is by the address generation circuit 50 inputting a predetermined address signal to the buffer memories 53 to 56.

In the figure, an image signal corresponding to pixels arranged in the Y direction, which is an image signal shifted by 2 bits in the Y direction, 0, 14,
An example when 2, 6 are read is shown. In this case, the read image signal is rotated by 2 bits and then read by the processor 4.

As described above, from the image data memory 1,
When the image signals are read out in a predetermined order into a plurality of 1-bit wide buffer memories, the image signals having a predetermined width can be read out at high speed in both the X and Y directions. However, in this configuration, if the image data memory 1 has a large capacity, an extremely large number of buffer memories are required, and there is a problem that the processing becomes complicated as it is.

The present invention has been made by paying attention to the above points. Data is read at high speed in both the X and Y directions, and image data processing is freely and efficiently performed using a large capacity image data memory. It is an object of the present invention to provide an image data processing device capable of performing.

(Means for Solving the Problem) An image data processing device of the present invention is provided with an image data memory for storing image data in a two-dimensional array in orthogonal X and Y directions, and the image data is a pixel in each direction. The number of pixels, which is an aggregate of units arranged in the same number, is arranged and stored so that pixels arranged in the Y direction in the unit are sequentially shifted in the X direction by one pixel at a time. Two memory blocks each including the same number of memory element groups are provided, and a predetermined unit and the image signal corresponding to each pixel of a unit adjacent to this unit in the X direction or the Y direction are stored in different memory blocks. A memory address generation circuit for generating an address signal for reading an image signal and a selection signal for selecting a memory element group is provided to read in the X direction. If you want to extend, supply the same address to each memory block,
When reading in the Y direction, the addresses are changed in order, and the image signals of the adjacent units are changed in the X direction or Y direction.
The image signal corresponding to the consecutive pixels in the direction is read from each memory block, and a rotator that shifts the array with respect to the read image signal is provided to restore the image data consisting of consecutive pixels. The device of the invention divides the image data in the image data memory into a matrix first to form an aggregate of units, and among the units thus obtained, the units adjacent in the X direction or the Y direction are divided into different memory blocks. The image signal is stored.

In each memory block, the storage order of the image signals is devised so that the image signals corresponding to the pixels arranged in the X direction and the image signals corresponding to the pixels arranged in the Y direction can be taken out at one time.

If the memory address generation circuit generates and supplies a predetermined address signal to these memory elements, the image signal corresponding to the desired image can be read from any location in both the X and Y directions.

Since the read signals are stored in the memory element while being shifted in a predetermined direction, they are array-converted by the rotator and taken out.

That is, when the image to be read extends between two units, the image is read from a pair of adjacent units.

Therefore, if these are stored in separate memory blocks, the image signal corresponding to the image to be read can be read at once with one access.

(Examples) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the image data processing device of the present invention.

This apparatus includes a first memory block 201 and a second memory block 202 that store the image data 100 in two. And these memory blocks 201, 20
The image signal read from 2 is input to the rotator 300,
After that, it is read by the processor 400. Further, a memory address generation circuit 500 is provided to supply an address signal to the first memory block 201 and the second memory block 202.

Now, as shown in the figure, the image data 100 has X direction and Y direction.
A straight line along the direction, each of which is divided into, for example, four and is divided into a matrix. With this, the image data is 4 ×
4, that is, an aggregate of 16 units 101 in total. Each unit 101 has 4 bits in the X direction,
It is assumed that the pixel 102 is composed of 16 bits of 4 bits in total in the Y direction.

When dividing the image data 100, the number of divisions in the X direction and the Y direction may be arbitrary, but the pixels forming the unit 101 should be arranged in the same number in the X direction and the Y direction in signal processing. Requires.

First memory block 201 and second memory block 2
02 has a capacity capable of storing all pixels constituting the image data 100 shown in FIG. still,
In this case, the first memory block 201 stores the image signal of the unit of the image data 100 shown in FIG. Then, the second memory block 202
Stores the image signal of the unit with the reference numeral # 2. That is, the storage locations of the first memory block 201 and the second memory block 202 are selected so that units adjacent to each other and sharing the side 103 are separately stored. The side 103 is the boundary between the units shown in the enlarged view of the unit 101 in the figure.

Also, the processor 400 can send 1 word (width 4
(Bit) data is read and processed. Therefore, as shown in the enlarged portion of the unit 101 in the figure,
For example, the images a and b made up of 4-bit pixels continuous in the X direction and the images c and d made up of 4-bit pixels continuous in the Y direction are read out. In addition, all 1
The image e contained in one unit may be read out.

A more detailed connection diagram of each block in FIG. 1 is shown in FIG.

In the figure, first, the first memory block 201 is 4
It is composed of two memory devices M13, M12, M11 and M10.
The second memory block 202 is also composed of four memory elements M23, M22, M21, M20. That is, each memory block is provided with four memory elements, the number of which corresponds to the number of pixels in the X direction of one unit 101 of the image data 100 shown in FIG. Each memory element is composed of a memory element group having an address capacity of 1 bit in width and 32 bits in depth.

That is, the image data in the image data memory 110 is composed of 4 × 4 units as in the example shown in FIG. 1, and one memory block has pixel signals of 4 × 2 units. Are stored in each memory block, and four memory elements are provided in each memory block. Therefore, one memory element must store image signals for two units. From this, one memory device stores 4 × 4 × 2, that is, 32-bit image signals.

On the other hand, the memory address generation circuit 500 includes an X / Y direction register 510 that stores data indicating the array direction of an image to be read or written, and an X coordinate register 520 that stores data indicating the X coordinate of the start point of the image. ,
A Y coordinate register 530 that stores data indicating the Y coordinate is provided. Then, based on these signals, the first
In order to output an address signal to each memory element of the memory block 201 and the second memory block 202, a unit address generating section 540, a pixel address generating section 550, and an element selecting section 560 are provided.

The unit address generator 540 has an X / Y direction register 51
X / Y direction signal 511 output from 0 and X coordinate register 520
Upper 2 bits X of X coordinate (X ₃ , X ₂ , X ₁ , X ₀ ) output from
₃ , X ₂ and the Y coordinate output from the Y coordinate register 530 (Y ₃ ,
_{Y 2, Y 1, Y 0} ) high-order 2 bits Y ₃ of, Y ₂ and inputs. In addition to the X / Y direction signal 511 output from the Y / Y direction register 510, the pixel address generating unit 550 also outputs the X coordinate (X ₃ , X ₂ , X ₁ , X ₀ ) output from the X coordinate register 520. Lower two bits X ₁ , X _{0 of} the Y coordinate and Y coordinate (Y ₃ , Y ₂ , Y ₁ ,
Y ₀₎ low order 2 bits Y _1, Y ₀ is input among.

Further, the outputs of the X coordinate register 520 and the Y coordinate register 530 are directly input to the element selection unit 560. Then, from the unit address generation unit 540, three units each specifying which unit, out of the image signals stored in each memory element in the first memory block 201 and the second memory block 202, is to be read out. Two sets of bit-configured unit addresses 501 are output. In addition, the pixel address generation unit 550 outputs four sets of pixel addresses 502 each having a 2-bit configuration that specifies which pixel of the unit designated by the unit address 501 the image signal corresponding to is read. From the element selection unit 560, a selection signal 503 of 1-bit configuration for selecting which one of the memory elements connected two by two is connected to the data bus 301 of four 4-bit configuration. Are output.

Therefore, the unit address 501 is assigned to each memory element of the first memory block 201 and the second memory block 202.
The pixel address 502 and the element selection signal 503 are input, and the read 1-bit signal is connected so as to be output to the rotator 300 via the data bus 301.

The rotator 300 is composed of a read unit 310 and a write unit 320 connected to the data bus 301, and a rotate amount generation unit 330 that instructs these to the rotate amount.

The reading unit 310 is a circuit as shown in FIG. 3, which shifts the image signal from 1-bit rotate to 3-bit rotate as appropriate and outputs it to the output side. Processor
400 reads the image signal after rotation through the 4-bit data bus 302, and outputs the data to be written in the image data memory 110 toward the writing unit 320 of the rotator unit via the data bus 302. To do.
The rotate amount generation unit 330 includes the memory address generation circuit 500.
X coordinate output from the X coordinate register 520 (X ₃ , X ₂ , X ₁ ,
Accept the lower two bits Y _1, Y ₀ of the lower 2 bits X _1, X _0, and Y Y coordinates output from the coordinate register _{(Y 3, Y 2, Y} 1, Y 0) of the X _0), treated It is a circuit that calculates the rotation amount according to the data to be stored and controls the rotation amount of the reading unit 310 and the writing 320.

Next, the relationship between the image signals stored in the image data memory 110 and the image signals stored in the first memory block 201 and the second memory block 202 will be described in detail.

FIG. 5 is an explanatory diagram specifically showing the configuration of the memory block and the image signal stored therein.

In the figure, the image data memory 110 stores image signals of 16 bits in the X direction and 16 bits in the Y direction, and each image signal is numbered from 0 to 255.

Also, as shown on the right side of the figure, the first memory block 20
Each of the memory elements M13, M12, M11, M10 constituting 1 has a capacity of 1 bit in width and 32 bits in depth, and its data is read / written by an address of 5 bits. Of these, the upper 3 bits are the unit address and the lower 2 bits are the pixel address.

That is, for example, focusing on the unit of 4 × 4 bits in the upper left corner of the image data memory 110, 0,1,2,3,16,17,18,19,32,33, 34,35,48,49,
The image signals of 50 and 51 are stored. These image signals are transmitted to the memory elements M13, M12, M11, M1 of the first memory block.
It is stored at addresses 0 to 00000 to 00011.

 This storage method is as follows.

That is, the array conversion of the image signals is performed so that the pixels arranged in the same column in the X direction in advance in this unit are sequentially shifted in the X direction by one pixel. This is performed in the same manner as in the case where the image signals are stored in the buffer memories 53 to 56 already described in FIG. Similar to the one shown in FIG. 3, the image signals after the array conversion are divided in the Y direction and stored in separate memory elements. The image signal of the unit on the right side or the lower side adjacent to this unit is the second signal as shown in FIG.
Stored in the memory block 202. This storage method is the same.

Next, the operation of the unit address generator 540 shown in FIG. 4 will be described.

FIG. 6 is a specific connection diagram of the unit address generation unit.

This unit address generator 540 is a register for X / Y direction.
510, an X-coordinate register 520, an address converter 541 that receives the outputs of the Y-coordinate register 530, the output of the address converter 541 and some bits of the X-coordinate and the Y-coordinate, Y ₃ , X ₃ , It is composed of an adder 542 and an adder 543 which accept Y ₂ .

The address converter 541 is a circuit for obtaining 4-bit output signals Q1, Q2, Q3, Q4 corresponding to the signals input from the registers 510, 520, 530, as shown in FIG. 8 later.
The adder 542 also outputs the X value output from the X coordinate register 520.
_{Coordinates, X 3, X 2, X} 1, and the most significant bits X ₃ of X _0, Y coordinate outputted from the Y coordinate register _{530, Y 3, Y 2,} Y 1, the upper two of the Y ₀ Address translator 541 accepting bits Y ₃ and Y ₂
Add a predetermined value to the signals Q3 and Q4 output from the
It is a circuit for outputting a unit address for the memory block. Similarly to the adder 542, the adder 543 receives signals from the X coordinate register 520 and the Y coordinate register 530 and also receives the output signals Q1 and Q2 of the address converter 541 to perform a predetermined calculation, and then the second adder This is a circuit that outputs a unit address for a memory block.

The operation of this circuit will be described in detail with reference to FIGS. 7 and 8.

FIG. 7 is an explanatory diagram of the principle for selecting a unit address.

In the figure, as described above, the image data memory 100 is composed of 4 × 4, that is, 16 units,
Since each unit is composed of a 16-bit image signal, a total of 4 × 4 × 16-bit image signals are divided into two and stored in the first memory block 201 and the second memory block 202. It will be. That is, an image signal of 4 × 4 × 8, that is, 4 × 32 bits is stored in the first memory block. The same applies to the second memory block. Then, as shown in the figure, assign a unit number <0 to each unit in advance.
> To <7>. In this case, the units stored in the first memory block 201 are hatched, and the units stored in the second memory block 202 are also assigned the same numbers.

In this way, <
Units 0> to <7> are stored.

Here, the X-coordinate and the Y-coordinate in the image data memory 110 are 4-bit digital data, respectively, as described above, but pay attention only to the _second bit from the top, that is, X ₂ and Y _2. However, as shown in FIG. 7, the positions of 0, 1, 0, 1 and each unit can be identified. That is, for example, a unit in which X ₂ is 0 and Y ₂ is 0 is a unit in the upper left corner, two units to the right and two units below it, and two units to the left, a total of four units. Become. By utilizing such a relationship, unit addresses can be created as shown in FIG.

In FIG. 8, first, the input signal and the output signal of the address converter 541 shown in FIG. 6 are shown in the left end portion thereof. The input signal is an X / Y direction signal, which means that when 0, the images lined up in the X direction are processed, and when 1, the images lined up in the Y direction are processed. Further, X ₂ and Y ₂ are data having the contents as described with reference to FIG. Then, the address converter 541 shown in FIG. 7 outputs data of contents such as Q1, Q2, Q3, Q4 corresponding to these input signals. Further, on the right side, units selected in pairs in each memory block are displayed. That is, for example, when the unit in the upper left corner of FIG. 7 is a unit including the start point of the image to be read, the unit on the end point side of the image is the one to the right or below. The input signal of the address converter 541 limits the unit on the start side and the unit on the end side, and the combination thereof is shown in the table of FIG.

Then, in these cases, whether the unit stored in the first memory block is on the starting point side or the unit stored in the second memory block is on the starting point side is indicated in the column of pair relation in FIG. it's shown. That is, for example, it is assumed that the unit on the start point side is the <0> unit of the first memory block. In this case, the input signals X ₂ and Y ₂ of the address converter 541 are both 0. And if X / Y is 0, X
Since it is an image of the direction, the unit to be paired is
It becomes <0> of the first memory block and <0>(# 1- # 2) of the second memory block. Therefore, if the unit number of the first memory block is selected as 0, +0, that is, the same unit number 0 is selected for the end point side,
This is output from the data address generator 540 as the unit address of FIG.

Further, when X / Y = 1 at the same start point, that is, when the images are arranged in the Y direction, the paired units are <0> of the first memory block and <1> of the second memory block.
(# 1- # 2). In this case, when the unit number of the first memory block is selected as 0, 1 is added to the unit number to generate the unit address of the second memory block on the end point side.

Also, the unit that becomes the starting point is the second memory block <
If 4>, then X ₂ = 1 and Y ₂ = 0. And X / Y ＝
0, that is, when the images are lined up in the X direction, the paired units are the second memory block <4> and the first unit.
Memory block <6>(# 2- # 1). Therefore, in this case, 2 is added to the unit number 4 of the first memory block to generate the unit address of the first memory block.

When X / Y = 1 at the same start point, that is, when the images are arranged in the Y direction, the paired units are <4> of the second memory block and <5> of the first memory block.
(# 2- # 1). Therefore, in this case, 1 is added to the unit number of the first memory block to generate the unit address of the first memory block.

The adders 542 and 543 shown in FIG. 6 generate the respective unit addresses as described above and output the signals to the first memory block and the second memory block.

FIG. 9 shows the memory blocks 201 and 202 shown in FIG.
In the explanatory diagram of the circuit operation for generating the lower 3 bits of the 5-bit address signal, the pixel address generating unit 550 shown in the fourth generates the pixel address according to this table.

That is, the pixel address generator 550 shown in FIG. 4 receives X / Y and X ₁ , X ₀ and Y ₁ , Y ₀ as shown in FIG.
First memory block 201 and second memory block 202
A 2-bit pixel address signal as shown in the table is output to each of the four memory elements provided in.
Thus, when reading in the X direction, the same address is supplied to each element, and when reading in the Y direction, the address is sequentially incremented by one. The reason for this is apparent from FIG. As a result, the image signal is read out in the X direction or the Y direction in the same manner as described in FIG.

FIG. 10 is a table showing the rotation amount when the image signal thus read is rotated by the rotator 300 shown in FIG.

In this table, memory elements M13, M12, M11, M10, M23, M2
Any one of 2, M21 and M20 is selected by the element selection unit 560 of FIG. 4 and connected to the data bus 301.
The circles in the table indicate which memory element is selected in which case, and the circles indicate the image signal to be rotated to the MSB (most significant bit).

That is, for example, the image signal at the top of the table is M13, M12, M1.
Since the image signal that is read from the M1 and M10 is located at the left end of the M1 and M10, the image signal is read as it is to the processor 400 without being rotated. The image signal of the next stage is 2 from the left.
Since the second MSB image signal is stored, the image signal is rotated by 1 bit and output. In addition, the memory element is selected by various combinations as shown in the drawing according to the image to be read, and the image signal is read.

As can be seen from the figure, the rotation amount is ₀ , ₁ , 2, 3, 1 according to the change of the signals of X ₁ , X ₀ , Y ₁ , Y ₀ input to the rotation amount generation unit 330. It's changing like 2,3. However, whether the read image is arranged in the X direction or the Y direction does not affect the rotation amount. Therefore, the rotation amount is uniquely determined by the four signals X ₁ , X ₀ , Y ₁ , and Y ₀ .

For the case of X ₂ = 0, Y ₂ = 0 or X ₂ = 1 and Y ₂ = 1
When X ₂ = 1 and Y ₂ = 0 or X ₂ = 0 and Y ₂ = 1 the memory element
M13 and M23, M12 and M22, M11 and M21, and M10 and M20 are replaced, respectively. It goes without saying that the opposite is true when writing data.

Finally, a specific read operation of the device of the present invention will be described. For example, the image data memory shown in FIG.
At 110, a 4-bit image whose starting point coordinates are (1, 5) is read and written.

This data is 81,82,8 as shown by the hatching in the figure.
If it is 3,84 and the coordinates of its starting point are displayed in binary,
It will be 0001,0101. In this case, the unit address is 001 for both the first memory block and the second memory block, and the unit <1> described in FIG. 7 is selected from both blocks. The pixel address is 01 for all memory elements. That is, the address of the memory element is 5 in decimal. Further, the element selection signals at this time are X ₂ = 0 and Y ₂ = 1 so that the memory element
M23, M12, M21, M20 are selected. As can be seen from FIG. 5, the image signal thus output is an image signal in the form of being shifted by 2 bits, so it is read by the processor by shifting it by 2 bits by the rotator.

Also, this time, the coordinates of the starting point are the image data memory 110
Consider the case of (3, 3) of (3, 3) and reading and writing image data arranged in 4 bits in the Y direction. In this case, the coordinates of the starting point are represented by the binary system as 0011,0011. The image signals are 51,67,83,99.

Therefore, the address of the first memory block is <0>,
The address of the second memory block becomes <1>,
Address 0001 of memory device M11 of memory block 201 of
The image signal is read from the address 0101 of the memory element M23 of the first and second memory blocks 202, the address 00110 of the memory element M22, and the address 00100 of the memory element M20. Also in this case, since the image signal is shifted by 2 bits, it is rotated and read by 2 bits.

The image data processing device of the present invention is not limited to the above embodiments.

When the image data is divided into a matrix, the number of divisions or the bit configuration of the divided units may be freely selected. Also, the circuits for address generation, data array conversion, etc. may be replaced with circuits having similar functions as necessary.

(Effects of the Invention) According to the image data processing device of the present invention described above, various two-dimensional image data are read in word units, and for example, this is rotated or density conversion is performed, for example, enlargement / reduction is performed, and various image data is processed. It is possible to perform a process of performing arithmetic processing and then storing it again in the image data memory at an extremely high speed. Moreover, since the image data arranged in the X direction and the image data arranged in the Y direction can be processed by the same algorithm, there is no problem that the calculation speed differs depending on the direction, and the processor can be used efficiently.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an image data processing device of the present invention, FIG. 2 is a block diagram of a conventional image data processing device, and FIG. 3 is an operation explanatory diagram of another conventional image data processing device. FIG. 4 is a wiring diagram of an embodiment of the device of the present invention, FIG. 5 is an explanatory diagram of a memory block configuration and an image signal to be stored, FIG. 6 is a wiring diagram of a unit address generating section, and FIG. 7 is a unit address. FIG. 8 is an explanatory diagram for selection, FIG. 8 is an explanatory diagram of the operation of the unit address generating section, FIG. 9 is an explanatory diagram of the operation of the pixel address generating section, and FIG. 100 ... Image data, 101 ... Unit, 102 ... Pixel, 103 ... Side, 110 ... Image data memory, 201 ... First memory block, 202 ... Second memory block, 300 ... Rotator , 400 ... processor, 500 ... memory address generation circuit, 501 ... unit address signal, 502 ... pixel address signal, 503 ... element selection signal.

Claims (1)

(57) [Claims] 1. An X-direction and a Y-direction orthogonal to image data.
An image data memory for two-dimensionally arranging in each direction is provided, and the image data is a set of units in which the number of pixels in each direction is the same, and one pixel is arranged in the Y direction in each unit. Two memory blocks, each of which has the same number of pixels as the number of pixels and stores the image signals after array conversion so that the image signals are sequentially shifted in the X direction, are provided in the X direction or the Y direction with respect to the predetermined unit. An image signal corresponding to each pixel of an adjacent unit is stored in a different memory block, and a memory address generation circuit that generates an address signal for reading an image signal from the memory block and a selection signal for selecting a memory element group is provided. The same address is supplied to each memory block when reading, and the address when reading in the Y direction. Image signals corresponding to pixels that are consecutive in the X direction or Y direction among the image signals of adjacent units are read from each memory block, and a rotator that shifts the array with respect to the read image signals is provided, and consecutive pixels are changed. An image data processing device characterized by restoring image data consisting of.