JPS62205452A - Memory control system - Google Patents

Abstract

PURPOSE:To provide flexibility and a high speed to the processing of two-dimensional information by providing an address generating circuit to generate a different address to plural memory devices and a data changing-over circuit to execute the rearrangement of data. CONSTITUTION:An address generating circuit 1 generates a reference address 4 and addresses 6-9 to send to four memory devices 10-13 from a control signal 5 to designate a longitudinal and horizontal direction which is a simultaneous access direction of two-dimensional information. A data changing-over circuit 2 distributes a data bus 3 with the external part, sends to the memory devices 10-13 at the time of writing, and synthesizes and outputs to the external part at the time of reading. Thus, by making variable the rule to generate the address of respective memory devices from a reference address, the information of plural elements that the memory of two-dimensional information continues in the longitudinal or horizontal direction or comes to be a 2X2 block can be simultaneously accessed and the effect that the flexibility and the high speed can be provided to the processing of the two-dimensional information can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage control system, and particularly to a read/write control system in a storage circuit for storing two-dimensional information.

``Big Brother and 1'' A storage device basically has a configuration in which one bundle of address buses, one bundle of data buses, and a control port are drawn out as shown in Figure 2, and information between the storage device and the outside is connected. Transfers can only be made for one address at a time. Storing two-dimensional information requires a large storage device, but conventional techniques include a storage circuit that expands the address bus by connecting multiple storage devices as shown in Figure 2, and two-dimensionally adjacent storage devices. There are memory circuits that expand the data bus by concentrating all the points at the same address.

Of the conventional memory circuits mentioned above, the former has the same basic form as shown in Figure 2 as a whole, and because it has one address bus system, only data for one address can be read or written at the same time. As a result, there is a drawback that the access time becomes extremely long in order to handle two-dimensional information of the maxim ω.

In addition, the latter type of conventional memory circuit is efficient in the sense that information from multiple points can be handled in one access, but on the other hand, the combination of two-dimensional adjacent points becomes unique at the time of writing, and when reading The disadvantage is that there is a lack of flexibility in handling two-dimensional information because it cannot be read out in other ways.

SUMMARY OF THE INVENTION An object of the present invention is to provide a storage control method that allows faster access to the stored contents of large amounts of two-dimensional information.

Another object of the present invention is to provide a storage control system in which combinations of two-dimensional adjacent point information that can be processed in one access can be arbitrarily selected.

Structure of the Invention According to the present invention, there are provided a plurality of storage devices for storing two-dimensional information, and an address conversion unit predetermined for each of the storage devices based on a reference address serving as a predetermined reference. address generation means for calculating addresses based on logical formulas; and address generation means provided between each of the storage devices and an external data bus for rearranging data during data access;
There is obtained a storage control system characterized in that the data switching means performs data synthesis and one-division processing, and the two-dimensional information is accessed simultaneously for a plurality of storage elements.

Example Next, this embodiment will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The address generation circuit 1 generates four storage devices f! from a reference address 4 and a control signal 5 specifying the vertical and horizontal directions, which are directions in which two-dimensional information is simultaneously accessed. Address 6 to send to 10-13
This is a circuit that generates 9. The data switching circuit 2 distributes the external data bus 3 during writing to the storage devices 10 to 1.
This is a circuit that sends the signals to 3, and when reading, synthesizes the signals and outputs them to the outside.

As a specific example, a case will be explained in which the circuit is implemented as a circuit for storing multi-valued image information having a size of 64×64 dots and each dot is represented by 4 bits. By preparing four storage devices, it is possible to simultaneously access four consecutive pixels in the vertical direction (hereinafter referred to as vertical direction specification) and simultaneously access four consecutive pixels in the horizontal direction (hereinafter referred to as horizontal direction specification). The external data bus is made up of 16 bits. In addition, in order to distribute the memory space corresponding to 64x64=4096 dots to four storage Vl locations 10 to 13, the address buses 6 to 9 of each storage device are N
oq2 (4096/4)=10 bits. In order to represent the entire space, the reference address is 6 bits in the X direction and 6 bits in the Y direction, a total of 12 bits in width.

Part of the image information is shown in FIG. In order to distinguish between the four storage devices, each of the storage devices 10 to 13 is designated as A, B, C, and D.
and 1. , each memory pixel shared by each memory Vt Ei 10 to 13 is written in each frame in Fig. 3, and A, B, C
, The number added to the lower right of D indicates the address of each storage device.

As an example of the operation of the address generation circuit 1, a case where the reference addresses are X address -2 and Y address -1 will be explained below. When specifying the horizontal direction, address 1 in the storage device
0 and address 11 to devices B and C in 4a. Also, for the same standard address, when specifying the vertical direction, set address 10 for the storage device, 20 for 8, 30 for B, etc.
Send 40 to C each. Assume that the addresses to be sent to each storage device are determined in the same manner for other reference addresses.

On the other hand, as an example to explain the function of the data switching circuit 2, when specifying the horizontal direction, the information of the leftmost pixel is transferred to the upper 4 bits of the external data bus, and when specifying the vertical direction, the information of the uppermost pixel is transferred to the external data bus. Consider controlling to ride on the upper 4 bits of the data bus. In the case of pixel information storage device allocation as shown in FIG. 3, it can be seen that the data arrangement should be rotated by 4 pixels (-) based on the reference address.

An implementation example of the address generation circuit will be explained below using the drawings. FIG. 4 is a block diagram of an implementation example of the address generation circuit 1. Address calculation circuits that receive the base L1ζ address as input are provided separately from the horizontal circuits 19 to 22 and the vertical circuits 23 to 26 for the four storage devices, and these horizontal direction circuits are respectively provided by specifying the direction.

Selector 27 to select one of the address calculation circuits in the vertical direction.
30.

Taking as an example the address n output circuit to the horizontal direction designated address output circuit, it is assumed that the address A is assigned according to the example of FIG. Set the reference address to X=O, Y=O
Then, in the case of horizontal direction specification, A O, B O, CO, D
Since O is accessed at the same time, it is sufficient to output O as the address of A, and the standard 7 dots L/strX=1
, Y=(le then B O, G O.

Since DO and AI are accessed simultaneously, the address of A is 1.
will be output. Similarly, Δ addresses specified in the horizontal direction for all reference addresses are as shown in FIG.

Therefore, the horizontal direction designation address calculation circuit is a logic circuit that performs input/output according to the example of FIG. 5. Similarly, each address calculation circuit can be logically described and realized as a logic circuit according to the description.

Next, an implementation example of the data switching circuit 2 will be explained using the drawings. FIG. 6 is a block diagram of one implementation example of the data switching circuit. It is assumed that each pixel is associated with a storage device according to the example shown in FIG. 3, and a case of horizontal direction specification will be explained. When the data on the external data bus is specified in the horizontal direction as shown in Figure 7, it is four bits each from the high-order side: left, middle left, middle right, and right, and when it is specified in the vertical direction, it is the upper pixel information. Assume that there are four pixel information, 4 bits each from the side: upper, middle, lower middle, and lower. When the reference address is set to X=O and Y=0, simultaneous access is performed to A O, B O, G O, and D O, and the upper 4 bits of the external data bus and the internal data bus A are coupled. Similarly, the next 4 pins 1- and B,
The next four bits, the lower four bits of C1, and the internal data bus of D are coupled. Set the reference address to X=1. If Y-0, simultaneous accesses are BO, CO, Do, A1, and the upper 4 bits of the external data bus, the 81st 4 bits, and C2.
The next 4 bits are taken and the lower 4 bits are coupled to A's internal data bus 2.

One embodiment for enabling the bus coupling operation described above is shown in the sixth example.
This figure shows that the above-mentioned bus joining operation
Because of the property that the same operation is performed depending on the value of (X+Y) mod 4, output selectors 31 to 34 and input selectors 35 to 38 are used. In FIG. 6, the upper half selectors 31 to 34 are readout circuits that operate only during readout, and the lower half selectors 35 to 38 are sinking circuits that operate only during tongue thrusting.

The embodiment described above is only an example, and as mentioned above, the
Regarding the storage of multivalued image information in which 1 dot is represented by 4 bits in a 4x64 dot size, only a configuration in which the external data bus is 16 bits and four storage devices are provided to simultaneously access 4 dots horizontally or vertically is available. explained. Also, the correspondence between each storage device and pixel,
Address generation circuits and data switching circuits are also examples, and different logic descriptions and circuit configurations can be realized by designing in accordance with the actual application. In the following, other embodiments will be described in comparison with the above-mentioned embodiment (referred to as the first embodiment).

The second embodiment is an example in which binary image information is handled. In this case, the capacity of the image information will be 1/4 of that of the first embodiment, and at the same time, the data bus of each storage device will be 1 bit, and the external data bus will be 4 bits. Therefore, considering that the external data bus remains 16 bits and 16 pixels can be accessed simultaneously, 16 memory devices δ will be installed. At this time, at a3 in FIG. 1, the address generation circuit 1 constitutes a circuit for generating addresses for 16 different lines, and the data switching circuit 2 is also configured to be capable of switching 16 buses. This second embodiment can be realized using the same concept as the first embodiment. FIG. 8 shows an example of the correspondence between storage devices and pixels that is effective in realizing the second embodiment.

Next, as a third embodiment, an example will be described in which not only elements that are continuous in the vertical and horizontal directions but also blocks of elements such as 2×2, 3×3, 4×4, etc. are to be accessed simultaneously. In this case, the most important point to be aware of is that no matter what block is selected, the correspondence between storage devices and pixels must be established so that different addresses will not be accessed at the same time for the same storage device. . For example, in the case of the correspondence in Figure 3, the four points A O, B in the upper left corner as a 2 × 2 block
O.

310, simultaneous access to CIO is limited to storage device B
Therefore, both addresses 0 and 10 must be accessed at the same time, which is impossible.

As a countermeasure against this kind of inconvenience, there is a countermeasure to install extra storage devices. FIG. 9 is an example of the correspondence between the storage device and the pixels for flexible simultaneous access to a 2×2 block with continuity in the vertical and horizontal directions when a storage device port is additionally installed. continuous, horizontal continuous, 2x2
This makes it possible to simultaneously access different storage devices even within a cluster. In this example, the address generation circuits are arranged vertically and horizontally for five storage devices, respectively.

The circuit configuration is such that one of the 2×2 wash addresses is sent, and the data switching circuit connects the data buses of four storage devices selected from the five storage devices with an external data bus. The circuit configuration is as follows.

As described in detail, the present invention includes an address generation circuit that generates different addresses for a plurality of storage devices, and an arrangement of data between a data bus of each storage device and an external data bus. It is equipped with a data switching circuit that performs switching, division and synthesis, etc., and by making the rules for generating addresses for each storage device from a reference address variable, it is possible to store two-dimensional information that is continuous in the vertical or horizontal direction or in 2×2 blocks. It has the effect of making it possible to simultaneously access information on multiple elements such as , and giving flexibility and high speed to the processing of two-dimensional information.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a first embodiment of a two-dimensional information storage circuit according to the present invention, FIG. 2 is a 1079 diagram of a basic storage device,
FIG. 3 is a diagram showing the correspondence between each pixel of two-dimensional image information and the storage device in the first embodiment, FIG. 4 is a block diagram of the address generation circuit in the first embodiment, and FIG. FIG. 4 is an input/output correspondence diagram showing the input and output of the horizontal specified address calculation circuit A, FIG. 6 is a block diagram of the data switching circuit in the first embodiment, and FIG. 7 is an external data bus in the first embodiment. FIGS. 8 and 9 are diagrams showing the correspondence between each bit of 2D and each pixel when horizontal or vertical designation is made, respectively, and FIGS. It is a diagram showing correspondence. Explanation of symbols of main parts 1...Address generation circuit 2...Data switching circuit

Claims (2)

[Claims] (1) A plurality of storage devices for storing two-dimensional information, and a logical formula for address conversion predetermined for each of the storage devices based on a reference address serving as a predetermined reference. Address generation means for calculating an address;
A data switching means is provided between each of the storage devices and an external data bus to rearrange data, combine data, and divide data during data access;
A storage control method characterized in that when accessing dimensional information, multiple storage elements are accessed simultaneously. (2) A patent claim characterized in that a plurality of storage elements can be freely selected by changing the logical formula for address calculation in the address generation means and the data processing mode in the data switching means as desired. Storage control method in the first term of the range.