JPH0727558B2 - Image memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image memory device capable of high-speed random access in pixel units in computer graphics and image processing.

2. Description of the Related Art A conventional image memory device has a structure as shown in FIG. Reference numeral 11 is a selector for switching the address from the central processing unit (hereinafter referred to as CPU) and display address to interleave, and 12, 13 and 14 are memory elements corresponding to the bits constituting each pixel of the image, and are composed of n elements. When the CPU address stored therein is supplied to the memory, the CPU reads / writes data from / to the memory element, and when the display address is supplied, the data output from the memory element is output to a monitor or the like.

The operation of the conventional image memory device configured as described above will be described below.

FIGS. 4 (a), (b), (c) and (d) are timing charts according to the conventional example of FIG. 11 selectors
The CPU address and the display address are alternately supplied to the memory device by the selector control signal of FIG. At this time, the CPU address is common to each memory element, and moreover, the bit arrangement of the CPU data bus and the bit arrangement of each memory element are fixed. Further, the bit arrangement of the data lines output from each memory at the time of display access is also fixed.

Problems to be Solved by the Invention However, in the above configuration, when it is desired to write to a specific screen having a split screen by CPU access in an image divided in the depth direction even with a 1-pixel n-bit configuration, First, data must be read from the memory device, and only a specific bit must be changed and rewritten. For example, when n = 16, in an image divided into four in the depth direction, a specific divided screen, for example, #
When writing to a divided screen (corresponding to 4 bits from MSB of CPU data bus) corresponding to the memory elements 1 to # 4, pixel data of 16-bit width is read, converted from MSB to 4 bits, and rewritten. Data processing time becomes slow.

An object of the present invention is to eliminate the above-mentioned conventional problems,
An object of the present invention is to provide an image memory device in which an image memory composed of n memory elements corresponding to the number of bits per pixel (n) is divided into screens in the depth direction and which can be randomly accessed in each divided screen. And

Means for Solving the Problems According to the present invention, n memory elements corresponding to the number of bits per pixel (n), addresses of random access from a central processing unit and division of a screen in the depth direction, and divided screens are provided. Input the split screen designating signal and
N which is a random access address of each memory element
Address calculators, n selectors for selecting the random access address and the display address and supplying them to the memory element, and data conversion at the time of random access from the central processing unit is performed by the split screen designating signal. An image memory device comprising a first data converter and a second data converter for performing data conversion of a memory element output at the time of display access, wherein each division unit is used in a screen division in an exponential multiple of 2 in a depth direction. It enables random access.

Operation With the above configuration, it is possible to read and write only a specific divided screen divided into an exponential multiple of 2 in the depth direction by random access. Therefore, it is possible to continuously access a plurality of divided images, and Direct memory access (DMA) transfers to split screens can be easily realized.

Embodiment FIG. 1 is a block diagram showing an embodiment of the image memory device of the present invention. 31,32,33 is the number of divided screen CPU address,
And an address calculator that calculates an address for accessing a specific split screen, 34, 35, 36 are selectors that switch between the display address and the CPU address after the address calculation, 3
7,38,39 are memory elements corresponding to the number of bits of pixels, 40 is C
The first data converter (1) 41 for converting the bit arrangement between the CPU data bus and the memory data bus of the memory device in the case of PU access sends 41 the display data output from the memory device to the display. It is the 2nd data converter which changes the bit arrangement at the time of doing.

The operation of the image memory device of the present embodiment configured as described above will be described based on the split screen of FIG.
In FIG. 1, n = 8 and CPU data bus width = 8. Further, it is assumed that an image composed of 8 bits for one pixel is divided into two, and the divided screens 1 and 2 are formed by divided pixels of 4 bits each.

The display address is counted up as 0, 1, 2, ..., and when one screen output is completed, it is repeated from 0 again. This display address is selectors 34, 35 from # 1 to # 8,
36 by the memory element 37,3
Supplied as 8,39 addresses. On the other hand, the CPU address is determined by the arithmetic units 31, 32 and 33 of # 1 to # 8 in accordance with the number of divided screens and the divided screen designating signals for designating the divided screens 1 and 2 respectively. Executes the address operation supplied to 39. When accessing split screen 1 here, the CPU
If the address is "0", the address calculator output from # 1 to # 4 is "0", and the address calculator output from # 5 to # 8 is "1"
Is. Conversely, when accessing the split screen 2, if the CPU address is "0", the address calculator output from # 1 to # 4 is "1" and the address calculator output from # 5 to # 8 is "0". "Is.

When accessing the split screen 1, the MSB (D7) of the CPU data bus of the first data converter (1) 40 is connected to the data line (M7) of the memory element 37 of # 1. Is # 2 and the data line (M6) of the memory element 38 is in sequence, and D0 is #
8 memory device 39 is converted to be connected to the data line (M0). On the contrary, when the split screen 2 is accessed, it is connected to D7M3, D6M2, ... D4M0, D3M7, ... D0M4. When the split screen 1 is accessed when the CPU address is "1", the address calculator outputs of # 1 to # 4 are "2",
The output of the address calculators of # 5 to # 8 is "3", and vice versa when the divided screen 2 is accessed.

That is, the address calculators # 1 to # 4 output the address twice the CPU address when accessing the divided screen 1, and add 1 to the twice the CPU address when accessing the divided screen 2. Output the address. The address calculators # 5 to # 8 output the opposite.

On the other hand, in the second data converter (2) 41, when the display address is “0”, the memory elements 37, 38, # 1 to # 8,
The data output of 39 is each data line, and M _{7 to} M ₀ are M _m = Q _m (m = 0 to 7) in connection with the data lines Q _{7 to} Q ₀ of the display data bus, and the display address is “ In the case of 1 ", M _m = Q _{m + 4} (m = 0 to 3), M _{m + 4} =
It is connected to Q _m (m = 0 to 3). That is, when the display address is an even number, M _m = Q _m (m = 0 to 7), and when the display address is an odd number, M ₄ = Q _{m + 4} (m = 0 to 3), M _{m + 4} = It is connected to Q _m (m = 0 to 3).

The number of split screens is 2, but it is an exponential multiple of 2, that is, 8 splits, 4
Address converter 31, 32, 33 for each of division, 2 divisions, and 1 division
CPU address conversion and first and second data converter 4
The operation of 0,41 is also easy.

As described above, according to the present embodiment, the number of memory elements corresponding to the number of bits per pixel, the address calculator for calculating the random access address of each memory element, and the random access address and the display address are alternated. A screen divided in the depth direction by providing a selector for supplying each memory element, a first data converter for performing data conversion at random access, and a second data converter for performing data conversion of display data. Can be randomly accessed at high speed.

According to the present invention, the number of memory elements corresponding to the number of bits per pixel, an address arithmetic unit for performing an address operation at the time of random access of each memory element, and a data conversion at the time of random access are provided. By providing the data converter of No. 2 and the second data converter for converting the data output at the time of display access, it is possible to read and write only a specific split screen divided into exponential multiples of 2 in the depth direction by random access. Therefore, this is an image memory device that enables continuous access to a plurality of divided images and can easily realize direct memory access (DMA) transfer to a specific divided screen.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a correspondence diagram of the split screen of FIG. 1 and a memory element, FIG. 3 is a block diagram of a conventional image memory device, and FIG. It is a towing chart of a figure. 11 …… Selector, 12,13,14 …… Memory element, 31,32,33 ……
Address calculator, 34, 35, 36 ... Selector, 37, 38, 39 ... Memory element, 40 ... First data converter, 41 ... Second data converter.

Claims (1)

[Claims] 1. n corresponding to the number of bits per pixel (n)
Each memory element, a random access address from the central processing unit, a division in the depth direction of the screen, and a split screen designating signal for designating the address of the split screen are input, and become the random access address of each memory element. n address calculators, n selectors for selecting the random access address and the display address and supplying them to the memory device, and data conversion at the time of random access from the central processing unit by the split screen designating signal. It comprises a first data converter for performing and a second data converter for performing data conversion of a memory element output at the time of display access, performs screen division in the depth direction by an exponential multiple of 2, and randomizes in each divided screen unit. An image memory device characterized by being accessible.