JPH0581914B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention provides a high-speed, multi-layered image memory.
The present invention relates to a reading and writing system, and particularly to an access device for an image memory having a multilayer structure, which has an arithmetic unit in each layer of the image memory and processes graphics and images at high speed.

[Background of the invention]

A conventional color image display control device will be explained with reference to FIGS. 1 and 2.

FIG. 1 shows image memories 407, 408, 409 consisting of N layers each having color information of N bits per pixel.
FIG. 4 is a block diagram showing a method in which a control device 401 such as a microprocessor accesses image memory units of each layer. The control device 401 controls one of the image memories by the address signal 402 of the image memory.
Specify word. A part of the address signal 402 is input to a data switch 406 and a memory control switch 405, and a memory control signal 403 from the control device 401 and a data line 404 are input to the N-layer image memory 407, 408, 4.
Connected to one of 09. One word data designated in this manner is read and written in accordance with the memory control signal 403 of the control device 401. Image memory 407, 40
The data of No. 8,409 is always read out by a display controller 410 and displayed on a display device 411 such as a CRT. In such a memory access method, in order to write one pixel, memory accesses must be performed N times, which is the number of layers of the image memory. However, if the number of bits constituting one word is W, then M pixels arranged horizontally can be accessed by memory N times.

FIG. 2 shows a block diagram of an image memory control circuit that accesses the image memory pixel by pixel.

An N-bit data line 404 outputting from the control device 401 connects each layer of the image memory to 412, 41.
3,414, one bit each. The address signal 402 corresponds to each layer 412, 4 of the image memory.
Specify one bit of 13,414 and write to that N-bit signal, that is, one pixel data, using the memory control signal 403, or
Perform reading. This method of accessing the image memory pixel by pixel is effective when drawing a straight line, but it is not suitable for raster unit processing such as painting. because,
When the image memories 412, 413, and 414 are normally read out to the display controller 410, a plurality of pixels are read out and displayed on the display device 411. Therefore, for one plane of the image memory, there is actually not one data line but multiple bits, and only one of these bits is used when accessing the image memory.
When memory access is performed in the raster direction, the same memory address is accessed multiple times, which is inefficient.

[Purpose of the invention]

An object of the present invention is to enable high-speed processing such as reading, changing, and writing image data consisting of a plurality of pixels, especially transferring image data within the image memory, to a multilayered image memory that retains color information, etc. The present invention provides an image memory access device.

[Summary of the invention]

The gist of the present invention is that an arithmetic unit is provided in each layer of the image memory, each layer processes image data in parallel, and the arithmetic unit is configured to at least process a transfer source composed of a plurality of pixels stored in the image memory. first and second image data holding means connected in series for holding image data; third image data holding means for holding destination image data in the image memory; A shift means for shifting the image data outputted from the third holding means together by an arbitrary number of bits, and at least an exclusive OR between the output of the shifting means and the image data held in the third holding means. and means for performing logical operations including.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 3, 4, and 5.

Figure 3 shows an image memory 1 that stores a binary image of 1024 x 1024 pixels with a read/write data width of 8 bits, and a video signal 1 that stores the contents of the image memory 1.
It consists of a parallel-to-serial converter 8 that converts
The configuration of, for example, 101, which is a single-layer image memory in the figure, is shown. The control signal bus 41 includes a read/write signal, and the read/write signal is connected to the read/write terminal of the memory element constituting the image memory 1.

FIG. 4 shows an example of the configuration of a color image display device for realizing the image memory access method of the present invention. Image memory 101 shown in FIG.
Image memory 102,...,1 having the same configuration as
0N and the arithmetic units 111, 112, . . . , 11N, each has an 8-bit wide local data bus 1
21, 122, . . . , 12N. Control device 5 and calculation devices 111, 112,..., 11N
An 8-bit data bus 2 and a control signal bus 41 connect between the two. The first bit of the data input/output signal 21 of the data bus 2 is sent to the first arithmetic unit 111, the second bit to the second arithmetic unit, and the eighth bit to the eighth arithmetic unit. It is connected. When N is 9 or more, the Nth bit data is connected to the (Nmod8)th bit arithmetic unit.

FIG. 5 is a diagram showing the configuration of the first arithmetic unit 111 in FIG. 4, and the second to Nth arithmetic units 112, . . . , 11N have the same configuration. The arithmetic unit 111 has a local data bus 1
A first register 202 that latches the 8-bit data on 21, a second register 203 that latches the contents of the first register 202, and these 16
A barrel shifter 204 that shifts bit data from 0 to 15 bits and outputs the lower 8 bits, and a third register 2 that latches the output of this barrel shifter 204 and the data on the local data bus 121.
08, and a mask selector 206 that selects the result of the logical operation and the contents of the third register 208 in bit units.
and a fourth register 207 that latches the output of the mask selector 206 and is connected to the local data bus 121;
It consists of a fifth bidirectional register 201 that interfaces with the data bus 2. The fifth bidirectional register 201 receives a 1-bit data input/output signal 2
The 8-bit “00000000” is created by the function of latching 1 and the 1-bit data “0” and “1”.
or “11111111” and controls sending it to the local data bus 121; and a function to latch 1 bit of the 8-bit data on the local data bus 121.
It consists of a function to control the sending of the 1-bit data to the data input/output signal 21, and this can be easily configured using two D-type flip-flops, one 8-to-1 selector, and nine 3-stator buffers. can do. By the way, control signal bus 4
1 is the read/write signal 1 of the image memory 1 mentioned above.
A 1-bit signal that takes in 1-bit data of the data input/output signal 21 to the fifth bidirectional register 201, a 1-bit signal that expands the taken data and controls sending it to the local data bus 121, and The first signal consists of 3-bit data that determines which 1 bit of the 8-bit data is selected, the selected 1 bit, and a 1-bit signal that controls sending of the 1-bit data to the data input/output signal 21. Five bidirectional registers 201, a total of seven
A bit control signal 213, a latch signal 210 of the first register, a latch signal 211 of the second register, a 4-bit control signal 212 that controls the number of shifts of the barrel shifter 204, and a function (TTL) of the arithmetic unit 205. I C
A 4-bit control signal 214 that determines the logical operation mode of 74LS181) and a mask selector 206
An 8-bit control signal 215 that controls the selection of each input bit by bit, a latch signal 217 of the third register 208, a latch signal 1 bit of the fourth register 207, and the captured data. The control signal 216 for the fourth register 207 is composed of a 1-bit signal for controlling transmission to the local data bus 121 and has a total of 2 bits. These control signal buses 4
1, the data in the fifth bidirectional register 201 of the control signal 213 is transferred to the local data bus 1.
21, a signal to select 1 bit from 8 bits on the local data bus 121, a signal to take that signal into the fifth bidirectional register 201, and a latch signal 210, 21.
1, 217 and control signals 212, 214, 21
5, 216 are each arithmetic unit 111, 112,...,
11N in common. Also, a signal that takes in the data input/output signal 21 of the control signal 213 from the control signal bus 41 into the fifth bidirectional register 201 and a signal that sends out the contents of the fifth bidirectional register 201 to the data input/output signal 21. When the number of image memories N is 8 or less, the control signals are the signals for each arithmetic unit 111, 112,..., like other control lines.
11N in common. If N exceeds 8, then for every 8 these two signals are (N-1/8+
Divide into the largest integer not exceeding 1. That is, the control device 5 is the arithmetic device 111, 112,
...When accessing the fifth bidirectional register of 11N, since data bus 2 is 8 bits,
These control signals are divided to access five fifth bidirectional register units. For the sake of simplicity, the following description will be made assuming that N is 8 or less.

Now, in FIG. 4, the image memories 101, 102,
..., 10N, video signals 151, 152,
..., 15N is read out and converted into a color video signal 14 by the color conversion circuit 13, and the color
The operation for displaying a color image on the CRT6 is as follows.

First, serial data 15 from the image memory
1,152,...,15N is the CRT control device 7
(For details, refer to the HD46505 section in the Hitachi Microcomputer System Device Data Book.)
The display address 71 from the image memory is given to the image memory via the selector 9 as the address signal 91 of the image memory, and the read image data of each screen memory is converted into serial data by the parallel-serial converter 8. It will be done. The obtained N-bit data is a color code for one pixel, and is input to the color conversion circuit 13.
It is converted into an RGB video signal 14. This video signal 14 and the periodic signal 72 output from the CRT control device 7 are sent to the color CRT 6, and a color image is displayed on the CRT.

Below, the control device 5 includes arithmetic devices 111, 11
2,..., 11N, the screen memory 101,1
A method of accessing the image memory 1 in 02, . . . , 10N will be described.

First, in order to bring information for one pixel consisting of N bits from an image memory to the data bus 2, the control device 5 sends the address of the image memory containing the pixel to be read to the address bus 3. The address selection signal 42 is set on the address bus 3 side. Next, a 3-bit signal for selecting 1 bit from the 8-bit data of the control signal 213 is used.
The pixel to be read out is set as the number of the eight read pixels, and a latch signal for taking in the data from the local data bus 121 of the control signal 213 is provided. At the same time, by sending the control signal 213 to the data input/output signal 21,
The target pixel information taken into the fifth bidirectional register 201 is sent to the data bus 2.

Next, in order to write N-bit pixel information to a certain point on the image memory, the control device 5 first sends out the pixel information to be written onto the data bus 2, and uses the control signal 213 to It is taken into the bidirectional register 201 of. The captured 1-bit data is expanded to 8-bit data and sent to the same control signal 2.
13 to the local data bus 121, and is taken into the first register 202 by the control signal 210. Then, the 4-bit control signal 212 of the barrel shifter is set to a shift number of 0 so that one input of the arithmetic unit 205 has the same data as the first register 202. On the other hand, the control circuit 5 gives the address of the image memory 1 containing the target writing point to the address bus 3, sets the address selection signal 42 to the address bus 3 side, and sends the data of the image memory to the local data bus 121. At the point in time, the data is taken into the third register 208 by the latch signal 217. At this time, the output of the fifth bidirectional register 201 to the local data bus,
In order to avoid conflict with the output of the image memory, the control device 5 controls the address selection signal 42 and the control signal 213.
control. In addition, the control device 5 gives a control signal 214 indicating what kind of logic is used to calculate the pixel information to be written and the pixel information of the point to be written currently in the image memory, so that the point to be written is The position of the 8 pixels corresponding to the address of the image memory containing the image is given to the control signal 215 of the mask selector 206 as 8-bit information. For example, if the second pixel from the left is the pixel to be written, the control signal 215 will be a binary number "01000000". Now, after the output of the mask selector 206 is determined, the control signal 216 causes the output of the mask selector 206 to be taken into the fourth register, and the taken data is sent to the local data bus 121. The control device 5 has a control signal bus 41
By writing a read/write signal to the write point, the logical operation result of the given pixel information and the pixel information that existed before writing is written to the point to be written. By appropriately changing the control signal 215 in this process, it is also possible to write the same image information to up to eight pixels.

Next, a method will be described in which eight arbitrary pixels arranged horizontally on the image memory are transferred by performing a logical operation on each eight pixels specified for one address in the image memory. First, the eight pixels to be transferred are specified by two addresses spanning two words, so the address with one word on the left side on the screen is called the source address. On the other hand, the addresses of the 8 pixels to which the data is transferred are called destination addresses.

The control device 5 first sends the source address to the address bus 3 and sets the address selection signal 42 on the address bus 3 side. When the data in the image memory corresponding to the source address is sent to the local data bus 121, the image data is taken into the first register 202 by the latch signal 210. At the same time, the control device 5 sends the source address plus 1 (on the right side on the screen) to the address bus 3.

When the data in the image memory at the source address plus 1 is sent to the local data bus 121, the latch signal 211 and the latch signal 21 are activated.
0 causes the contents of the first register 202 to be latched into the second register 203 and at the same time the data on the local data bus 121 is taken into the first register 202. Next, the control device 5 sends a 4-bit binary value to the control signal 212 indicating the position of the leftmost pixel of the 8 pixels to be transferred from the left of the 8 pixels of the source address. Give as a signal. Furthermore, the control signal 214 is set to determine what kind of logical operation is to be performed. Next, the control device 5 gives a destination address to the address bus 3, and when the data of the image memory is sent to the local data bus 121, the control device 5 sends a control signal 21.
7 to the third register 208. All control signals 215 are set to "1", all outputs of the arithmetic unit 205 are set to be outputs of the mask selector 206, and the output of the barrel shifter 204 and the logical operation result of the third register 208 are stored in the fourth register. After being determined as the input of 207, the control signal 2
16, the output of the mask selector is taken into the fourth register and simultaneously sent to the local data bus. By setting the read/write signal of the control signal bus 41 to write, an image of any consecutive 8 pixels out of the 16 consecutive pixels at the source address and the source address plus 1 on the image memory is generated. Before the data is transferred, a logical operation is performed on the image data of 8 pixels located at the destination address, and the result is written to the destination address. With this process,
By providing mask information to the control signal 215 of the mask selector 206, a masked image can be transferred.

As described above, according to this embodiment, each screen memory is provided with an arithmetic unit, and by accessing the single image memory 1 in parallel, the screen memory can be reduced compared to the conventional system shown in FIG. Processing can be performed several times faster, and is eight times faster than the method shown in FIG. In addition, there are first and second registers that hold the pixel information of the transfer destination in the arithmetic unit, a barrel shifter that shifts them by an arbitrary number of bits, a third register that holds the pixel information of the transfer destination, and a barrel shifter that holds the pixel information of the transfer destination. It has an arithmetic unit that performs a logical operation between the output and a third register, a mask selector that can select the output of the arithmetic unit and the third register in bit units, and a fourth register that holds pixel information to be transferred. This significantly speeds up the transfer of images in the image memory.

〔Effect of the invention〕

According to the present invention, it is possible to speed up the process of aligning the transfer source image data in one layer of image memory with the memory boundary of the transfer destination, which is the write destination, and furthermore, it is possible to speed up the process of aligning the transfer source image data in the image memory with the write destination memory boundary, and furthermore, it is possible to speed up the process of aligning the transfer source image data in the image memory with the write destination memory boundary. As a result, processing such as image data transfer to the entire image memory can be speeded up.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a display control device that accesses each layer of image memory in units of words.
FIG. 3 is a block diagram of a display control device that accesses an image memory in units of one pixel. FIG. 3 is a block diagram of one screen memory of a color image display control device according to an embodiment of the present invention. FIG. FIG. 5 is a block diagram of a color image display control device according to an embodiment of the present invention. 1...Screen memory, 2...Data bus, 3...
Address bus, 41... Control signal bus, 42...
Address selection signal, 5...Control device, 6...Color CRT, 7...CRT control circuit, 71...Display address, 72...Synchronization signal, 8...Parallel-serial converter, 9...Selector, 101, 102,...,10
N...1st to Nth screen memory, 111,
112,..., 11N... 1st to Nth arithmetic units, 13... Color conversion circuit, 204... Barrel shifter, 205... Arithmetic unit, 206... Selector, 207, 208, 210, 211... Register , 401...Memory control device, 402...Address signal, 403...Memory control signal,
404...Data line, 407, 408, 40
9,412,413,414...image memory, 4
10... Dispress controller, 411...
CRT.

Claims (1)

[Scope of Claims] 1: an image memory having a multilayer structure for storing color image data; means for sequentially reading out this image memory in the raster direction and sending it to a display device; In a control device that controls reading and writing of a memory, at least transfer source image data composed of a plurality of pixels stored in the image memory is held between the image memory and the control device. first and second image data holding means connected in series; third image data holding means for holding destination image data in the image memory; and output from the first and second holding means. Shifting means for shifting the image data by an arbitrary number of bits;
An arithmetic device comprising means for performing a logical operation including at least an exclusive OR between the output of the shifting means and the image data held in the third holding means is provided for each layer constituting the image memory. An image memory access device characterized in that: 2. In the image memory access device according to claim 1, of the first and second holding means connected in series, the second image data holding means stores the first image data. An image memory access device characterized in that when new image data is held in the holding means, image data that has been held in the first image data holding means is fetched and held.