JPH0810426B2 - Bitmap display device and memory device thereof - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a bitmap display device (also referred to as a bitmap display device) for displaying characters and graphics on a screen with a pixel (dot) structure, and the display device. Memory device for a computer.

[Conventional technology]

Block diagram of a conventional bitmap display device (FIG. 7)
The configuration will be described with reference to FIG. 100 is the display screen and 1
It is a frame buffer memory corresponding to the pair 1. 71
Is a CPU that creates data on the display screen, accesses the frame buffer memory 100, and reads / writes. Bitmap display devices rewrite at a time in units that are continuous in the horizontal direction on the display screen at a time in order to speed up screen creation.Therefore, in general, when the frame buffer memory starts horizontally from the first address of a word boundary on the display screen. As long as n bits can be simultaneously accessed at one time. 72 is the position of any dot in the display screen sent from the CPU, and corresponds to the dot address that indicates the start address of the word that is continuous in the horizontal direction on the display screen.
It is a shifter that shifts CPU data.

In such a conventional type display device, regarding a 16-bit system, 1) When the data position designated by the CPU does not cross a word boundary, that is, the shaded portion in FIG. 8 is the data. In this case, the lower 4 bits of the horizontal dot address sent from the CPU are all 0, and at this time the shifter 2 does not operate, the data is not shifted, and the lower 4 bits designated by the CPU Write the data as it is to the memory of the address except.

2) If the data position specified by the CPU crosses a word boundary, that is, if the shaded area in FIG. 9 is data, the lower 4 bits of the dot address are not all 0s. When the lower 4 bits indicate 3, a) When the CPU starts the read operation of the address D, the data in the frame buffer memory is taken into the shifter,
The shifter rotationally shifts the data by the difference between the positions of the word boundary and the actual data boundary. In the example of FIG. 9, the shifter is rotated and shifted by 3 bits to the lower side in the shifter, and the shifted data is taken into the CPU.

b) The CPU masks the upper 3 bits of the data thus read and sets all the remaining bits to 0.

c) The CPU masks the lower 13 bits of the 16-bit write data and sets all the remaining bits to 0.

d) The result of b) and the result of c) are ORed.

e) The CPU puts the result of d), that is, the replaced data in the shift, and the data that is rotationally shifted by 3 bits to the upper side in the shifter by the address D of the frame buffer memory.
Write to.

f) The CPU adds 1 to bit 5 of the address and reads the address D + 1. When the CPU starts the read operation of the address D + 1, the data in the frame buffer memory is taken in by the shifter, rotationally shifted to the lower side by 3 bits in the shifter, and this data is taken in by the CPU.

g) The CPU masks the lower 13 bits of the data read in f) and sets all the remaining bits to 0.

h) The CPU masks the upper 3 bits of the 16-bit write data and sets all the remaining bits to 0.

i) OR the result of g) with the result of h).

j) The CPU puts the result of i), that is, the replaced data into the shifter, and the data that has been rotationally shifted by 3 bits to the upper side in the shifter is the address D of the frame buffer memory.
Write to +1.

Because of this procedure, when the data position specified by the CPU crosses a word boundary,
In the conventional device, the n bits can be simultaneously accessed at one time only when starting from the first address of the word boundary in the horizontal direction on the display screen. Therefore, the above a), e), f), and j) are performed four times. of
Access to the CPU is required, and the mask data creation stage for performing b), c), g), h) and b), c), d),
g), h), i) mask operation, a), b) mask, c)
The memory area for storing the mask of b), the result of c), the mask of f) and g), the mask of h), the result of g), and the result of h) is required.

As a technique for solving this kind of technical problem that occurs when a data position crosses a word boundary, Japanese Patent Laid-Open No. 62-10368.
There is Bitmap memory device No. 6 (May 14, 1987). The gist of this technology is as follows: "1 word consists of 2 ⁿ RAMs of 1 bit, 1 word is 2 ⁿ bits of bitmap memory, and any 1 bit in this bitmap memory is specified. According to the number m indicated by the lower-order n bits of the bit address, a value obtained by adding +1 to the remaining bits excluding the lower-order n bits of the above-mentioned bit address is determined as an address for m RAMs from the head among the 2 ⁿ RAMs, RAM address designating means for directly designating the remaining bits excluding the lower n bits of the bit address for the remaining RAM, and 2 ^n- bit read data read from the bit map memory in the read mode. , In write mode, write the 2 ^n- bit write data to the bit map memory to the bit indicated by the lower n bits of the bit address. The number m is a bit map memory device "which is characterized by comprising a shift circuit for only rotation shift technology as far as disclosed in the specification, 2 ⁿ
In order to obtain a value obtained by adding +1 to all the predetermined bits as an address for m RAMs from the head of the RAMs, the number of bits of the frame buffer memory, that is, only 16 adder circuits are provided in the embodiment. Requires RAM addressing section.

[Problems to be Solved by the Invention]

In the conventional bitmap display device, as described in detail in the previous section, when the position of the data to be displayed straddles a word boundary, access to the CPU is required four times, creating masked data. Four stages and six mask operations were required, and a memory area for temporarily storing the processing result was required during the series of processes. Therefore, the load on the CPU is large, the processing time is naturally delayed, and the memory storage capacity must be increased.

As a technique for solving this problem, the above Japanese Patent Publication No. 62-10368.
Although the technology of No. 6 is available, it has a drawback that the adder must be provided with the number of bits (for example, 16) of the frame buffer memory.

The present invention has been devised in order to solve such a problem, and does not consider a word boundary of a frame buffer memory composed of a plurality of memory elements (memory chips), and can arbitrarily change the frame buffer memory. It is an object of the present invention to realize a memory device capable of directly accessing the position of and to improve a bitmap display device by using the memory device.

Furthermore, by controlling the selection of memory elements (chip select) and the selection of addresses, it is possible to read / write the display data at a predetermined position without the mask operation by one memory access, and to store the data in the memory. It is an object of the present invention to realize a bitmap display device and its storage device which have a small capacity, reduce the load on the CPU, and can perform high-speed processing.

[Means for solving the problem]

The means adopted by the present invention firstly prepares two frame buffer memories each composed of a memory element group (a plurality of memory chips) and connects them in parallel to a common bus.

Secondly, the concept of even word address and odd word address is introduced, and one of the two frame buffer memories is divided into an even frame which is accessed by an even word frame and another one which is accessed by an odd word address. Furthermore, a selecting means is used which can select and read / write the memory elements belonging to a predetermined number of continuous dot addresses from the memory element groups of the two frame buffer memories.

[Action]

In the present invention, the number of bits of data k (eg 16, 32)
For the bus means having data lines of 1st, a first frame buffer memory composed of k memory device groups connected to the respective data lines, and a second frame buffer memory also composed of k memory device groups. And an even word frame memory (which corresponds to the first frame buffer memory) that is accessed by an even word address and an odd word frame memory (the second frame buffer memory that is accessed by an odd word address). Apply) is used. Memory element selecting means (chip select control means) capable of selecting a memory element group corresponding to continuous k dot addresses from the memory constituted by these k + k memory element groups
Place the rotation shifter and adder, and put them in CP
By controlling with U, the processing of data that crosses word boundaries was improved.

〔Example〕

A first embodiment of the overall configuration of the bitmap display device of the present invention
Shown in the figure. Although this figure was created with a 16-bit system, it can be expanded in the same way with a 32-bit system. In this case, the bit allocation method is indicated by the numbers in parentheses.

1 creates screen data, writes the data in the frame buffer memory, and displays a bitmap image on the display device based on the data. It is a CPU to realize the function. The address sent from this CPU is, for example, 21
Of the 21-bit address, the lower 11 bits are in the horizontal (X) direction on the screen and the upper 10 bits are vertical (Y).
Assign it to the direction and use it.

Reference numeral 2 is a shifter for rotating and shifting the data from the CPU 1 in accordance with the lower 4 bits of the address sent from the CPU 1.

Reference numeral 3 denotes an adder for adding the value (1 or 0) indicated by bit 4 to the value indicated by 16 bits excluding the lower 5 bits of the address 21 bits transmitted from the CPU 1. Where bit 4
Indicates the fifth bit from the lower order.

4 is a first frame composed of a group of memory elements (memory chips) capable of storing 16 bits for accumulating a display screen whose address is a value obtained by adding 1 or 0 by the adder 3. It is a buffer memory. 16 memory devices are connected so that each corresponds to one bit of data, and a memory group (block) with a data width of 16 bits
Composed of.

5 is a second frame buffer memory composed of a memory device capable of storing 16 bits for storing a display screen, with an address obtained by removing the lower 5 bits of the address transmitted from the CPU 1. Is. The configuration is the same as that of the first frame buffer memory 4, and the two memories 4 and 5 have a data line connected to each bus for each bit. That is, a wired OR connection is made.

Reference numeral 6 is a control for outputting a memory element selection signal (chip select signal) for selecting each memory element forming the first or second frame buffer memory according to the value of the lower 5 bits of the address transmitted from the CPU 1. Device (chip select controller). The memory element selection signal outputs a binary signal of 1 and 0 shown in the right column of the figure corresponding to the value of the lower 5 bits of the address (left vertical column of FIG. 2). The binary signal 1 selects the memory chip, and the binary signal 0 does not select the memory chip. There are 32 memory element selection signals in this embodiment, which are ₁ , _2, ...
…, ₃₂ .

Details of the first and second frame buffer memories shown in FIG. 1 are shown in FIG. In the figure, M1, M2 ... M16; and M17, M18 ... M32 are memory elements (memory chips), which constitute first and second frame buffer memories. Address A is the address added by the adder (3 in FIG. 1) and is the address line of the first frame buffer memory. Address B is an address line of the second frame buffer memory. In addition, the memory element selection signal _{1
16 to 17} ; ₁₇ to ₃₂ are outputs CS from the chip select controller 6, and 16-bit data are outputs from the shifter 2 in FIG. For example, in hexadecimal 8, (08
If the input of (H) (star column in FIG. 2) is added to the input of the chip select controller 6, outputs ₁ to ₁₆ ; ₁₇ to _{32 in} the right horizontal column of FIG. 2 are output. Then, the memory device group becomes M9 of the first frame buffer memory.
.About.M16 and M17 to M24 of the second frame buffer memory are selected, and writing (or reading) is performed in that portion.

Next, writing to and reading from the first and second frame buffer memories will be described.

First, the example of FIG. 4 is a case where data can be stored in the respective memory element groups forming the first or second frame buffer memory without crossing word boundaries. The top row shows 16-bit data a _{0 to} a ₁₅ processed by the CPU 1. The second row shows the data after being shifted by the shifter 2. The number of shifts is zero because the value a represented by the lower n = 4 bits of the dot address is zero. The data after this shift appears on the data lines of the first and second frame buffer memories, but the memory element selection signal from the chip select controller 6 indicates that the lower n + 1 = 5 bits of the address are all zero, Since it is a signal corresponding to 00H in FIG. 2, the memory element groups M1 to M16 are selected, written in the memory element group of the first frame buffer memory, and read at the time of display. This is shown in FIGS. 4 (b) and 4 (c). This example is the same as in FIG.

Next, proceed to FIG. This example is the same as in FIG. Here, the lower n + 1 = 5 bits are 01H to 0FH in hexadecimal.
It can take the values (1 to 15 in decimal). For example, if the lower 5 bits indicate 03H (3 in decimal), the shifter 2 rotationally shifts the data of the CPU 1 three times in the upper direction, and transfers it to the first and second frame buffer memories. M4 to M16 by the chip select controller 6;
Memory elements M17 to M19 are selected. When writing is performed in this state, writing is not performed in the memory element group for which the selection signal is 0.

In this way, by using the value indicated by the lower n or n + 1 bits for the dot address and preparing two groups of frame buffer memories, it is possible to realize an operation in which the word boundary in 16 bits need not be conscious.

Next, by adopting the first and second frame buffer memories, there is a word boundary in 32 bits. As a method for solving this word boundary problem, the first frame buffer memory is used. An adder 3 (Fig. 1) is placed at the address input of the. This adder adds the high order mn-1 bits of the dot address (where m is the number of bits of the dot address; n is the number of bits of the word data 2 ⁿ ) to the value b represented by the high order of the dot address. To calculate the word address by adding the value of the mnth bit. X (horizontal) from the position of X = 0, Y = 0 on the display screen
The display data stored in the first frame buffer memory when the addresses are sequentially assigned in the unit of word in the direction correspond to the even addresses of i = 0, i = 2, .. I will decide. Therefore, the first frame buffer memory is a memory element group corresponding to even word addresses.

The 32-bit word boundary is the lower n + 1 of the dot address
= Appears when 5 bits change from 11H to 1FH in hexadecimal. For example, the operation when the lower 5 bits become 13H will be described with reference to FIG. 6. As in the case of 03H above, the shifter 2 rotationally shifts the data of the CPU 1 three times in the upper direction and rotates the first and the third. 2 Pass to the frame buffer memory. Memory element groups M20 to M32; M1 to M3 are selected by the chip selection signal and data is written. At this time, bit 4 of the address becomes "1". The value of this bit 4 is added to the first frame buffer by the adder, and the data is written in the first frame buffer memory where 1 is added to the address of the second frame buffer memory. .

This is why the second frame buffer memory is called a frame memory having an odd word address, while the first frame buffer memory is called a frame memory having an even word address.

The above description is about a system using a 16-bit CPU, but it is obvious that it can be applied to a 32-bit CPU almost as it is. In this case, the description in FIG. 1 is replaced with the numbers in parentheses. Also, although it can be applied to other numbers of bits, the following is a typical configuration.

Generally, an m-bit dot address indicating the screen display position and a 2 ^n- bit indicating the drawing content. Consider a bitmap display position to be displayed based on word data. Shifter 2
Serves as a shifter that rotationally shifts the word data by the number of times a of the value represented by the lower n bits of the dot address, and outputs the shifted word data. The adder 3 outputs a value b represented by the upper m-n-1 bits of the dot address.
In addition, the adder calculates the even word address by adding the value of the mnth bit from the higher order of the dot address.
Memory device selection signals to output the chip select controller 6 is composed of 2 ^{n + 1} present, the C + 1 -th to C + 2 ^n-th when the value C representing the lower n + 1-bit dot address (i) C2 ⁿ -1 Are all 1 and all others are 0. (b) When C2 ⁿ , C-2 ⁿ + 1 to C
The memory element selection means outputs a memory element selection signal in which all the values up to the first are 0 and the others are all 1. 2 ⁿ from the first low-order n + 1 bit of the dot address by the first frame buffer memory 4 has an access function 1-bit units to retain the display contents of the screen position of the 2 ⁿ 1 respectively until the 2 ⁿ It consists number of memory element group, wherein the memory device selection signal from the first run to 2 ⁿ -th received, the said even word address of the memory element group in which the memory device selection signal is 1, are shifted word It becomes an even-word memory element group for storing data. The second frame buffer memory 5 has a 1-bit unit access function, and the lower n + 1 bits of the dot address start from 2 ⁿ +1.
The 2 ⁿ +1 for holding 2 ^{n + 1} of the display contents of the screen position, respectively
Is composed from the 2 ^{n + 1} to the 2 ⁿ memory element group from receipt of the memory device selection signal from the 2 ⁿ +1 -th to 2 ^{n + 1} -th, the memory device selection signal is 1 memory An odd-numbered word memory element group for storing the shifted word data is provided at an address represented by the upper m−n−1 bits of the dot address of the element group.

〔The invention's effect〕

As described above, in the present invention, k = 16 or k = 32
For a bus means including a number of data lines corresponding to a standard number k of bits, a first frame buffer memory composed of a group of k memory elements connected to each data line, and the same k A second frame buffer memory composed of memory device groups is prepared, and the concept of an even word frame memory corresponding to an even word address and an odd word frame memory corresponding to an odd word address is introduced, The buffer memory was divided, and memory elements belonging to consecutive k dot addresses were selected from the buffer memory to write / read the memory. Therefore, it was necessary when accessing data that crossed word boundaries. , Several times masking, several times CP
Eliminates complicated processing associated with access to U, processing speed,
The memory area can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of a device of the present invention, FIG. 2 is a diagram showing an input / output relation of a memory element (chip) selecting means (controller) used in the device of the present invention, and FIG. FIG. 4 is a diagram showing a configuration of an embodiment of a memory device of the present invention, FIGS. 4 to 6 are operation explanatory diagrams of the device of the present invention, FIG. 7 is a diagram showing a configuration of a conventional technique, FIG. The figure is a diagram for explaining the operation of the prior art, and is a diagram showing the relationship between the data in the frame buffer memory and each dot on the display screen. In the figure, 1: CPU, 2: shifter, 3: adder, 4: first frame buffer memory (even frame memory), 5: second frame buffer memory (odd frame memory), 6: memory element selection means (Chip select controller), 100: Conventional frame buffer memory, AD: Address, DAT:
Data, DT: signal from shifter, M and M1 to M32 indicate a memory element (memory chip) and P: display screen, respectively.

Claims (3)

[Claims] 1. A memory device for a display device for displaying drawing data at an arbitrary dot address, wherein bus means including at least k data lines and k connected to each of the k data lines of the bus means. First of
Memory device group, a k second memory device group connected to each of the k data lines of the bus means, and a predetermined continuous k among the (k + k) memory device groups.
A memory device for a display device, comprising: a memory element selecting means for selecting a memory element belonging to each dot address. 2. A bit map display device for receiving and displaying an m-bit dot address indicating a display position of a display screen and a 2 ^n- bit word data indicating a display content, by a numerical value of lower n bits of the bit address. A shifter (2) that shifts the received screen data a predetermined number of times, and first and second frame buffer memories (4, 4) each of which is composed of 2 ⁿ memory element groups and stores the screen data.
5) and the value excluding the lower (n + 1) bits of the bit address,
From the adder (3) that adds the value indicated by the bit n to calculate the address of the first frame buffer memory and the 2 × 2 ^n- bit memory element group of the first and second frame buffer memories, And a memory element selection means (6) for generating a signal for selecting the 2 ^n- bit memory element group based on the value indicated by the lower (n + 1) bits of the bit address. 3. A bit map display device for displaying on the basis of an m-bit dot address indicating a display position on a screen and 2 ^n- bit word data indicating a drawing content, wherein the lower n bits of the dot address indicate the word data. A shifter (2) that rotationally shifts by the number of times a represented value and outputs the shifted word data, and a value b represented by the upper m-n-1 bits of the dot address, from the upper mth of the dot address. An adder (3) that adds an n-bit value to calculate an even word address
And a memory element selection means (6) which is composed of 2 ^{n + 1} lines and which outputs a memory element selection signal whose value C represented by the lower order n + 1 bits of the dot address satisfies the following condition (a) or (b): It is configured to display contents of the screen position of the lower n + 1 bit from 1 2 ⁿ of the dot address has an access function 1-bit units from the 2 ⁿ memory devices from the first holding respectively until the 2 ⁿ , said memory element selection signals from the first run to 2 ⁿ -th received, the in even word address, even word memory element group for storing said shifted word data in the memory device the memory device selection signal becomes 1 (4) and, 1 of the dot address has an access function bitwise lower n + 1 bit is displayed on the screen position of the 2 ⁿ +1 2 ^{n + 1} from the 2 ⁿ +1 for holding each of the first 2 ^{n + 1} 2 ⁿ in
It consists number of memory elements, 2 from the 2 ⁿ +1 -th ^{n + 1}
An odd number that receives the memory element selection signals up to the first and stores the shifted word data at the address represented by the upper m−n−1 bits of the dot address of the memory element group in which the memory element selection signal is 1. A bit map display device comprising a word memory device group (5). (A) In the case of C2 ⁿ -1, all from C + 1 to C + 2 ⁿ are 1 and all others are 0. (B) In the case of C2 ⁿ , all of C−2 ⁿ + 1st line to Cth line are 0 and all others are 1.