JPH0347510B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a highly practical image storage device that can efficiently write and read display image information partially.

[Technical background of the invention and its problems]

Recently, there has been an increasing demand for display devices that can display characters, figures, images, etc. in arbitrary formats. This type of device is generally equipped with a bit map memory of about 1000 x 1000 dots for storing pixel data of display images, and a font memory that stores about 4000 character fonts of 24 x 24 dots per character. The read character font is written in a desired position of a bitmap memory (image memory) corresponding to a display image to form an image, which is then displayed. Conventionally, in order to improve the processing speed of these memories, reading and writing processes are generally performed using 8-bit to 32-bit pixel data as a processing unit of one word. In other words, 2
For value images, 8 to 32 pixels are handled as one word unit.

However, if you want to display a character image consisting of 24 x 24 dots at an arbitrary position on the screen, one word of data read from the font memory is written across one word on the bitmap memory, and then It becomes necessary to read this out.
In other words, a discrepancy occurs between the image data and the data storage unit of the memory. Therefore, conventionally, data to be written to one word in memory is selectively extracted using a mask and written to that word, and then
Processing is performed in which data to be written in the other word is similarly extracted using a mask and written in that word. However, performing the writing process twice in this way leads to a decrease in processing speed, and furthermore, there is a problem that the control thereof is complicated and complicated.

[Purpose of the invention]

The present invention has been made in consideration of these circumstances, and its purpose is to create an image in which display image information handled in units of a predetermined number of pixels is divided into blocks for each of the predetermined number of pixels and information is stored. It is an object of the present invention to provide a highly practical image storage device that can efficiently write to and read from any location in a memory.

[Summary of the invention]

The present invention uses simultaneously accessible first and second image memories that alternately store display images in blocks of a predetermined number of pixels, and the addresses to be simultaneously accessed in these image memories are set in units of the predetermined number of pixels. The pixel data group is controlled according to the position where the pixel data group is to be displayed, and the pixel data group to be written or the read pixel data group is rotated according to the position where the pixel data group is to be displayed. be.

〔Effect of the invention〕

Therefore, according to the present invention, image information can be easily given to any position of a displayed image, and externally, data of a predetermined number of pixels can be written and read as one unit, regardless of how internal data is handled. It can be done. In addition, control is simple, and great practical effects can be achieved, such as high-speed processing with only one access.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic configuration diagram showing the main parts of the embodiment device. It is assumed here that a binary image of 1024 dots in the horizontal direction and 1024 dots in the vertical direction is stored, and the pixel data is treated as 8 pixels (8 bits) as one unit (1 word). 1st
and second image memory (storage units A, B) 1, 2
have a storage capacity of 64k words each, and are configured to be accessed simultaneously in response to an address signal from a host controller (not shown).
However, for the first image memory 1, the calculation unit 3
The access address is controlled as described below. However, the first and second image memories 1 and 2 can also be configured by using large-capacity memories that can simultaneously access different addresses in two areas, and dividing the storage areas into two. As shown in FIG. 2, these first and second image memories 1 and 2 have addresses corresponding to each block formed by dividing the display screen into blocks of 8 pixels each. , the divided blocks are alternately associated with the first and second image memories 1 and 2. In other words, in each pixel line of the display screen, the 0th, 2nd, 4th, etc. even-numbered blocks correspond to each address in the first image memory 1 in order, and the 1st, The third, fifth, etc. odd-numbered blocks correspond to each address of the second image memory 2 in order. Therefore, the 0th block and the 1st block correspond to the same address position in the first and second image memories 1 and 2, and the 2nd block and the 3rd block correspond to the next same address position. We are beginning to respond. The first and second image memories 1 and 2, in which display screens and addresses are made to correspond in this way, constitute a so-called one image memory.

Thus, one unit of write pixel data group for these first and second image memories 1 and 2 is transferred from the input information rotation section 4 to the mask processing section 5.
via the first and second image memories 1, 2
They are now being given to each of them. Furthermore, pixel data groups read out by simultaneous access of the first and second image memories 1 and 2 are outputted via the output information rotation unit 6. In addition, 7 in the figure is a control unit, which controls the access address in the arithmetic unit 3 and the rotation process in the rotation units 4 and 6, according to the position information of one unit of pixel data group to be accessed. Mask processing in the mask processing section 5 is controlled.

Now, in the device configured in this way, 8
If a group of pixel data to be written or read in pixels as a unit matches each block position of the first and second image memories 1 and 2, just specify the corresponding address. It can be processed in exactly the same way as before. However, if the display position is arbitrarily determined, it becomes necessary to write one unit of pixel data across two blocks. In this case, depending on the position, as shown in FIG.
There are two cases; As mentioned above, these block addresses are distributed alternately from the first image memory 1 side, so in the case of the above condition P, the block addresses are allocated to the first and second image memories 1 and 2. If the same address is specified, each corresponding block can be accessed. On the other hand, in the case of the above condition Q, the address of the corresponding block in the first image memory 1 increases by "1" compared to the address of the corresponding block in the second image memory 2. The control unit 7 sets the conditions P,
As a result, when the above condition becomes Q, the arithmetic unit 3 increments (+1) the address data given by the host controller and then accesses the first image memory 1. ing. In the case of condition P, the first image memory 1 is directly accessed using the given address data. Also, the second image memory 2
is accessed by the given address data regardless of the above conditions P and Q. As a result, the addresses corresponding to the positions of the images to be processed are accessed simultaneously.

Now, when a pixel data group of 8 pixels as a unit is inputted with the position specified by the above condition P, the rotation unit 4 moves it to the first pixel position as shown schematically in FIG. 3. The input pixel data group is rotated accordingly. In this case, the rotation process is performed within a range of 8 dots, and pixel alignment is thereby performed. Thereafter, the rotated data group is subjected to mask processing in which unnecessary bit position data is removed by a mask section 5. After that, the pixel data group corresponding to a total of 16 pixels for 2 units that have been masked is divided into the top 8
The first and second data are divided into a pixel data group and a lower 8 pixel data group and accessed as described above.
The images will be written to the image memories 1 and 2, respectively.

Furthermore, in reading out the pixel data group written in this way, data for a total of 16 pixels read out from the first and second image memories 1 and 2 accessed at the same address are sent to the rotating section 6. This is performed by supplying data and performing a rotation process that is opposite to the rotation process during the write process described above, and then outputting data over eight pixels from the reference bit position.

On the other hand, when a pixel data group with 8 pixels as one unit satisfies the condition Q, as shown in FIG.
Rotation is performed over 16 bits, that is, over 2 blocks. In other words, the block of the first image memory 1 that is accessed in this case is the next address position that is greater by "1" than the block address of the second image memory 1. Therefore, it is necessary to arrange the data on the lower pixel side divided at the boundary of the block from the top of the upper pixel side supplied to the first image memory 1. Further, the data on the pixel side needs to be located on the lower side of the block in the second image memory 2. Therefore, as described above, the input pixel data group is rotated according to the pixel position as shown in FIG.
2 access blocks respectively. Also,
When reading the data written in this manner, it is sufficient to carry out reverse rotation processing as shown in FIG. 5, and then select and output the bit position.

As described above, according to the present device, the first and second
Blocks in which the display screen is divided by a predetermined number of pixels are made to correspond to each other alternately in the image memory of the image memory, so that they can be accessed simultaneously, and the access address is controlled according to the position of the pixel to be processed. Since pixel alignment is performed by rotating the write pixel data or the read pixel data accordingly, it becomes possible to easily process display image information at any pixel position. Moreover, since such processing is performed internally within the device, data groups of 5 pixels per unit can be handled as they are externally without any modification. Furthermore, unlike conventional devices, the process can be performed with just one access process, making it easy to speed up the process. be given

Note that the present invention is not limited to the above-described embodiments. For example, the number of pixels serving as a processing unit is 8
The processing target is not limited to pixels, and multivalued images can also be processed. Furthermore, by configuring the masking process in the embodiment to be maskable with an arbitrary bit width, image processing with an arbitrary width is also possible. This makes it possible, for example, to change only the radical of a Kanji character image, which is highly effective. In short, the present invention can be implemented with various modifications without departing from the gist thereof.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram showing the main parts of an apparatus according to an embodiment of the present invention, FIG. 2 is a diagram showing the relationship between blocking of the display screen and one unit of pixel group to be processed, and FIGS. FIG. 5 is a diagram for explaining rotation processing of one unit of pixel data group. 1, 2... Image memory, 3... Arithmetic unit, 4...
Input information rotation unit, 5...Mask processing unit, 6
. . . Output information rotation section, 7 . . . Control section.

Claims (1)

[Scope of Claims] 1. Simultaneously accessible first and second image memories in which image information is sequentially divided into blocks by a predetermined number of pixels and stored alternately in block units; means for simultaneously accessing blocks of the first and second image memories containing pixels to be written or read; An image storage device comprising: a rotation circuit that aligns or rotates data groups read from the two blocks to form one unit. 2. The rotation circuit rotates one unit of write pixel data group, aligns the pixels, and performs mask processing to supply only the above pixel data group to the first and second image memories for writing. An image storage device according to claim 1. 3. When one unit of pixels to be written or read is based on a block in the first image memory, the access means simultaneously accesses the same block address in the first and second image memories, and accesses the same block address in the second image memory. When using the second
2. The image storage device according to claim 1, wherein a block address next to an access block address of the first image memory is simultaneously accessed as an access block of the first image memory.