JPH0727364B2 - Memory writing control circuit for character / graphics display - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a character / graphics display device using a bit map method, and more particularly to a bit map memory in which a predetermined word consisting of a plurality of bits is addressed as a unit. The present invention relates to a character / graphics display device capable of writing a pattern graphic at high speed.

[Background of the Invention]

The character / graphics display device using the bit map method has a feature that any character or graphic can be displayed at any position on the screen because both characters and graphics are displayed in units of pixels. In order to display characters on such a character / graphics display device, in general, the lighting of the pixels forming the character
A character generator (hereinafter abbreviated as CG) created by turning on / off the light is provided, and bit information read from the CG is transferred to the frame memory.

FIG. 3 (a) is an example of a pixel pattern when the character "A" is composed of vertical and horizontal 8 pixels, and FIG. 3 (b) is a bit representing the same character stored in the CG as shown in FIG. 3 (a). Information. (This is called a character font.) As shown in FIG. 3, the bit information normally stored in the CG corresponds to a horizontally divided pixel pattern representing a character. Therefore, the letter "A" shown in Fig. 3 (a).
To write to the frame memory, first enter 0001 from CG.
Read a character font of 1000 (B) (where B indicates that the radix is a binary number) and write it to the frame memory, then read a character font of 00100100 (B) and write it to the frame memory. , A series of processing is performed. At this time, a group of bit information as a unit of processing is called one word. Although the case where one word consists of 8 bits will be described below, it is clear that the same argument holds for other values.

The frame memory is composed of storage elements sufficient to store bit information indicating turning on / off of all pixels on the display screen, and reading / writing of these bit information is also performed in word units. For this reason, as shown in FIG. 4, when the position where the character is to be displayed is aligned with the boundary of the words forming the frame memory, the bit information read from the CG is simply written to the frame memory. Although it is possible to display characters with, if there is a mismatch, that is, if the pattern of the characters to be displayed spans multiple words that are horizontally adjacent to each other, one word to the left and one word to the right are individually Must be written to.

FIG. 5 and FIG. 6 show a writing procedure to the frame memory of the left side portion and the right side portion of the character when the character to be displayed straddles a word boundary, respectively.

FIG. 5 shows a writing procedure of the left side portion of the character. If a character is to be drawn n bits to the right of a word boundary, it is necessary to first take out only the left part of the character font read from the CG. For this reason, the character font is shifted right by n bits. At this time, a shift operation causes a meaningless empty bit as a character font. When the left part of the character font obtained in this way is written to the frame memory, the left part of the character is displayed, but if the entire shifted font is written at this time, a meaningless space in the left part of the character resulting from the shift operation is written. Bits are also written at the same time, which damages the previously written characters or figures. In order to solve this problem, as disclosed in Japanese Patent Laid-Open No. 58-125284, a circuit for prohibiting or permitting the rewriting of any bit among the memory means forming one word is provided, and the shifted font is A method is known in which only a necessary portion is written in the frame memory and an unnecessary portion is not written. In the following, the operation of rewriting only the necessary bits in one word and not rewriting the other bits is called bit mask processing.

When the bit mask processing is performed on the unnecessary portion of the n bits supplemented at the time of shifting the font and writing to the frame memory, only the left portion of the character font read from the CG can be displayed. By performing the bit mask processing, the character or graphic previously drawn in the left half of the word in which the character font is written is saved. This completes the display of the left part of the letter "A".

FIG. 6 shows a writing procedure of the right side portion following the left side portion of the character. The character font read from the CG is shifted to the left by (8-n) bits because it is connected to the previously written left part at the word boundary. (If one word consists of m bits, it is (mn) bits, but here m = 8.) As a result of the left shift, there are invalid bits on the right side of the font as patterns for representing characters. Occurs. Bit mask processing is applied to this invalid portion and writing to the frame memory completes the display of one character.

FIG. 7 is a block diagram showing a conventional circuit example for performing the above-described operation.

In FIG. 7, 1 is a central processing unit (hereinafter abbreviated as CPU) which controls the overall drawing process, 2 is an address bus for transmitting an address signal generated by the CPU 1 for specifying peripheral devices and memories, and 3 is CPU1 is a data bus for transmitting and receiving data signals to and from peripheral devices and memory, 4 is CG, 5-1 to 5
-8 is a memory element (for example, Hitachi HM4864 etc.) that constitutes a frame memory, and 6 is the CPU 1 having memory elements 5-1 to 5-8.
A shift circuit for shifting the data signal to be given to the shift circuit, 7 is a shift control circuit for controlling the left shift, right shift and the number of bits to be shifted of the shift circuit 6, 8 is a write timing pulse generated by the CPU 1, 9-1 to 9-8 Reference numeral 10 is a gate circuit for individually controlling the transmission of the write timing pulse 8 to the memory elements 5-1 to 5-8, and reference numeral 10 is a bit mask register for storing a bit for permitting writing and a bit pattern for inhibiting writing during the bit mask processing. .

Hereinafter, the operation of the conventional circuit example of FIG. 7 will be described in detail with reference to FIGS. 5 and 6.

First, the left side portion of the character pattern shown in FIG. 5 is written. To shift the character font read from CG4 to the right by n bits, the control information of the shift circuit 6 is stored in the shift control circuit 7 by the CPU 1. After that, the data given to the memory elements 5-1 to 5-8 by the CPU 1 reach the respective elements after being shifted by n bits to the right by the shift circuit 6. Next, the bit mask register 10 is set to prohibit writing of unnecessary bits included in the shifted fonts. In the example of FIG. 5, the writing of the left n bits of the shifted font is prohibited, and the writing of the remaining (mn) bits is permitted. For example, if m = 8 and n = 5, the value of 00000111 (B) may be stored in the bit mask register 10. The data stored in the bit mask register 10 is given to the gate circuits 9-1 to 9-8, and when the write timing pulse 8 is activated, it is transmitted to the memory elements 5-1 to 5-8. Decide
Since the memory element to which the activation of the write timing pulse 8 is not transmitted does not perform the write operation, the data write is prohibited.

By setting the shift control circuit 7 and the bit mask register 10, the memory elements 5-1 to 5-8 are ready for writing, and the character font read from CG4 is stored in the memory element 5-.
It becomes possible to write in 1 to 5-8. Character fonts read from CG4 by CPU1 are stored in memory elements 5-1 to 5-8.
When writing is attempted, the shift circuit 6 provides the memory elements 5-1 to 5-8 with data obtained by shifting the character fonts by n bits to the right. The write timing pulse 8 is activated by the write operation of the CPU1,
Gate circuits 9-1 to 9-8 and bit mask register 10
By this function, only the specific element selected by the bit mask register 10 among the memory elements 5-1 to 5-8 becomes the writing operation, and only the necessary portion of the shifted character font is written. This completes the writing of the left part of the character.

Writing on the right side of the character pattern can be performed in exactly the same manner.

First, the shift control information is stored in the shift control circuit 7, and the shift circuit 6 is set to perform a left (mn) bit shift operation.
n) Store data for which writing is permitted for the right bit and writing is prohibited for the right n bit. Thereafter, the character font read from CG4 may be written in the memory elements 5-1 to 5-8.

By the way, in an application in which not only the characters are displayed but also other figures such as design drawings and maps are displayed in a mixed manner, the letters should be lit in the character pattern as shown in FIG. 3 (a). Draw only the pixels, that is, the black circles,
It is desirable to save the already drawn figures for the other parts. In order to realize this in the conventional circuit example of FIG. 7, the bit mask register 10 must store the data for permitting the writing of only the black circles in FIG. 1 (a). After the character font read from CG4 is shifted by software, the bit mask register
Must be written in 10 prior to writing the font font. As a result, the processing time has been greatly increased. Further, in this case, the shift circuit 6 cannot be used at all.

Further, even when the entire character pattern shown in FIG. 3 (a) is drawn or only the pixels forming the character, that is, the part indicated by the black circles in FIG. 3 (a) is drawn, the character font written in the frame memory is written. When crossing a word boundary, the settings of the bit mask register 10 must be changed on the left and right of the word boundary. In the conventional circuit shown in FIG. 7, the input of the bit mask register 10 is directly given from the CPU 1, and all the bit mask information must be generated by the software inside the CPU 1, and the software required for the bit mask processing is complicated. And increased processing time.

[Object of the Invention]

An object of the present invention is to eliminate the above-mentioned problems and to provide a memory write control circuit capable of writing a character at high speed to a bit map type frame memory by performing bit mask processing more easily.

[Outline of Invention]

In order to achieve the above object, the present invention has a configuration for prohibiting or permitting a writing operation for each memory element by the character font itself written in a frame memory.
The calculation and setting process of bit mask information is not required, and the contents of character display processing are simplified and the processing time is shortened.

Example of Invention

 An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, the same circuit parts as those in FIG. 7 are designated by the same reference numerals.

In the embodiment of FIG. 1, one of the inputs of the gate circuits 9-1 to 9-8 is supplied with the same signal as the output of the shift circuit 6, that is, the input to the memory elements 5-1 to 5-8.

The operation of the embodiment shown in FIG. 1 will be described below.

Prior to writing to the memory elements 5-1 to 5-8, the CPU 1 sets the shift control circuit 7, and first draws the left side portion of the character font. Therefore, as in FIG.
Perform bit shift operation. Next, one character font word read from CG4 is written into the memory elements 5-1 to 5-8. This character font is shifted right n bits by the operation of the shift circuit 6 and then given to the memory elements 5-1 to 5-8, and at the same time, the gate circuit 9 is provided.
-1 to 9-8. Gate circuits 9-1 to 9-8
Among them, the one given the logical value "1" in the bit information of one word constituting the shifted character font, activates the write timing pulse 8 in the memory elements 5-1 to -5.
Those which transmit to the connected element of -8 and are given the logical value "0" suppress the transmission of the write timing pulse 8. As a result, among the memory elements 5-1 to 5-8, the one to which the write timing pulse 8 is transmitted is in the write state, the logical value “1” is written, and the one to which the write timing pulse 8 is not transmitted is not written. It is not performed and keeps the contents that it remembers from before. For example, the same 1-bit signal out of the output of the shift circuit 6 is input to the memory element 5-1 and the gate circuit 9-1, and when this signal takes a logical value "1", the gate circuit The write timing pulse 8 is transmitted to the memory element 5-1 through 9-1, and the logical value "1" is applied to the memory element 5-1.
Is written. When the signal given from the shift circuit 6 to the gate circuit 9-1 has the logical value “0”, the write timing pulse 8 is not transmitted to the memory element 5-1.
The contents of the memory element 5-1 cannot be rewritten.

As a result of the above-described operation, only the bits having the logical value "1" contained in the character font shifted right by n bits are written in the memory elements 5-1 to 5-8.

When the writing of the left side portion of the character font is completed, the CPU 1 resets the shift control circuit 7 in order to write the right side portion of the character font, and the shift circuit 6 shifts to the left (m- n) Perform bit shift operation. Next, when one character font word read from CG4 is written to the memory elements 5-1 to 5-8, it is included in the character font bit-shifted to the left by (mn) in the same manner as the left part. Only bits with logical "1" are written.

When the writing of the left side portion and the right side portion of the character font is completed, the writing of one character is completed.

According to the embodiment shown in FIG. 1, since the setting process of the bit mask register is unnecessary, the program for controlling the writing of characters can be simplified and the processing time can be shortened, and the bit mask register itself is not necessary. Therefore, there is an effect that the present invention can be implemented at a lower cost than before.

FIG. 2 is a block diagram showing another embodiment of the present invention.
In FIG. 2, the same circuit parts as those in FIGS. 7 and 1 are designated by the same reference numerals.

In FIG. 2, reference numeral 11 switches the output of the shift circuit 6 and the output of the bit mask register 10 to switch the gate circuits 9-1 to 9-9.
The selector 12 provided to the input of -8 is a select signal for switching the operation of the selector 11. The present embodiment is characterized in that the input of the bit mask register 10 is not given directly from the data bus 3 but is given from the output of the shift circuit 6.

The operation of the embodiment shown in FIG. 2 will be described below.

In this embodiment, there are two operation modes depending on the state of the selector 11. The first operation mode is a mode in which the same operation as that of the embodiment of FIG. 1 is performed, and the second operation mode is a mode in which an operation similar to that of the conventional example of FIG. 7 is performed.

In the first operation mode, the selector 11 selects the output of the shift circuit 6 under the control of the select signal 12 and supplies it as the input of the gate circuits 9-1 to 9-8. At this time, the same input is applied from the shift circuit 6 to the memory elements 5-1 to 5-8 and the gate circuits 9-1 to 9-8, and the same operation as that of the embodiment of FIG. 1 is possible.

In the second operation mode, the selector 11 selects the output of the bit mask register 10 under the control of the select signal 12,
It is given as an input to the gate circuits 9-1 to 9-8. In the second operation mode, the same operation as in the conventional example of FIG. 7 is performed,
Since the input of the bit mask register 10 is obtained from the output of the shift circuit 6, the bit mask information for designating permission or prohibition of writing of the memory elements 5-1 to 5-8 stored in the bit mask register 10 is stored in the CPU 1 by software. There is no need to shift and create. That is, when a character is displayed at a position shifted to the right by n bits (n <m) as shown in FIG. 5 for one word on the frame memory consisting of m bits, the bit mask set in the bit mask register 10 is set. The information must be write protected to the left n bits. Such bit mask information is obtained, for example, by right-shifting n bits of data in which all m bits forming one word have a logical value "1". Normally, this processing is performed by software inside the CPU1. There is. In the embodiment shown in FIG. 2, the memory device 5
Prior to writing -1 to 5-8, it is necessary to set the shift control circuit 7 and the bit mask register 10. For example, the shift control circuit 7 is set so that the shift circuit 6 shifts right by n bits. After that, the data to be written in the bit mask register 10 by the CPU 1 is also shifted to the right by n bits by the shift circuit 6 and then supplied to the bit mask register 10. Accordingly, the CPU 1 has the shift control circuit 7
After setting, all bits that form one word are written in the bit mask register 10 with data having a logical value "1", so that proper bit mask information can be stored in the bit mask register 10.

In the embodiment shown in FIG. 2, there are two operation modes as described above, and only the pixels forming the character, that is, the portion indicated by the black circle in FIG. If you want to save the text in the first operation mode and erase all the squares that overlap under the character you want to display and display the character, you can write the character font in the second operation mode. In any case, there is an advantage that character display processing can be performed more easily and in a shorter time than ever before. Further, FIG. 2 shows a configuration in which the bit mask register 10 and the selector 11 are combined, but in one operating state, the input signal is output as it is (cylinder disconnection state), and in the other operating state, the input signal is temporarily output. Stores the stored contents and continues to output the stored contents regardless of changes in the input signal (latching state) through latch, for example, SN74373 manufactured by TI
Is used for the bit mask register 10, the selector 11 can be eliminated. That is, the bit mask register 10 is formed by a through latch, and instead of causing the selector 11 to select the output of the shift circuit 6, the through latch is in the cylinder missing state, and instead of causing the selector 11 to select the output of the bit mask register 10, the through latch is in the latch state. given that,
The same operation as in the embodiment of FIG. 2 can be performed. Therefore, the selector 11 of the embodiment of FIG. 2 is not always necessary, and the present invention can be implemented at a low cost with a small number of parts.

〔The invention's effect〕

According to the present invention, it is possible to easily perform the bit mask process when displaying a character at a position extending over the word boundary of the frame memory, so that the software for displaying the character can be simplified, and at the same time, the character display can be performed. There is an effect that the processing time required for can be shortened. In addition, there is almost no increase in required hardware compared to the past,
The present invention can be implemented at low cost.

[Brief description of drawings]

1 and 2 are block diagrams showing an embodiment of the present invention, FIG. 3 is an explanatory diagram showing correspondences between patterns representing characters and CG contents, and FIG. 4 is a character display position on the frame memory. FIG. 5 is an explanatory view showing the processing of the left side part of the character at the time of mismatching, FIG. 6 is an explanatory view showing the processing of the right side part of the character at the time of mismatching, and FIG. It is a block diagram of a conventional device. 1 ... CPU, 4 ... CG 5-1-5-8 ... Memory element 6 ... Shift circuit, 7 ... Shift control circuit 8 ... Write timing signal 9-1-9-8 ... Gate circuit 10 ...... Bit mask register 11 …… Selector

Claims (2)

[Claims] 1. An image information storage device which is addressed in units of at least one word consisting of a predetermined plurality of bits, and a central processing unit which reads and writes the image information storage device in units of one word to update pixel information. A character generator that stores bit information representing a character shape that can be read by the central processing unit, and pixel information generated by the central processing unit that is shifted by a predetermined number of bits in a predetermined direction and is used as an input of the image information storage device. The shift device to be provided and, when writing one word of the image information storage device, prohibits writing of a plurality of designated bits in the one word, thereby changing the storage content of any bit in the one word by writing. Protects the pixel information that is not specified and the pixel information that is assigned by the write operation for the unspecified bits. A bit mask means for controlling the writing of data bits to be expressed so that only an arbitrary part of a bit group forming one word of the image information storage device can be changed, and the central processing unit has the character generator. A character / graphic display device for displaying characters / graphics by writing the read bit information to the image information storage device under the control of the bit mask means, which is the result of performing a predetermined shift process through the shift device. In the above, the central processing unit gives data representing pixel information to be written in the image information storage device via the shift device to the image information storage device as input data, and also to the bitmap means. Input data for designating a bit group for rewriting the stored content included in the bit group forming one word of the storage device The bit mask means enables a write operation only to a bit group to be rewritten for a specified storage content in a bit group forming one word of the image information storage device, and passes through the shift device. The data itself representing the pixel information given to the image information storage device itself protects the previously stored contents without rewriting and the bit group forming the bit group forming one word. A memory write control circuit for a character / graphic display device, characterized in that only a necessary portion of the image information stored in the image information storage device is updated by separating the bit groups to be processed. 2. A memory write control circuit for a character / graphic display device according to claim 1, wherein the bit mask means temporarily stores information for designating a bit group whose stored content is to be rewritten. Register means for storing and, when writing to the image information storage device to update the image information stored in the image information storage device, protect from the writing stored in the register means Rewriting is performed with the bit group to be rewritten in the bit group forming one word by the information designating the power bit and the data itself representing the image information given to the image information storage device via the shift device. The image information storage device via the shift device, and has selection means for switching the storage contents from before to the information designating the bit group to be protected. By dividing the bit group to be rewritten from the bit group forming one word by the data itself representing the pixel information given to the above and the bit group to be protected from the previous stored contents without rewriting, Pixel information given to the image information storage device based on the information for updating only the necessary portion of the pixel information stored in the image information storage device or for specifying the bit to be protected from writing stored in the register means. A memory writing control circuit for a character / graphics display device, characterized in that it is possible to select whether to separate a group of bits that should protect the stored contents independently of the data representing the.