JPH06118942A - Liquid crystal display controller and liquid crystal display system - Google Patents

Abstract

PURPOSE:To facilitate display control over a pattern such as a mark and an icon in bit units by providing a segment ROM which stores the pattern independently of a character generator RAM and a character generator ROM. CONSTITUTION:A CPU interface circuit 31, a CR oscillation circuit 32, a display RAM 21 stored with character codes, the character generator RAM 22 stored with character font patterns, the character generator ROM 23, and the segment RAM 24 stored with patterns such as marks and icons are incorporated in a liquid crystal display controller 20. Display patterns read out of the character generator RAM 22 or character generator ROM 23 and segment RAM 24 are outputted from a segment driver 27 on a time-division basis to drive a liquid crystal display 30. In this case, respective driving lines for time-division driving are selected by a common driver 28 in the liquid crystal display controller 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control technique and a technique particularly effective when applied to a liquid crystal drive control, and more particularly to a technique effectively applied to a dot matrix type liquid crystal drive device for character display.

[0002]

2. Description of the Related Art A display system including a conventional dot matrix type liquid crystal display device for character display includes a liquid crystal display device, a liquid crystal drive device, and a central processing unit (hereinafter referred to as CP).
(Abbreviated as U) and a liquid crystal display controller. The liquid crystal drive device includes a display RAM for storing a character code and a character generator RAM and ROM (hereinafter, referred to as CGR) for storing a character font pattern.
(Abbreviated as AM and CGROM).
The CPU is the above-mentioned display R corresponding to the display position of the liquid crystal screen.
A character code to be displayed is written in the address of AM, and an arbitrary font pattern is written in CGRAM.

The liquid crystal display controller first reads the character code stored in the display RAM at the display address corresponding to the display position, uses this as a part of the address of the CGRAM or CGROM, and reads the character font pattern. The liquid crystal display was controlled. Therefore, when displaying a picture pattern such as a mark / icon other than the dot matrix character, CGRAM or C is used for the picture pattern such as the mark / icon.
It was necessary to occupy a part of GROM for use. A liquid crystal driving device equipped with the CGRAM and CGROM is, for example, LCD-manufactured by Hitachi Ltd.
II (issued in February 1984, see "HD44780 User's Manual" p.1 to p12).

[0004]

However, the present inventors have clarified that the above-mentioned technique has the following problems. That is, when the number of picture patterns such as marks and icons increases, CGRAM necessary for storing picture patterns such as marks and icons.
Alternatively, the capacity of the CGROM increases, and the capacity of the CGRAM or CGROM that stores the original dot matrix character font pattern decreases. For example, in a liquid crystal display system equipped with a CGRAM capable of storing a font pattern of 5 × 8 dots for 8 characters, an attempt to display a pattern pattern such as 30 marks / icons will occupy 6 characters of CGRAM. become. Therefore, the CGRAM capacity that can be used to store the original dot matrix character font pattern is limited to the remaining two characters. Therefore, the number of character font patterns that can be displayed simultaneously is limited, and the display control software becomes complicated.

Further, since a pattern pattern such as a mark / icon is stored in the CGRAM or CGROM for use, it is necessary to write a character code for reading out the CGRAM or CGROM into the display RAM at the time of display, which is difficult to use. There is. Furthermore, originally, CGRA
Since M and CGROM store fonts in character units and use them, independent display control cannot be performed for each picture pattern corresponding to each bit. For example CGRA
It is impossible to selectively control the blinking of only a specific picture pattern from a plurality of picture patterns stored in the same address of M and CGROM.

An object of the present invention is to provide a liquid crystal display controller capable of displaying a picture pattern such as a mark / icon in bit units independent of the dot matrix character display. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The typical ones of the inventions disclosed in the present application will be outlined below. First, when displaying a dot matrix character, the display RAM is accessed by using the display addresses sequentially generated according to the display position to read the character code. Next, using this character code and line address (raster address), the character generator ROM is accessed to read the character font pattern. Separately from this, the segment RAM is accessed by using the display address sequentially generated according to the display position at the time of displaying a specific line, and the display / non-display information of the picture pattern such as the mark icon is read.

The dot-matrix character and the mark independent of the dot-matrix character can be obtained by performing the liquid crystal driving for displaying the character font pattern and the liquid crystal driving for displaying the picture pattern such as the mark and icon in a time division manner.・ Display a picture pattern such as an icon on the same screen. Further, in the segment RAM, in addition to lighting information for instructing display / non-display of a pattern pattern such as each mark / icon, attribute information for designating display control such as blinking and black / white inversion for each mark / icon is provided. Store. Here, blinking or the like can be selectively performed for each specific mark / icon from a plurality of mark / icon information in the same address position of the segment RAM. However, this attribute information is not essential.

[0009]

According to the above-mentioned means, the display RAM accessed by the display addresses sequentially generated according to the display position
And a liquid crystal display control device for reading a character font pattern from a character generator RAM or ROM which is accessed by a character code read from the display RAM, and a segment RAM which is directly accessed by a display address sequentially generated according to a display position. Since it is provided with, the display control of the picture pattern such as the mark / icon can be performed by the read bit pattern. Segment RAM for accessing display RAM or character generator RAM and ROM for displaying characters and displaying pattern patterns such as marks and icons
Is accessed in a time-division manner according to the display position, so that dot-matrix characters and picture patterns such as marks and icons independent of them can be displayed on the same screen. In addition, in the data read from the segment RAM that is directly accessed by the display address sequentially generated according to the display position, in addition to lighting information of lighting / non-lighting for each pattern, attributes such as a display method for each pattern are also included. If you include information,
Display control such as blinking for each icon is also possible.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a liquid crystal display system which is an embodiment of the present invention. The display system of this embodiment includes a CPU 10 that executes a display control program, a liquid crystal display controller (liquid crystal display control device) 20 that is controlled by a command sent from the CPU 10, and a liquid crystal display that is controlled by the liquid crystal display controller 20. (Liquid crystal display device). The liquid crystal display controller 20 includes a CPU interface circuit 31, a CR oscillation circuit 32, a display RAM 21 for storing a character code, a character generator RAM 22, a character generator ROM 23 for storing a character font pattern, and a pattern pattern such as a mark icon. It has a built-in segment RAM 24 for storing.

The address spaces of the display RAM 21, the character generator RAM 22, and the segment RAM 24 are independent of each other, and the CPU 10 is in accordance with the display information.
You can freely rewrite the contents. Although not particularly limited, the liquid crystal display controller 20 is formed on a one-chip semiconductor substrate such as single crystal silicon by a known semiconductor manufacturing technique. The CPU 10 is the liquid crystal display controller 20.
A register select signal RS, a read / write signal R / W and a data signal are supplied to a CPU interface circuit 31 therein. When the register select signal RS is low level, it means selection (writing or reading) of the CPU address counter 103, and when it is high level, the display RAM 21 and the character generator RAM 2 are described.
2. It means selection (writing or reading) of the segment RAM 24. The information indicated by the register select signal RS and the read / write signal R / W supplied to the CPU interface circuit 31 is supplied to each circuit block via the internal control bus cb.

For example, when rewriting the data in the display RAM 21, the CPU 10 sends a low level register select signal RS to the CPU interface circuit 3.
Supply to 1. On the other hand, the CPU address counter 103 includes an external data bus DB, a CPU interface circuit 3
The data (predetermined address in the display RAM 21) supplied from the CPU 10 via 1 and the internal data bus db is written. Next, the CPU 10 supplies a high level register select signal RS and a low level read / write signal R / W indicating the write mode to the CPU interface circuit 31. Table 1 shows the relationship between the control signals R / W and RS and the operation modes.

[Table 1]

Further, the CPU 10 has an external data bus D.
B, CPU interface circuit 31 and internal data bus d
The information for instructing the address multiplexer 44 to select the output of the CPU address counter 103 is supplied to the internal control circuit 104 via b. The display RAM 21 is supplied with the display RAM address from the CPU address counter 103, and is further supplied with write data from the CPU 10 via the external data bus DB, the CPU interface circuit 31 and the internal data bus db. RA for display
The data supplied to M21 is written in the address selected by the display RAM address from the CPU address counter 103, and the data rewriting operation ends.

When rewriting the data in the segment RAM 24, the CPU 10 sends the register select signal R
S is set to low level, and the CPU address counter 10
While supplying the segment RAM address to 3,
Information that instructs the address multiplexer 44 to select the output of the CPU address counter 103 is supplied to the internal control circuit 104. Next, the CPU 10 sends the high level register select signal RS and the low level read / write signal R / W indicating the write mode to the CP.
It is supplied to the U interface circuit 31. Then, the segment RAM 24 is supplied with an address from the CPU address counter 103 and further supplied with write data from the CPU 10. The data supplied to the segment RAM 24 is written in the address selected by the address from the CPU address counter 103, and the data rewriting operation is completed.

When the data in the character generator RAM 22 is rewritten, the CPU 10 is operated as described above.
Sets the register select signal RS to the low level, supplies the address for the character generator RAM to the CPU address counter 103, and provides the internal control circuit 104 with information for instructing the address multiplexer 44 to select the output of the CPU address counter 103. Supply. Next, a high level register select signal R
By supplying S to the CPU interface circuit 31 from the CPU 10, the character generator RAM
22 is supplied with an address from the CPU address counter 103, and a low level register select signal RS is supplied to the CPU interface circuit 31 to supply write data from the CPU 10. The data supplied to the character generator RAM 22 is written in the address selected by the address from the CPU address counter 103, and the data rewriting operation is completed.

Next, the display operation will be described. The display address counter 25 sequentially generates display addresses according to the display position on the screen based on the clock signal φ having a predetermined frequency from the CR oscillation circuit 32. Further, the line address counter 26 sequentially generates a raster address according to the raster position of the character display to be driven based on the clock signal φ having a predetermined frequency from the CR oscillation circuit 32. At the time of character display, the address multiplexer 44 displays the display address generated by the display address counter 25 by the internal control circuit 104 on the display RA.
The character code is output to M21, and the character code is read from the display RAM 21 in accordance with the supplied display address.
Further, the address multiplexers 43 and 45 output the character code read from the display RAM 21 and the raster address generated by the line address counter 26. Then, when the display address is the address for the character generator RAM, the character font pattern is read from the character generator RAM 22, and when the display address is the address for the character generator ROM, the character font pattern is read from the character generator ROM 23 to perform the display control. Be done.

On the other hand, when displaying a picture pattern such as a mark icon, the address multiplexer 44 outputs the display address generated by the display address counter 25 by the internal control circuit 104 to the segment RAM 24, and the display control information is output from the segment RAM 24. It is read and display control is performed. The display of characters and the display of pattern patterns such as marks and icons are performed in a time-sharing manner when displaying one screen. The size of the character font and the number of display characters (number of digits x number of lines) are not particularly limited.

The liquid crystal display controller 20 of this embodiment is
The clock signal φ supplied from the built-in CR oscillation circuit 32 is used as a basic clock signal, and the display RAM 21 and the character generator RAM according to the address from the CPU address counter 103 according to the basic clock signal.
22. Read and write operations of the segment RAM 24 are executed. Further, the liquid crystal display controller 20 uses the address from the display address counter 25 for display RA.
The reading operation of M21, the character generator RAM 22, and the segment RAM 24 is executed. As shown in FIG. 5, the liquid crystal display controller 20 of the present embodiment is
The read or write operation by the address from the CPU address counter 103 and the display address counter 2
The read operation by the address from 5 is executed in time series. Each of the read operation or the write operation by the address from the CPU address counter 103 and the read operation by the address from the display address counter 25 is one cycle.

FIG. 2 shows a display example on the liquid crystal display when this embodiment is applied. here,
Although it is not particularly limited, a character font of 5 × 8 dots is 8
The case of displaying digits × 4 lines is shown as an example. Figure 2
In the above example, since the character font of 5 × 8 dots for the first line to the 32nd line is displayed for 4 lines, the RA for display is displayed.
The M21, the character generator RAM 22, and the character generator ROM 23 are read out. That is, the character font patterns for 8 rasters of the first line are read from the first line to the eighth line, the second line from the ninth line to the sixteenth line, and the second line from the seventeenth line to the second line.
The 4th line is read out on the 4th line, and the 4th line is read on the 25th to 32nd lines.

In the 33rd line, a pattern RA such as a mark or icon is displayed.
Reading of M24 is performed. The display pattern read from the character generator RAM 22 or the character generator ROM 23 and the segment RAM 24 is time-divisionally output from the segment driver 27 in the liquid crystal display controller 20 of FIG.
Drive 0. Here, the selection of each drive line in the time division drive is performed by the common driver 28 in the liquid crystal display controller 20. In the example of FIG. 2, 40 segment drivers and 33 common drivers provide 5 ×.
A maximum of 32 characters (eight digits × 4 lines) of 8-dot characters and 40 types of pattern patterns such as marks and icons can be displayed.

Although the character generator RAM 22 and the segment RAM 24 are described as independent circuit blocks in the embodiment of FIG. 1, both are accessed in a time division manner and the address space is also independent as described above. Therefore, they may be provided in the same RAM circuit. Figure 3
An example of the liquid crystal display controller 20 in that case is shown in FIG. However, even in this case, the address spaces of both are independent, and they are time-divisionally accessed by two independent addresses. Address multiplexer 41
According to the control information from the internal control circuit 104,
U10 switches between an address for accessing the character generator RAM 22 and the segment RAM 24 and an address for reading at the time of display.

For example, the address multiplexer 41 is
When the data is switched from the character generator RAM 22 or the segment RAM 24 from the CPU 10, CP
The U address counter 103 outputs the character generator RAM address or the segment RAM address. Also, the address multiplexer 41
The liquid crystal display controller 20 is a liquid crystal display 30.
The address from the address multiplexer 42 is output when the above display is performed. The address multiplexer 42 switches the address for reading the character generator RAM 22 or the segment RAM 24 during display.

FIG. 4 shows an example of the data format of the segment RAM 24 for displaying a picture pattern such as marks and icons. 8-bit display control information is stored in the same address of the segment RAM 24. The lower 5 bits (bit 4 to bit 0) of the display control information store lighting information for lighting or non-lighting a picture pattern such as a mark icon. The most significant bit (bit 7) is attribute information that gives an instruction to blink and display all the lit picture patterns of the picture patterns such as five marks and icons. Bits 6 and 5 are the bit 4 and the bit 4 respectively. This is a bit in which attribute information for giving an instruction to blink and display only the picture pattern for which the lighting instruction is given in bit 3 is stored. The period of blinking display is determined by the clock signal (blink signal) obtained by dividing the clock signal φ by the frequency divider 33.

[0024]

As described above, according to the present invention,
Since a segment RAM for storing picture patterns such as marks and icons is provided independently of the character generator RAM and ROM for storing dot matrix character font patterns, display control of picture patterns such as marks and icons is performed in bit units. It can be easily realized. Further, since the character generator RAM or ROM and the segment RAM are read out in a time division manner to drive the liquid crystal display device, a dot matrix character and a picture pattern such as a mark icon are displayed on the same screen. Can be made.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a liquid crystal display control device and a liquid crystal display system according to the present invention.

FIG. 2 is a diagram showing a display example in the liquid crystal display system according to the present invention.

FIG. 3 is a block diagram showing another embodiment of the liquid crystal display control device and the liquid crystal display system according to the present invention.

FIG. 4 is a diagram showing a format example of data stored in a segment RAM in the liquid crystal display control device according to the present invention.

FIG. 5 is a time chart showing an operating state during one cycle of the liquid crystal display control device according to the present invention.

[Explanation of symbols]

 10 CPU 20 Liquid Crystal Display Controller 30 Liquid Crystal Display

Continued Front Page (72) Inventor Kimihiko Sugiyama 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd.

Claims (12)

[Claims] 1. A display memory for storing a plurality of character codes, a character memory for storing a plurality of character font patterns corresponding to each of the plurality of character codes supplied from the display memory, and a plurality of Has a segment memory for storing the picture pattern and the address output means for outputting a display address for displaying the character font pattern and the picture pattern, and the display address is one of the character font patterns.
So that the display address is supplied to the display memory when it is an address for reading one, and the display address is supplied to the segment memory when the display address is an address for reading one of the picture patterns. A liquid crystal display control device comprising: 2. The address output means further includes the plurality of character codes stored in the display memory, the plurality of character font patterns stored in the character memory, and the plurality of character storage patterns stored in the segment memory. 2. The liquid crystal display control device according to claim 1, further comprising rewriting / reference address outputting means for outputting an address for rewriting or referring to each of the picture patterns. 3. The liquid crystal display control device according to claim 2, wherein the display memory, the character memory, and the segment memory are configured to have different address spaces. 4. The liquid crystal display control device according to claim 3, wherein the segment memory has attribute information for instructing whether or not to blink a picture pattern to be displayed. 5. The liquid crystal display control device according to claim 4, wherein when the picture pattern to be displayed is made to blink, the blinking period is determined by a clock signal of a predetermined frequency. . 6. A control means for outputting a control signal, and a switch means for outputting one of the display address from the address output means and one of the addresses from the rewrite / reference address output means, The control means is a control for causing the switch means to output the address from the rewrite / reference address output means when information for rewriting or referring to the data stored in the memory is supplied from the outside. The liquid crystal display control device according to claim 5, wherein the liquid crystal display control device is configured to output a signal. 7. A CPU for outputting an address and inputting / outputting data, a liquid crystal display device for displaying a plurality of character font patterns and a plurality of picture patterns, and a liquid crystal display device to be displayed on the liquid crystal display device. In a liquid crystal display system including a liquid crystal display control device for supplying a character font pattern and a picture pattern to the liquid crystal display device, the liquid crystal display control device includes a display memory for storing a plurality of character codes and the display memory. A character memory for storing a plurality of character font patterns corresponding to each of the plurality of character codes supplied from the memory, a segment memory for storing a plurality of pattern patterns, the character font pattern and the pattern pattern An address output means for outputting a display address for displaying, When the display address is an address for reading one of the character font patterns, the display address is supplied to the display memory, and when the display address is an address for reading one of the picture patterns, the display is performed. A liquid crystal display system characterized in that an address is supplied to the segment memory. 8. The address output means further includes the plurality of character codes stored in the display memory, the plurality of character font patterns stored in the character memory, and the plurality of character font patterns stored in the segment memory. 8. The liquid crystal display system according to claim 7, further comprising rewriting / reference address output means for outputting an address supplied from the CPU when rewriting or referring to each of the picture patterns. 9. The liquid crystal display system according to claim 8, wherein the display memory, the character memory and the segment memory are configured to have different address spaces. 10. The liquid crystal display system according to claim 9, wherein the segment memory has attribute information for instructing whether or not to blink a picture pattern to be displayed. 11. The liquid crystal display system according to claim 10, wherein the blinking cycle of the picture pattern to be displayed is determined by a clock signal having a predetermined frequency. 12. A control means for outputting a control signal, and a switch means for outputting one of the display address from the address output means and one of the addresses from the rewrite / reference address output means, The control means causes the switch means to output the address from the rewrite / reference address output means when information for rewriting or referring to the data stored in the memory is supplied from the CPU. 12. The control signal output circuit according to claim 11, wherein the control signal is output.
The described liquid crystal display system.