KR100524904B1 - Graphic RAM and liquid crystal device driver having the graphic RAM - Google Patents

Abstract

Disclosed are a graphic RAM and a liquid crystal display device driver incorporating the graphic RAM. The liquid crystal display driver incorporating the graphics RAM according to the present invention interfaces with an external microprocessor to write / read RAM data corresponding to a predetermined address, and scan the RAM data to drive an external liquid crystal display panel. In the graphics RAM to be issued, predetermined RAM data corresponding to an address applied by a microprocessor through a word line is written / read through the bit line and the complementary bit line, respectively, and the RAM data written corresponding to the predetermined scan address is written. A plurality of RAM cells output as scan data and a plurality of transistors connected to respective word lines of the RAM cells, and precharging the scan data output terminal in response to a predetermined precharge control signal, or outputting scan data; Characterized in that it comprises a precharge control means. By reducing two transistors in each RAM cell, the size of the entire graphic RAM and the LCD driver incorporating the graphics RAM can be reduced, and only the enable signal (EN) for selecting a scan address is used. This has the effect of reducing the routing area of the metal lines for the array.

Description

Graphic RAM and liquid crystal device driver having the graphic RAM

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display driver incorporating a graphics RAM, and more particularly, to a graphic RAM and a liquid crystal display driver incorporating a graphics RAM, which reduces the overall chip size by reducing the cell size of the graphics RAM.

In general, an LCD driver integrated circuit (IC) incorporating a RAM for a liquid crystal device (LCD) is a graphic random access memory (GRAM) having the same size as one-to-one correspondence with an external LCD panel. It is provided inside. That is, an LCD driver with a graphics RAM generates a common signal COM and a segment signal SEG to drive an external LCD panel, and the common signal COM drives each column line, and the segment signal SEG. ) Drives each row line (ie, word line).

In addition, the LCD driver generally includes a write / read interface block for interfacing data write / read with a microprocessor (MICROPROCESSOR UNIT: MPU), and scan address (EN / ENB) and COM shift to control timing of scan read. And a scan read timing controller for generating a clock signal and a SEG latch clock signal. In addition, scan data outputted from the graphics RAM is input, the common signal COM is shifted in response to the COM shift clock signal to select the common line of the LCD panel, and the latched scan data output is output in response to the SEG latch clock signal. The apparatus further includes a COM / SEG signal driver for outputting the segment signal SEG.

That is, in order to generate the segment signal SEG and the common signal COM for driving the row lines (ie, word lines) and column lines of the external LCD panel, the graphics RAM inside the LCD driver corresponds to each common line. The SRAM is generated by periodically scanning and reading the data of the graphics RAM.

1 is a circuit diagram illustrating a RAM cell structure of a conventional graphic RAM, and includes a read / write control unit 10 and a scan read control unit 15 having a basic structure. Here, the read / write control unit 10 has NMOS transistors MN11 and MN12 having a gate connected to the word line WD and a drain connected to each bit line / complementary bit line BIT / BITB. And inverters I11 and I12 having an input / output engaged between the sources of MN11 and MN12. Here, the scan read control unit 15 may include a PMOS transistor MP13 having a gate connected to the second storage node N2, a NMOS transistor MN14, and a PMOS transistor MP14 having a gate connected to the complementary scan address ENB. And a NMOS transistor MN13 having a gate connected to the scan address EN.

Referring to FIG. 1, the write / read control unit 10 of the basic cell structure including six transistors corresponds to a bit line BIT or a complementary bit line BITB corresponding to an address applied through a word line WD. It stores predetermined RAM data from the MPU or outputs the stored RAM data to the microprocessor. In addition, the scan read control unit 15 receives RAM data stored in the write / read control unit 10, and the RAM data stored in the write / read control unit 10 corresponding to the scan address / complementary scan address EN / ENB. The scan read operation is performed by outputting the data through the scan data output terminal DOUT.

For example, when the scan address EN is enabled at the high level, when the RAM data stored in the second storage node N2 is at the high level, a low level signal is output to the scan data output DOUT, and the RAM data is output. Is low level, a high level signal is output to the scan data output DOUT.

That is, in the conventional LCD driver, when the inverters I11 and I12 of the read / write control unit 10 are each implemented with two MOS transistors, a total of six transistors for the read / write control unit 10 and In addition, four transistors of the scan read control unit 15 are added to require ten transistors.

2 (a) to 2 (h) are waveform diagrams for explaining a scan read operation of a conventional LCD driver incorporating a graphics RAM, where 2 (a) shows a COM shift clock signal and 2 (b) shows m Bit common signals COM <1: m>, 2 (c) to 2 (e) represent m-bit scan addresses / complementary scan addresses (EN / ENB), and 2 (f) are n-bit scans. Data (DOUT <1: n>) is shown, 2 (g) represents the SEG latch clock signal, and 2 (h) represents the n-bit segment signal (SEG <1: n>).

Referring to FIG. 2, in response to the COM latch clock signal illustrated in FIG. 2A, the scan address EN / ENB illustrated in FIG. 2C is sequentially enabled, and thus the common signal illustrated in FIG. Output (COM) Each time one bit of the common line is selected, the n-bit parallel segment signal SEG <1: n> shown in Fig. 2H is simultaneously output.

That is, the biggest difference between the graphic RAM and the general RAM is that since the graphic RAM is the same size and one-to-one correspondence with the LCD panel, when one common line COM is selected, the data of the number of segments must be read out and output at the same time. The graphic RAM does not read data by one byte, but by enabling the scan address / complementary scan address (EN / ENB) shown in FIGS. 2 (c) to 2 (e) corresponding to the selected common line. The RAM data stored in the cell is output as scan data DOUT <1: n> shown in FIG. 2 (f). At this time, the unselected common line enables the address EN / ENB corresponding to the common line.

That is, the graphic RAM having the RAM cell structure shown in FIG. 1 has a problem in that the size of the graphic RAM is increased because the cell is implemented using 10 transistors, thereby increasing the size of the entire LCD driver. As described above, as the size of the LCD panel increases, the size of the graphic RAM also increases. In a driver IC that drives a very large LCD panel, the size of the graphic RAM becomes 2/3 or more of the total chip size. Should give.

An object of the present invention is to provide a graphic RAM with a reduced overall size by providing a transistor for precharge outside the ram cell and reducing the number of transistors constituting the ram cell.

Another object of the present invention is to provide an LCD driver with a graphics RAM in which the chip size of the entire LCD driver is reduced by embedding the graphics RAM.

In order to achieve the above object, the graphics RAM according to the present invention interfaces with an external microprocessor to write / read RAM data corresponding to a predetermined address, and scans the RAM data to drive an external liquid crystal display panel. In the graphics RAM to be issued, predetermined RAM data corresponding to an address applied by a microprocessor through a word line is written / read through the bit line and the complementary bit line, respectively, and the RAM data written corresponding to the predetermined scan address is written. A plurality of RAM cells output as scan data and a plurality of transistors connected to respective word lines of the RAM cells, and precharging the scan data output terminal in response to a predetermined precharge control signal, or outputting scan data; It is preferable to comprise a precharge control means.

In order to achieve the above object, the liquid crystal display device driver incorporating the graphics RAM according to the present invention interfaces with an external microprocessor to write / read RAM data corresponding to a predetermined address and to drive the external liquid crystal display panel. A liquid crystal display driver which scans and reads the RAM data to generate a common drive signal and a segment drive signal, the write / read interface means for interfacing data write / read between a microprocessor and a liquid crystal display driver. RAM cells and precharge control means, for writing / reading RAM data through the write / read interface means, and driving the RAM data in response to a predetermined scan address and precharge control signal. Output as parallel scan data Scan address and pre-difference in response to the system clock signal and the common / segment signal driving means for inputting the graphics RAM, scan data and outputting the common drive signal and the segment drive signal in response to the predetermined common shift clock signal and the segment latch clock signal Preferably, the control circuit comprises scan read timing control means for generating an azig control signal and generating a common shift clock signal and a segment latch clock signal. The precharge control means includes a plurality of transistors connected to respective word lines of the RAM cells. Then, a precharge control signal is applied to each gate of the transistors.

Hereinafter, a graphic RAM and an LCD driver incorporating the graphic RAM according to the present invention will be described with reference to the accompanying drawings.

FIG. 3 is a schematic block diagram illustrating an LCD driver 30 incorporating a graphics RAM according to the present invention, and includes an MPU write / read interface 32, a graphics RAM 34, and a scan read timing controller 36. As shown in FIG. And a COM / SEG signal driver 38. For convenience of description, the LCD panel 35 connected to the outside of the LCD driver 30 is shown together.

The MPU write / read interface unit 32 is a block for controlling the writing / reading of data between the external microprocessor and the graphics RAM 34. The MPU write / read interface unit 32 receives instructions and data from a microprocessor (not shown) through the input terminal IN. Input, apply an address to the graphics RAM 34 through the word line WD, and write / read to or from the graphics RAM 34 via the bit line / complementary bit line BIT / BITB. Transfer the data.

The graphics RAM 34 includes a plurality of RAM cells and precharge control means, writes / reads RAM data through the MPU write / read interface 32, and responds to a predetermined scan address and precharge control signal. The written RAM data is output as parallel scan data DOUT for driving the LCD panel 35. That is, the graphics RAM 34 writes / writes basic RAM data such as a write function for storing bit map data to be displayed on the LCD panel 35 and a read function for outputting the written data and transmitting the read data to a microprocessor (not shown). Perform a read function. In addition, in order to generate a COM / SEG signal corresponding to a scan address EN output from the scan read timing control unit 36, that is, an enable signal EN for selecting scan data, it is stored in the graphics RAM 34. Output the data as scan data DOUT.

The scan read timing control unit 36 generates a scan address EN and a precharge control signal PRE_CHA as an timing generation and control block, outputs them to the external graphic RAM 34, and shifts the common signal COM. The COM shift clock signal CK1 and the SEG latch clock signal CK2 for latching the SEG signal are generated and output to the COM / SEG signal driver 38.

The COM / SEG signal driver 38 inputs scan data DOUT output from the graphics RAM 34 and shifts the M / A signal in response to the COM shift clock signal CK1 output from the scan read timing controller 36. A common signal COM for sequentially selecting common lines is generated, and the n-bit latched scan data DOUT is segmented in response to the SEG latch clock signal CK2 output from the scan read timing controller 36. Outputs simultaneously as (SEG). Here, the output common / segment signal COM / SEG is applied to the LCD panel 35 to drive the LCD panel 35.

That is, the LCD driver 30 generates a segment signal SEG and a common signal COM for driving the low lines (ie, word lines) and column lines of the LCD panel 35, and each common line is generated for each common line. The bitmap data of the graphics RAM 34 corresponding to the common is periodically read and scanned to generate a segment signal SEG.

FIG. 4 is a circuit diagram illustrating a RAM cell array of the graphics RAM 34 embedded in the LCD driver 30 shown in FIG. 3, and includes a plurality of RAM cells 41a, 41b, 4mn-1, and 4mn. The charge control unit 40 is included. Here, the precharge control unit 40 is composed of n PMOS transistors MP41 to MP4n connected to each row line (that is, a segment line or a word line) of n bits, and the RAM cells 41a to 41n are formed. The first scan address EN1 for selecting the first common line is connected, and the ram cells 4ma to 4mn are similarly connected to the mth scan address ENm for selecting the mth common line.

That is, the graphic RAM 34 illustrated in FIG. 3 is implemented as a RAM cell array as illustrated in FIG. 4, and the precharge controller includes PMOS transistors connected to each word line of the RAM cells 41a to 41mn. The use of 40 reduces the number of transistors constituting the RAM cell to eight. The detailed operation of each of the RAM cells 41a to 4mn is described in detail in FIG. 5 below.

Referring to the RAM cell array illustrated in FIG. 4, n-bit scan data outputs DOUT are connected to m-bit scan addresses EN1 to ENm, respectively, and the scan address EN is connected to an enabled line. The output of the connected ram cell becomes scan data DOUT and is latched by the COM / SEG signal driver 38 and then output as a segment signal SEG.

FIG. 5 is a circuit diagram of a preferred embodiment for explaining each cell structure of the RAM cell array shown in FIG. 4. The write / read control unit 50 consisting of six transistors and the scan read control unit consisting of two transistors ( 55) and is connected to the PMOS transistor MP41 of the precharge controller 40 outside the cell. The ram cell illustrated in FIG. 5 has been described with reference to the ram cell 41a of FIG. 4, and it can be seen that the remaining cells shown in FIG. 4 have the same structure.

Referring to FIG. 5, the write / read control unit 50 which performs data write / read with the MPU is composed of six transistors as in the related art. Here, the inverters I51 and I53 are each implemented with two transistors. In addition, since the scan read control unit 55 which performs scan read to display data on the LCD panel 35 uses the precharge PMOS transistor MP41 outside the RAM cell 41a, two NMOS transistors are used. (MN56, MN58) can be implemented only. That is, the NMOS transistor MN58 of the scan read control unit 55 uses the data of the second storage node N2 of the write / read control unit 50 as a gate input, and the drain thereof is connected to the source of the NMOS transistor MN56. The source is connected to the reference power supply (GND) to transfer the RAM data stored in the ram cell. In addition, the NMOS transistor MN56 uses an enable signal EN indicating a scan address of each common line as a gate input, and a drain thereof is connected to the scan data output terminal DOUT and selects a corresponding common line. On the other hand, the precharge PMOS transistor MP41 provided outside the RAM cell 41a has a power supply voltage VDD connected to a source, a drain connected to the scan data output terminal DOUT, and a precharge signal input to the gate. In response to PRE_CHA, DOUT is precharged to the power supply voltage VDD.

The data write / read and scan read operations of the graphics RAM according to the present invention will be described in detail with reference to FIG. 5 as follows.

First, a data write / read operation with a microprocessor (not shown) will be described. In other words, the first RAM cell 41a of the RAM cell array illustrated in FIG. 4 will be described by way of example. The write / read control unit 50 of the RAM cell 41a is connected to an address applied through the word line WD. Correspondingly, RAM data stored in the first storage node N1 or the second storage node N2 is output through the bit line BIT or the complementary bit line BITB, or externally the bit line BIT or the complementary bit line. The RAM data applied through the BITB is stored in the first or second storage node N1 or N2. The stored data is applied to the gate input of the NMOS transistor MN58 of the scan read control unit 55.

At this time, the scan data output terminal DOUT is pre-set by the low-level precharge control signal PRE_CHA input to the gate of the PMOS transistor MP41 in a period where the scan address EN is at a low level, that is, a period in which the scan address EN is disabled. Be charged and maintain a high level.

That is, a section where the precharge control signal PRE_CHA is at a low level is a precharge section, and a section at which the high level is a scan read section is performed. The scan read operation of the graphics RAM 34 is performed based on the precharge timing. Therefore, when the precharge control signal PRE_CHA is at the low level, the scan address EN is set at the low level, and the transistor MN56 whose gate address is the scan address EN is turned off to turn off the scan data output terminal DOUT. At the same time as PLOATING, the PMOS transistor MN41 is turned on, thereby precharging DOUT to the power supply voltage VDD. In addition, the precharge control signal PRE_CHA is generated by the scan read timing control unit 36 shown in FIG. 3 and periodically repeats the low level and the high level. The scan address EN is enabled at the high level, and the high level scan address EN output from the scan read timing controller 36 is sequentially output from EN1 to ENm to select the common line. Here, in the case of the first RAM cell 41a illustrated in FIG. 5, the precharge control signal PRE_CHA is transferred to the high level in a section in which the high level scan address EN, that is, EN1 is enabled. When the NMOS transistor MN56 of the scan read control unit 55 is turned on, the first common line is selected to output scan data corresponding to the first common line. At this time, the output level of the scan data output terminal DOUT is determined according to the data level stored in the second storage node N2 of the write / read control unit 50. In the case of the RAM cell illustrated in FIG. 5, the scan read control unit 55 is illustrated as inputting data of the second storage node N2, but it is also possible to input data of the first storage node N1.

For example, when the data stored in the second storage node N2 of the RAM cell 41a is at a high level, the NMOS transistor MN58 is turned on and the reference is made through a discharge path formed through the turned-on transistors MN56 and MN58. Since a predetermined current flows through the power supply VSS, the previously precharged high level DOUT becomes a low level. That is, when the RAM data applied from the MPU is inverted and written in the RAM cell 41a, the RAM data is inverted and output again in the RAM cell 41a. As a result, the same data as the input data can be obtained by inverting twice.

On the other hand, when the data stored in the second storage node N2 of the RAM cell 41a is at the low level, the NMOS transistor MN58 is turned off, so that the voltage previously precharged to the power supply voltage VDD remains the output terminal. Output to DOUT to output high level data. As a result, the DMOS is floated because the PMOS transistor MP41 is turned off at the time of the scan read timing, but the scan data output terminal is turned on by the high level voltage that was previously precharged and the turn on / turn off of the NMOS transistor MN58. It can be seen that the level of DOUT is determined.

6 (a) to 6 (i) are waveform diagrams for explaining a scan read operation of the LCD driver 30 incorporating the graphics RAM shown in FIG. 3, and 6 (a) is a scan read timing controller 36. Represents the COM shift clock signal CK1 output from the signal, 6 (b) represents the common signal COM output from the COM / SEG signal driver 38, and 6 (c) represents the precharge control signal PRE_CHA. 6 (d) to 6 (f) denote scan addresses EN <1> to EN <m>, 6 (g) denote data output through the scan data output terminal DOUT, and 6 (h). Denotes the SEG latch clock signal CK2 output from the scan read timing control section 36, and 6 (i) represents the segment signal SEG output from the COM / SEG signal driver 38.

That is, referring to FIG. 6, in response to the COM shift clock signal CK1 shown in FIG. 6A, m-bit common driving signals COM <1> to COM <m> are shifted and output sequentially. Select the common line. In addition, when the precharge signal PRE_CHA illustrated in FIG. 6C output from the scan read timing control unit 36 is based on the common shift clock signal CK1, the half cycle is a precharge period and a half cycle. It can be seen that is a section for performing scan read. In the scan readout period in which the precharge control signal PRE_CHA shown in FIG. 6C is at a high level, the scan addresses EN1 to ENm shown in FIGS. 6D to 6F are sequentially selected. Therefore, in the precharge period in which the precharge control signal PRE_CHA is at the low level, the scan data output DOUT shown in FIG. 6G maintains the high level, and the precharge control signal PRE_CHA is at the high level. In the scan readout interval, n bits of scan data outputs DOUT <1> to <n> are generated each time one bit of the scan address EN is enabled. That is, when one bit of the scan address EN is enabled, the ram cell connected to the common line selected by the address is simultaneously driven, so that DOUT <1> to <n> are simultaneously generated whenever the common signal COM is shifted. Is output. The scan data output DOUT shown in Fig. 6G is latched by the COM / SEG signal driver 38, and is output as an n-bit SEG signal in response to the SEG latch clock signal CK2. as shown in i). The n-bit SEG signals SEG <1> to <n> output from the COM / SEG signal driver 38 are applied to the LCD panel 35 to drive each segment. As a result, the LCD driver 30 shown in FIG. 3 reduces the number of transistors constituting the RAM cells of the graphic RAM 34 compared with the conventional LCD driver, but as shown in FIGS. You can get the output. Therefore, the LCD driver 30 according to the present invention can reduce the size of the graphic RAM 34 by reducing the number of transistors in the structure of the RAM cell by two, thereby reducing the chip size of the LCD driver 30 as a whole. It becomes possible. In particular, in the case of an LCD driver in which the graphics RAM occupies 2/3 or more of the total chip area, the size of the entire chip can be effectively reduced by applying the RAM cell structure according to the present invention.

According to the present invention, the size of the entire graphics RAM can be reduced by reducing two transistors in each cell structure of the graphics RAM, and thus the size of the LCD driver incorporating the graphics RAM can be reduced. In addition, although EN and ENB are conventionally used as an enable signal for selecting a scan address, the present invention has an effect of reducing the routing area of the metal line for the cell array by using only EN.

1 is a circuit diagram illustrating a cell structure of a conventional graphic RAM.

2A to 2H are waveform diagrams for explaining a scan read operation of a liquid crystal display driver incorporating a conventional graphic RAM.

3 is a schematic block diagram illustrating a liquid crystal display driver having a graphics RAM according to the present invention.

FIG. 4 is a diagram for describing a RAM cell array of the liquid crystal display driver illustrated in FIG. 3.

FIG. 5 is a circuit diagram illustrating a cell structure of the ram cell array shown in FIG. 4.

6A to 6I are waveform diagrams for describing a scan read operation of the liquid crystal display driver illustrated in FIG. 3.

Claims (6)

A graphic RAM which interfaces with an external microprocessor to write / read RAM data corresponding to a predetermined address, and scans and reads the RAM data to drive an external liquid crystal display panel. The microprocessor writes / reads predetermined RAM data corresponding to an address applied through a word line through a bit line and a complementary bit line, respectively, and outputs the written RAM data as scan data corresponding to a predetermined scan address. A plurality of RAM cells; And And a precharge control means having a plurality of transistors connected to each word line of the RAM cells and precharging a scan data output terminal in response to a predetermined precharge control signal, or outputting the scan data. Graphic RAM. The method of claim 1, wherein the plurality of RAM cells, Implemented with six MOS transistors, the RAM data stored in the first storage node or the second storage node in response to the address is output through the bit line and the complementary bit line, or applied through the bit line and the complementary bit line. Write / read control means for storing the stored RAM data in the first storage node or the second storage node; And Implemented by two MOS transistors, inputs RAM data stored in the first or second storage node, outputs a precharged signal in response to a predetermined scan address, or outputs the RAM data as the scan data. And a scan read control means, respectively. The method of claim 1, wherein the precharge control means, And each of the transistors having a drain connected to the scan data output terminal, a source connected to a power supply voltage, and a gate connected to the precharge control signal. The method of claim 1, wherein the precharge control means, When the precharge control signal applied to the gate is at a low level, the scan data output terminal is precharged to a power supply voltage. When the precharge control signal is at a high level, the RAM data is scanned in response to the scan address. Graphic RAM output as data. The method of claim 2, wherein the scan read control means, A first transistor having a gate connected to the scan address and a drain connected to the scan data output terminal; And And a second transistor having a gate connected to the first or second storage node, a drain connected to a source of the first transistor, and a source connected to a reference power source. A liquid crystal display device which interfaces with an external microprocessor to write / read RAM data corresponding to a predetermined address, and scans and reads the RAM data to drive an external liquid crystal display panel to generate a common driving signal and a segment driving signal. In the driver, Write / read interface means for interfacing data write / read between the microprocessor and the liquid crystal display driver; And a plurality of RAM cells and precharge control means, and write / read the RAM data through the write / read interface means, and display the RAM data in response to a predetermined scan address and precharge control signal. A graphics RAM for outputting parallel scan data for driving the device panel; Common / segment signal driving means for inputting the scan data and outputting a common driving signal and a segment driving signal in response to a predetermined common shift clock signal and a segment latch clock signal; And Scan read timing control means for generating the scan address and the precharge control signal in response to a system clock signal, and generating the common shift clock signal and the segment latch clock signal; The precharge control means includes a plurality of transistors connected to each word line of the RAM cells, and the precharge control signal is applied to each gate of the transistors. driver.