JPH01239625A - Display device and memory device for bit map - Google Patents

Abstract

PURPOSE:To display plotting data at arbitrary (k) dot addresses by providing a selection means for memory devices which belong to prescribed continuous (k) dot addresses out of (k) first memory device groups and (k) second memory device groups. CONSTITUTION:Low-order 11 bits of the address sent from a CPU1 are used by dividing in a direction of X on a screen and high-order 10 bits in a direction of Y. A shifter 2 shifts data corresponding to the value of four low-order bits of the address, and an adder 3 adds a value represented by a bit 4 on the value represented by 16 bits except for low-order 5 bits of the address, and accumulates it in a first frame buffer 4. In a second frame buffer 5, the address from which low-order 5 bits are excluded is accumulated as the address. A chip select controller 6 selects each memory device which comprises the memory 4 or 5 according to the value of five low-order bits of the address. Thus, it is possible to process and display the data at high speed by reducing a load on the CPU even when the data extends over a word boundary.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a bitmap display device (also referred to as a bitmap display device) that displays characters and figures on a screen using a configuration of pixels (dots), and the display bag. The present invention relates to a memory device for.

[Conventional technology]

The configuration of a conventional bitmap display device will be explained with reference to a block diagram (FIG. 7). 100 is the display screen and l
This is a frame buffer memory that supports pair l. 7
1 creates display screen data and accesses the frame buffer memory 100 to read/write data;
It is PU. In order to speed up screen creation, a bitmap display device refreshes the display screen in consecutive units at a time in the horizontal direction on the display screen.For this reason, frame buffer memory is generally updated horizontally on the display screen starting from the first address of a word boundary. As long as n bits can be accessed simultaneously at one time. Reference numeral 72 denotes a shifter that shifts CPU data at an arbitrary dot position within the display screen sent from the CPU in response to a dot address indicating the start address of horizontally consecutive words on the display screen.

In such a conventional display device, if we look at a 16-bit system, 1) If the data position specified by the CPU does not straddle a word boundary, that is, the shaded area in Figure 8 is likely to be data. In this case, the lower 4 bits of the horizontal dot address sent from the CPU are all O, and
At this time, the shifter 2 does not operate, the data is not shifted, and the data is directly written into the memory at the address specified by the CPU excluding the lower 4 bits.

2) If the data position specified by the CPU straddles a word boundary, that is, if the shaded area in Figure 9 is data, the lower 4 bits of the dot address are not all O, but When the lower 4 bits indicate 3, a) When the CPU starts a read operation at address D, the data in the frame buffer memory is taken into the shifter, and the shifter moves between the word boundary and the actual data boundary. Rotate and shift the data by the difference.

In the example shown in FIG. 9, the data is rotationally shifted by three bits to the lower order side within the shifter, and the shifted data is taken into the CPU.

b) cr'u is the top 3 of the data read in this way
Mask the bits and set all remaining bits to O.

c) The CPU masks the lower 13 bits of the 16-bit write data and sets all remaining bits to O.

d) OR the results of b) and C) above.

e) The CPU puts the result of step d), that is, the swapped data, into the shifter, and transfers the data rotated by 3 bits toward the upper part in the shifter to address D of the frame buffer memory.
write to.

f) The CPU adds 1 to the pinpoint 5 of the address and sells the address D+1. When the CPU starts reading the address D+1, the data in the frame buffer memory is taken into the shifter, and the data in the lower side is transferred in the shifter. The data is rotationally shifted by 3 bits, and this data is taken into the CPU.

g) The CPU masks the lower 13 bits of the data read in r) and sets all remaining bits to O.

h) CPtJ masks the upper 3 bits of the 16-bit male data and sets all remaining bits to O.

i) OR the results of g) and h) above.

j) The CPU puts the result of i), that is, the swapped data, into the shifter, and transfers the data rotated by 3 bits to the upper side in the shifter to address D of the frame buffer memory.
Count on +1.

Because of this procedure, when the data position specified by the CPU straddles a word boundary,
With conventional devices, n bits can only be accessed at once starting from the first address of a word boundary in the horizontal direction on the display screen, so the above a), e), f),
j) requires four accesses to the CPU, b),
Mask data creation stage for performing c), g), h), b) + C) + dL gLh), i)
mask operation, a), b) mask, C) mask,
Result of b), Result of C), f), Mask of g), h)
A memory area was required to store the mask of , the result of g), and the result of h).

As a technique for solving this type of technical problem that occurs when data positions cross word boundaries,
There is a bitmap memory device No. 3686 (May 14, 1986). The gist of this technology is as described below: [a bitmap memory consisting of 2n RAMs in which each word is 1 bit, and each word is 2n bits, and a bit that specifies any 1 bit in this bitmap memory. The above 2n RAMs are selected according to the number m indicated by the lower n bits of the address.
As the address for m RAMs from the top of the list, determine the value obtained by adding 1 to the remaining bits excluding the lower n bits of the above bit address, and use the remaining bits excluding the lower n bits of the above bit address as the address for the remaining RAM. A RAM address specifying means for specifying as is, 2n-bit read data read from the bitmap memory in the read mode, and 2n-bit edge data to the bitmap memory in the write mode, and a shift circuit (f
``Bitmap memory device characterized by ``tfl''
, and with the technology disclosed in the specification, 2+
In order to obtain a value in which all predetermined bits are +1 as an address for m RAMs from the beginning of the ``RAMs, an adder circuit is provided for the number of bits of the frame buffer memory, that is, 1G in the embodiment. A separate RAM addressing section is required.

[Problem to be solved by the invention]

In conventional bitmap display devices, as detailed in the previous section, if the position of the data to be displayed straddles a word boundary, access to the CPU is required as many as four times, and the masked data creation stage 4 times and a mask operation 6 times, and during these series of processes, a memory area was required to store the processing results, even if only temporarily. Therefore, the amount of time required for the CPU was large, the processing time was naturally slowed down, and the capacity of the memory had to be increased by +2.

As a technique to solve this problem,
There is a technique disclosed in No. 3686, but it has the drawback that the adder must be provided with the number of bits of the frame buffer memory (for example, 16 pieces).

This invention was developed by Tomiyama in order to solve such problems, and allows arbitrary data processing in the frame buffer memory without being aware of the word boundaries of the frame buffer memory, which is composed of multiple memory elements (memory chips). It is an object of the present invention to realize a memory device that allows direct access to locations, and to improve a bitmap display device using the memory device.

Furthermore, by controlling memory element selection (chip select) and address selection, display data at a predetermined position can be read/written in a single memory access without the need for a mask operation, and memory storage is possible. The object of the present invention is to realize a bitmap display device and its storage device that require less space, reduce the burden on the CPU, and enable high-speed processing.

[Failure to solve the problem]

The means adopted by the present invention is, first, to prepare two frame buffer memories each consisting of a group of memory elements (a plurality of memory chips), and to connect them in parallel to a common bus.

Second, we introduced the concept of even word addresses and odd word addresses, and divided one of the two frame buffer memories into even frames, which are accessed by even word addresses, and odd word frames, which access the other frame buffers by odd word addresses. Then, a selection means is used which can select and read/write memory elements belonging to a predetermined number of consecutive dot addresses from the memory element groups of the two frame buffer memories.

[Effect]

In the present invention, the number of bits of data k (for example, 16.32
) data lines, a first bus means consisting of a group of memory elements connected to each data line.
1 frame buffer memory and a second frame buffer 1 memory which is also made up of a group of memory elements, and an even word frame memory (to which the first frame buffer memory ) and the concept of an odd word frame memory (allocating the second frame buffer memory) that is accessed using odd word addresses. A memory element selection means (chip select control means) capable of selecting 351 memory element groups corresponding to consecutive dot addresses from among the memory consisting of ten memory element groups is provided, and a rotary shifter is installed. By providing adders and controlling them with the CPU, we improved the processing of data that spanned word boundaries.

〔Example〕

FIG. 1 shows the overall structure of the bitmap display device of the present invention. Although this diagram was drawn in a 16-bit system, it can be developed in the same way in a 32-bit system. The bit allocation method in that case is shown by the numbers in parentheses.

Reference numeral 1 denotes a CPU for realizing functions of creating screen data, writing the data into a frame buffer memory, and displaying a bitmap image on a display device based on the data. The address sent from this CPtJ has, for example, 2n bits, and of the 2n bits of the address, the lower 11 bits are allocated to the horizontal (X) direction on the screen, and the upper 10 bits are allocated to the 11 (Y) direction. .

2 is a shifter that rotates and shifts data from the CPUI in accordance with the value of the lower 4 bits of the address sent from CPtJ1.

3 is an adder that adds the value (1 or O) indicated by bit 4 to the value indicated by 16 bits excluding the lower 5 bits of address 2n bits sent from CPtJ 1. Here, bit 4 refers to the fifth bit from the lowest.

Reference numeral 4 indicates a first memory element (memory chip) group capable of storing 16 bits for storing a display screen whose address is the value added with 1 or 0 by the adder 3. Frame l is a buffer memory. 1
The six memory elements are connected so that each corresponds to one bit of data, and are configured as a memory group (block) with a data width of 16 bits.

5 is a second frame buffer consisting of a memory element capable of storing 16 bits, whose address is the address sent from CPU 1, excluding the lower 5 bits, and for storing the display screen. It's memory.

Its configuration is the same as the first frame buffer memory 4, and these two memories 4.5 have data lines connected to respective buses for each bit. That is, a wired OR connection is made.

6 is a control for outputting a memory element selection signal (chip select signal) for selecting each memory element constituting the first or second frame buffer memory according to the value of the lower 5 bits of the address sent from the CPUI. The memory element selection signal, which is a chip select controller, is a binary signal of 1.0 shown in the right column of the figure, corresponding to the value of the lower 5 bits of the address (left vertical column in Figure 2). Output. This binary signal 1 selects a memory chip, and the binary signal 0 does not select a memory chip. In this embodiment, there are 32 memory element selection signals, and they are sequentially 01.0□.
..., indicated by 0□friend.

The details of the first and second frame buffer memories shown in FIG. 1 are shown in FIG. 3, Ml.

M2...Ml6; and Ml7. MLB...
...M32 is a memory element (memory chip), and the first
and a second frame buffer memory.

Address A is the address added by the adder (3 in FIG. 1) and is the address line of the first frame buffer memory. Address B is the address line of the second frame buffer memory. In addition, the memory element selection signal (5, x
5. , ;Q, , ~0□2 is the output C3 from the chip select controller 6, and the 16-bit data is the first
This is the output of shifter 2 in the figure.

For example, 8, (08H) shown in hexadecimal (Fig. 2 (7)
)ffi mark 4r4) is added to the input of the chip select controller 6, the outputs 01 to Q I4 ; The groups M9 to M16 of the first frame buffer memory and M17 to M24 of the second frame buffer memory are selected, and writing (or reading) is performed to those parts.

Next, filling in the first and second frame buffer memories and reading from the same memories will be explained.

First, the example shown in FIG. 4 is a case where data can be stored in each memory element group constituting the first or second frame buffer memory without straddling word boundaries. The top row shows 16-bit data a0~a processed by the CPUI.
Indicates 1%. The second stage shows data after being shifted by shifter 2.

Since the value a represented by the lower n=4 bits of the dot address is zero, there is no shift, and the data after this shift appears on the data lines of the first and second frame buffer memories. , the memory element selection signal from the chip select controller 6 is
Since +1=5 bits are all zero and are OOH compatible signals in FIG. 2, memory element groups M1 to M16 are selected and written to the memory element group of the first frame buffer memory, and when displayed. is read out. The situation is shown in FIGS. 4(b) and 4(C). This example is the same as that in FIG.

Next, proceed to FIG. 5, which is the same case as FIG. 9.

Here, ゛+1+ lower n+1=5 bits are hexadecimal OIH~0F)I(1
(equivalent to 1-15 in base 0') can be taken.

For example, if the lower 5 bits indicate 038 (3 in decimal), the shifter 2 rotationally shifts the data of the CPU 1 in the upper direction three times and passes it to the first and second frame buffer memories. The chip select controller 6 selects memory elements M4 to M16; M17 to M19. If writing is performed in this state, the memory element group whose selection signal is 0 will not be written.

In this way, by using the value indicated by the lower n or n+1 bits of the dot address and preparing two groups of frame buffer memories, it is possible to realize an effect that does not require consideration of word boundaries in 16 bits.

Next, by employing the first and second frame buffer memories, a 32-bit word boundary exists, but as a method to solve this word boundary problem, the first frame buffer memory Adder 3 (Fig. 1) was placed at the address input of . This adder calculates the upper m-n-1 bits of the dot address (where m is the number of bits of the dot address; n is the number of bits of the word data 2
A word address is calculated by adding the value of the m-nth bit from the upper part of the dot address to the value represented by (corresponding to n). From the X-0, Y=00 position on the display screen
The display data stored in the first frame buffer memory when allocated to the address input in units of words in the (horizontal) direction corresponds to even addresses of i = 0.1 = 2°. is called an even word address. Therefore, the first frame buffer memory is a group of memory elements corresponding to even word addresses.

The 32-bit word boundary is the lower n+ of the dot address.
1 = Appears when 5 bits become IIH to IFH in hexadecimal. For example, to explain the operation when the lower 5 bits become 131+ with reference to FIG. 2 frame buffer memory. The memory element group M is selected by the chip selection signal.
20 to M32; M1 to M3 are selected and data is written. At this time, bit 4 of the address becomes “1°”,
The first frame buffer uses this bit 4 by an adder.
is added to the first frame buffer memory, and the value is added to the first frame buffer memory.
Data is written to a location added by l from the address of the second frame buffer memory.

This is why the second frame buffer memory is referred to as a frame memory with odd word addresses while the first frame buffer memory is referred to as a frame memory with even word addresses.

Although the above description has been given for a system using a 16-bit CPU, it is clear that the system can be applied almost directly to a 32-bit system. In this case, the description of FIG. 1 will be replaced by the numbers in parentheses. Although it can be applied to other numbers of bits, if the configuration is changed to a boat fishing configuration, the following results.

-g, consider a bitmap display device that displays data based on an m-bit dot address indicating the display position on the screen and 2n-bit word data indicating the content to be drawn. The shifter 2 rotates and shifts the word data by a number of times a, which is the value represented by the lower n bits of the dot address, and outputs the shifted word data. The adder 3 becomes an adder that calculates an even word address by adding the value of the m-nth high-order bits of the dot address to the value represented by the m-n-1 high-order bits of the dot address. The memory element selection signal output from the chip select controller 6 is composed of 2n141 lines, and when the value C represented by the lower n+1 bits of the dot address is (a) C≦2n-1, the signals from C+1st to C+2'1st are All are l and all others are 0, and (b) when C≧2n, C-2n
The first frame buffer memory 4, which serves as a memory element selection means for outputting a memory element selection signal in which all the bits from the +1st line to the 0th line are 0 and all others are 1, has a 1-bit unit access function. Lower n+ of dot address
It is composed of 2° memory element groups from 1st to 2n, each holding the display contents of the screen positions from 1 to 2', and receives the memory element selection signals from the 1st to 2+1st memory elements. However, the even word memory element group stores the shifted word data at the even word address of the memory element group where the memory element selection signal becomes 1. The second frame buffer memory 5 has an access function in 1-bit units, and the lower n+1 bits of the dot address hold the display contents of the screen positions from 2n+1 to 2n°1 accordingly.
It is composed of 2n memory element groups up to 1, and the 2n
+1st to 2n1+11th memory element selection signals are received, and the shifted word is transferred to the address represented by the upper m-n-1 bits of the dot address of the memory element group where the memory element selection signal is 1. This is a group of odd word memory elements that store data.

〔Effect of the invention〕

As explained above, in the present invention, −3
For a bus means including a number of data lines corresponding to a standard number of bits k, such as 2, a first frame buffer memory consisting of a group of memory elements connected to each data line, a second frame buffer memory composed of a memory element group, and an even word frame memory corresponding to an even word address;
Introducing the concept of odd word frame memory corresponding to odd word addresses, dividing the frame buffer memory and selecting memory elements belonging to consecutive dot addresses from among them to perform memory loading/reading. This reduces the number of mask operations and code required when accessing data that spans word boundaries.
Is it associated with access to PU? By eliminating complicated processing, processing speed and memory area can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an embodiment of the device of the present invention, and FIG. 2 is a memory element (chip) i! used in the device of the present invention. 3 is a diagram showing the configuration of an embodiment of the memory device of the present invention. FIGS. 4 to 6 are diagrams illustrating the operation of the device of the present invention. FIG. 7 is a diagram showing the configuration of the prior art, and FIGS. 8 and 9 are diagrams explaining the operation of the prior art, and are diagrams showing the relationship between data in the frame buffer memory and each dot on the display screen. In the figure, 1: CPU, 2: Shifter, 3: Adder, 4: First frame buffer memory (even frame memory),
52 second frame buffer memory (odd frame memory), 6: memory element selection means (chip select controller), 100: frame buffer memory of prior art, AD near address, DAT: data, signal from DT logic , M and Ml-M32 represent a memory element (memory chip), and P represents a display screen, respectively. Patent applicant: Anritsu Corporation

Claims (1)

[Scope of Claims] 1. In a memory device for a display device that displays drawing data at arbitrary dot addresses, a bus means including at least k data lines, and a connection to each of the k data lines of the bus means; k first
a second memory element group connected to each of the k data lines of the bus means;
A memory device for a display device, comprising: memory element selection means for selecting memory elements belonging to predetermined consecutive k dot addresses from a group of k+k) memory elements. 2. In a bitmap display device that receives and displays an m-bit dot address indicating the display position on the display screen and 2^n-bit word data indicating the display content, the number of times determined by the numerical value of the lower n bits of the bit address a shifter (2) for shifting the received screen data by a bit; first and second frame buffer memories (4, 5) each consisting of 2^n memory element groups and storing the screen data; The value excluding the lower (n+1) bits of the address is
An adder (3) that calculates the address of the first frame buffer memory by adding the value indicated by bit n, and a group of 2×2^n bit memory elements of the first and second frame buffer memories. Memory element selection means (6
) and a bitmap display device. 3. In a bitmap display device that displays based on an m-bit dot address indicating the display position on the screen and 2^n-bit word data indicating the drawing content, the word data is converted into a value represented by the lower n bits of the dot address. a shifter (2) which rotationally shifts the number of times a and outputs this shifted word data; Adder (3) that adds bit values to calculate even word address
and 2^n^+^ memory element selection means (2^n^+^) which outputs a memory element selection signal which is composed of one line and in which the value C represented by the lower n+1 bits of the dot address satisfies the following conditions (a) or (b). 6), and 2^n from the first to the second^n, which have a 1-bit unit access function and the lower n+1 bits of the dot address hold the display contents of the screen positions from 1 to 2^n, respectively.
The shifted word data is configured from memory elements, receives the first to 2^n memory element selection signals, and transfers the shifted word data to the even word address of the memory element where the memory element selection signal becomes 1. an even word memory element group (4) that stores , and has a 1-bit unit access function so that the lower n+1 bits of the dot address are 2^n+1 to 2^n^+^1.
The second ^n^+ which holds the display contents of each screen position.
It is composed of 2^n memory elements from ^1 to 2nd^n^+^1, and from the 2^n+1st to 2^n^+^1
An odd number that receives the memory element selection signals up to the first memory element selection signal and stores the shifted word data at the address represented by the upper m-n-1 bits of the dot address of the memory element group where the memory element selection signal becomes 1. A bitmap display device comprising a word memory element group (5). (a) When C≦2^n-1, C+2^ from C+1st
All numbers up to the nth number are 1, and all others are 0. (b) When C≧2^n, all values from C-2^n+1 to C are 0 and all others are 1.