JPS61112270A - Byte converter - Google Patents

Abstract

PURPOSE:To attain a simple and high-speed byte conversion by providing a byte rotating circuit which replaces the byte of the input data, a buffer circuit and a control circuit which designates an input data writing area to said buffer circuit. CONSTITUTION:In case two devices have 2 bytes and 4 bytes respectively, the input data is replaced for each byte by a byte rotating circuit 6 and stored to an area of a buffer 7 which is designated by a buffer output control circuit 8. A buffer output control circuit 9 designates the area that should be read by the buffer 7. In this case, the output data given from the circuit 6 is written to a designated area. Thus the circuit 9 reads out the output data successively and every 4 bytes and delivers them to the device at the other side at every 4 bytes.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a byte conversion device for data transfer between arbitrary devices, and particularly to a byte conversion device suitable for application to data transfer between a memory and a peripheral device. .

(Prior Art) In a device having a memory in which one word is composed of a plurality of bytes, there are cases where memory access is executed in units of bytes. For example, when one word of the memory is composed of 4 bytes, 7 bytes from the 4th byte of any one word are written to the memory. In this way, the memory access start address is not necessarily the word start byte. For example, in a memory where one word has a 2-byte configuration and the memory access start address is the lower byte, conventionally the control shown in the flowchart shown in FIG. 5 has been realized by software, firmware, or hardware.

FIG. 5 is a flowchart showing the procedure at the time of memory write. First, in step 20, an initial value of the number of input data is set. That is, the initial value m is set to m=1. In step 21, first data (Data m:
m=1) is stored in Renostar R,. Step 22
At , the upper and lower bytes of the data in register R1 are converted and stored in register R2. In step 23, the upper byte of register R2 is masked (OOFF), and only the lower byte of register R2 is transferred to address t (Mem) of the memory.
Write to (4).

In this case, memory addresses are given for each byte. In step 24, the number of transferred bytes is set to -1 (n-1
→n), and the number of input data m is +1 (m+1→m).

And the memory address t is +Bt+1→g. In step 25, the number of transferred bytes is checked, and if it is 2 or more, step 26 is executed. In step 26,
The second manual data (Data m: m=2) is stored in the register R1. In step 27, register R
The upper and lower bytes of data 1 are exchanged and stored in register R3. In step 28, the upper byte of register R2 (lower hide of the first data; FF00) and the lower pi i of register R3 (upper byte of second data; 0OF)
F) is the area Me specified by memory addresses t and t+1.
Write to m (t) and Mem (t+1), respectively. Memory address t.

t+1 is one word of memory and can be written to simultaneously. In step 7629, the contents of register R3 are transferred to register R2 (R3→R2), the number of transfer data bytes n is -2 (n -2→n), and the memory address t is +
2C1+2→t), and the number of data m is +1 (m-t-1
→m) Return to L, Stella 7'25. The above operation can be repeated until n≦1 (the number of transfer data bytes remaining is 1 byte or less) in step 25.

In step 25, if n≦1, step 30
Execute. In STETSU f30, the number of remaining bytes is 1 or O.
Make a judgment. When 0, these operations are finished, and when 1
At step 31, the upper byte (lower byte of the final input data) is written to the memory, and then the process ends.

(Problems to be Solved by the Invention) However, in such a conventional configuration, control for byte conversion during data transfer is extremely complicated, as described above. Therefore, when implementing byte conversion using this configuration, the configuration becomes extremely complicated regardless of whether it is software or -hardware. Furthermore, the processing speed of byte conversion becomes slow due to the complicated control. As a result, there is a problem in that the processing speed of data transfer is delayed. These problems occur when the number of bytes that make up a word is large, or when the number of bytes that make up one word in memory differs from the peripheral circuit that executes data transfer, for example, when data from a peripheral device is made up of two bytes. This becomes even more noticeable when one word of the memory consists of 4 bytes.

Therefore, the present invention aims to solve these problems.

(Means for Solving the Problems) The present invention is a byte conversion device that is intended for controlling data transfer between devices that process data with different numbers of bytes. The present invention includes a byte rotation circuit, a buffer, a buffer write control circuit, and a buffer output control circuit. The bite rotation circuit is
Swaps the bytes of human data input from one device.

/'? , 7 stores input data whose byte positions have been swapped in byte units. A buffer write control circuit specifies an area in the buffer where input data is to be written. The buffer output control circuit specifies an area of the buffer to be read and controls the transfer of input data stored in the area to another device.

(effect) As an example, one of the devices has a 2-byte configuration.

The explanation will be based on a case where the other device has a 4-byte configuration.

The 2-byte input data is replaced in units of bytes by a byte rotation circuit.

The input data exchanged in byte units is stored in the buffer area designated by the buffer write control circuit. At this time, by appropriately changing the designation of the first write area of the input data, if the other device has a memory of 4 bytes per word, the input data can be written to any byte position in one word of the memory. becomes possible. The above operations are performed sequentially for each input data having a 2-byte configuration. The buffer output control circuit specifies the area of the vanofa to be read. At this time, since the output data from the byte rotation circuit is written in a pre-specified area, the buffer output control circuit sequentially reads out the data for each number of bytes processed by the other device, that is, every 4 bytes in this case. go.

The read data is transferred to the other device every 4 bytes.

(Example) Hereinafter, the present invention will be described in detail based on an example with reference to the drawings.

FIG. 1 is a block diagram of a byte conversion device according to an embodiment of the present invention. Although not shown, a peripheral device is connected to the input side of the byte conversion device, and a memory is connected to the output side. A first input terminal group 1 receives input data sent from a peripheral device (not shown). This input data consists of a plurality of bytes, and therefore, the first input terminal group 1 receives these input data in parallel. 2 is a second input terminal group that receives part of bit information (for example, the least significant bit) of the memory address of the memory on the output side.

6 is a byte rotation circuit, which selects the first bit based on the lowest bit of the memory address supplied to the second input terminal group 2.
Converts the byte position of each byte of input data input via the input terminal group 1 in a parallel configuration. Reference numeral 7 denotes a buffer, which temporarily stores input data whose byte position has been converted and is supplied from the byte rotation circuit 6 under the control of a buffer write control circuit 8 and a buffer output control circuit 9, which will be described later. In order to write to a predetermined storage area of a memory (not shown), the input data whose byte position has been converted is converted to data in the Noclarel configuration,
Data is sent to the memory via the data output terminal group 10. A third input terminal group 3 receives part of bit information (for example, the lower two bits) of a memory address of a memory (not shown). This bit information indicates in which area of the buffer 7 the input data from the byte rotation circuit 6 should be stored. 9 is a buffer output control circuit, which outputs the input data stored in the buffer 7;
Specifies the data to be read, causes the specified input data to be output, and sends information indicating which data is invalid among the input data to be output to a memory (not shown) via the invalid data instruction output terminal group 11. do. A fourth input terminal group 4 receives information indicating the operation timing of the buffer write control circuit 8. A fifth output terminal group 5 receives information indicating the operation timing of the buffer output control circuit 9.

Next, detailed configurations of the bite rotation circuit 6 and the buffer 7 will be explained with reference to FIGS. 2 and 3, respectively.

The byte rotation circuit 6 shown in FIG. 2 has a parallel configuration in which input data is 2 bytes, and a memory (not shown) has a 4-byte configuration per word. The byte rotation circuit 6 in this case is composed of four selectors 60 to 63 as shown. Each selector outputs either one of the data input to inputs A and Bi (i=0.1...) to output Y. This selection is
It is controlled based on bit information applied to the select input (SEL) via the second input terminal group 2. Each byte of input data has an 8-bit configuration, and data lines from the first input terminal group 1 are connected as shown. Therefore, the lower byte L of the input data is output to the selectors 60 and 61, and the upper byte H of the input data is output to the selectors 62 and 63, respectively.

The buffer shown in FIG. 3 has a configuration corresponding to the byte rotation circuit of FIG. 2. In this case, the buffer consists of eight registers 70-77. Data lines from the byte rotation circuit 6 are connected to each register as shown, while the outputs of each nostar are connected as shown.

Although not shown, control lines from the buffer write control circuit 8 and the buffer output control circuit 9 are connected to each register.

Next, the operation will be explained. The operation described here is
Assume that the configuration shown in FIG. 2 is used as the byte rotation circuit 6, and the configuration shown in FIG. 3 is used as the buffer 7. That is, this is a case where the input data has a parallel configuration of 2 bytes and the memory has a 1 word 4-byte configuration as shown in FIG.

Below, input data is stored in memory as 4P+3 (p=o)
An example will be explained in which data is written sequentially starting from the fourth byte of an address, that is, one word. In Figures 1 to 3,
The first input terminal group 1 contains 2-byte data (Do*DI) :(DI lD2) :(D3) in a parallel configuration.
rD4); ... are supplied in order. Here, it is assumed that the input data of D in which 1 is an even number is the upper byte H, and the input data in which i is an odd number is the lower byte L. Also, D, and Dl constitute the first human power data, and D2 and D
3 constitutes the second human power data, and the following are similarly constituted.

First, the first manual data (Do + Dt) is given to the byte rotation circuit 6. At this time, the second
Input terminal group 2 has memory address 4 P+3 (P=O
) the least significant bit of the address is supplied. Here, the least significant bit of memory address 4P+3 (P=0, 1, 2, . . . ) is 1. This least significant bit is the select terminal (SEL) of each selector of the byte rotation circuit 6.
) is given to The select terminal is at no/no level, so
Input B, side is selected. As a result, selectors 60 and 6
The output of 1 is the lower byte D! is output, and the selector 62
The upper bit D0 is output as the output of and 63. That is, the byte rotation circuit 6 outputs the first manual data with the upper and lower bytes swapped. This output is sent to the buffer 7 and is the upper byte D of the first manual data. is applied to the inputs of Rhenostaf 1.73.75 and 77, and the lower byte D1 is applied to the inputs of Rhenostaf 0.72, 74 and 76, respectively. Next, buffer 7
A buffer write control circuit 8 that controls write signals of each register controls each register based on bit information given via the third input terminal group 3. Here, this bit information is calculated by the number of bytes of the first input terminal group 1 from the memory register 4P+3 (p=o) address specified by the lower two bits of the memory register 4P+3 (p=o) given to the third input terminal group 3. That is, write signals are output to registers corresponding to the number of bytes of the input signal. Memory register 4 P+3 (P=
The lower 2 bits of O) are 11" in binary representation, while the input data is 2 bytes in this case. Therefore, the buffer write control circuit 8 uses the register specified by 11", that is, 11" in decimal representation. In this case, it is 3”, so the fourth register from register 70 is Renostaph 3,
From now on, a write control signal is output for two bytes, that is, to the register 74. As a result, Rhenostav 3 has the first
Top pie of human power data)D. is stored in the register 74
The first human power r-Yu's lower order pi) DI is stored in .

When the input data is stored in the Rhenostuf 3, the buffer output control circuit 9 controls the following in order to output the data stored in the Rhenostaff 0 to 73 to the memory shown in FIG.
Output signals are supplied to these registers 70-73. That is, data is read out from the buffer 7 separately for renostafs 0 to 73 and renostafs 4 to 77, respectively. When the output signal is supplied from the buffer output control circuit 9 to the registers 70 to 73,
The data stored in these is read out. As a result, the upper byte DO of the first manual data is stored at address 4P+3 (P=O) of the memory shown in FIG. In addition, the remaining upper 3 bytes, that is, 4P, 4P+1
Since the data stored in and 4P+2 (P=0 in both) is invalid, the buffer output control circuit 9 is notified to the memory via the invalid data instruction output terminal group 11.

Next, the second human input data (D21D3) is applied to the byte rotation circuit 6 via the first input terminal group 1. As described above, this second manual data is given to the knockoffer 7 as input data with the upper and lower bytes swapped. On the other hand, the buffer write control circuit 8 outputs write control signals to the registers 75 and 76 following the Renostaph 4, respectively. As a result, the upper byte D2 of the second human power data is stored in the renostuff 5, and the lower byte D3 of the second human power data is stored in the register 76. Similarly, the third
The human power data (D4, Ds, ) is given to the byte rotation circuit 6, and as a result, the register 77 stores the upper byte D4 of the third human power data, and the register 70 stores the lower byte D5 of the third human power data. Ru.

When data is written to the rhenostuff 7, the buffer output control circuit 9 outputs an output signal to the rhenostaff 4 to 77. As a result, the register in FIG. 4 has the first
The upper byte D4 of the third human power data is stored in order from the lower byte D1 of the human power data. At this time, since no invalid data exists, the buffer output control circuit 9 notifies the memory that no invalid data exists.

Thereafter, the input data is read in the same manner, and the input data is sent to the memory in word units (4 bytes).

The present invention has been described above based on one embodiment using memory writing as an example. In addition, in the case of memory reading, the memory is provided in the input terminal group, the peripheral device is provided in the output terminal group, and the byte conversion direction (rotation direction) of the byte rotation circuit is reversed, so that the same operation as in the memory write operation is performed. It can be configured as follows.

Furthermore, according to the present invention, the same configuration as in the above-described embodiments can be achieved regardless of the number of bytes of input data and the number of bytes of one word of memory.

(Effects of the Invention) As explained above, according to the present invention, the byte rotation circuit and the buffer can be configured in a simple manner by taking into consideration the number of bytes of input data and the number of bytes for one word of memory. The present invention can be configured in a code-like manner using parts, and these can be controlled only by the memory and the input/output timing of input data, and a high-speed and regular byte conversion device can be provided.

Further, according to the present invention, it is possible to easily cope with an increase in the width of human-powered data and an increase in the transfer speed. The present invention is suitable for application not only to data transfer between a memory and a transfer device, but also to data transfer between arbitrary devices.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a detailed configuration of the rotation circuit shown in FIG. 1, and FIG. 3 is the same as that shown in FIG. a block diagram illustrating an example of a detailed configuration of the illustrated buffer;
FIG. 4 is a diagram showing how input data is stored in memory, and FIG. 5 is a flowchart showing a conventional byte transfer method. 6... Byte rotation circuit, 7... Buffer. 8... Buffer write control circuit, 9... Buffer output control circuit, 60-64... Selector, 70-77.
··register

Claims (1)

[Claims] In a byte conversion device that controls data transfer between devices that process data with different numbers of bytes, there is a byte rotation circuit that swaps input data input from one device in byte units, and bytes output from the byte rotation circuit. A buffer that stores input data whose position has been swapped in byte units, a buffer write control circuit that specifies an area in the buffer where the input data should be written, and an area that specifies the area where the input data should be read from the buffer and stores it in the area. 1. A byte conversion device comprising: a buffer output control circuit for controlling transfer of input data to another device.