JPH02110758A - Dma transfer system - Google Patents

Abstract

PURPOSE:To attain DMA transfer even when the address of the memory area of a transfer source is not continuous converting a pseudo address for a DMA controller to a real address for a CPU, and making access to the memory area composed of a discontinuous address. CONSTITUTION:An address converting part 4 converts the continuous pseudo address given to a direct memory access (DMA) controller 2 to a real address for plural memory areas M1 to Mn having the discontinuous address given to a CPU 1. At a elector 5, the pseudo address and the real address are respectively selected by a selecting signal SEL with the DMA controller 2 and the CPU 1 and the data transfer is carried out. Thus, even when the address of the memory areas M1 to Mn of the transfer source is discontinuous, the DMA transfer can be performed.

Description

[Detailed Description of the Invention] [Summary] Regarding a method in which a CPU and a DMA controller use a common bus to transfer data between storage areas by DMA, even if the addresses of the transfer source storage areas are discontinuous,
The purpose is to realize a method that can perform transfer, and converts consecutive pseudo addresses given to the DMA controller into real addresses for multiple storage areas where addresses given to the CPU are not consecutive. an address conversion unit that converts the pseudo address and the real address into the D
It consists of an MA controller and a selector that selects and transfers data based on a selection signal from the CPU.

[Industrial application field]

The present invention relates to a DMA transfer method, and particularly relates to a CPU and a DMA transfer method.
(Direct Memory Access) This relates to a method in which a controller uses a common bus to DMA transfer data between storage areas.

As the amount of information processed by a CPU increases, its processing speed decreases, so to prevent this, it is necessary to reduce the processing load on the CPU by transferring data using DMA.

[Conventional technology]

As shown in FIG. 4, the traditional MA transfer method, which has been commonly used, transfers the start address of a storage area 11 such as a memory or register as a data transfer source and the start address of a storage area 12 as a data transfer destination. By giving the number of data in advance to the program of the MPU (microcomputer control unit) 10 consisting of the CPUI and the DMA controller 2, the data in the transfer source storage area 11 is read from the above-mentioned start address via the common bus B and transferred. This is a method in which data is sequentially written from the first address of the transfer destination storage area 12 by the number of data.

By doing this, data transfer is performed only by the DMA controller 2, and the CPU
The processing load of the CPU is reduced, and the processing capacity of the CPU itself can be improved.

[Problems to be Solved by the Invention] As described above, when performing DMA transfer, addresses of storage areas need to be continuous.

For this reason, as shown in FIG.
If it is separated into M1 to M in SI, the sixth
As shown in the figure, when writing part of the data (hatched portion) in each of these storage areas M1 to M7 in order to the transfer destination storage area 12, the CPU writes each storage area as shown in FIG. Address generation and reading of each data M1 to Mn,
There was a problem in that DMA transfer using the DMA controller 2 could not be performed because the data had to be written to the transfer destination.

Therefore, an object of the present invention is to realize a system that allows DMA transfer even if the addresses of the transfer source storage area are discontinuous.

[Means for Solving the Problems] In order to achieve the above object, the present invention, as shown in principle in FIG. An address converter 4 converts the pseudo addresses and real addresses into real addresses for the plurality of storage areas M, to M7, and a selection signal S of the DMA controller 2 and CPUI, respectively.
It is provided with a selector 5 that selects based on EL and transfers data.

[For production]

In FIG. 1, normally the CPUI is the CPUI and the DM
The common bus of the A controller 2 is occupied to store the storage area M, ~
When accessing M7, the selector 5 connects the common bus B to the common areas M1 to Mfi in response to the selection signal SEL, so that access can be made in a normal address space.

Furthermore, when the DMA controller 2 occupies the common bus B, consecutive pseudo addresses given to the DMA controller 2 are input to the address converter 4. In the address conversion unit 4, the storage area M corresponding to the input pseudo address is
1 to Mll are converted into real addresses for access and output to the selector 5. The selector 5 outputs a selection signal S indicating that the DMA controller 2 occupies the common bus B.
Since EL indicates, by outputting the real address from the address conversion unit 4 to the storage areas M, ~Mfi, the transfer source is Storage area M, ~M,
, can be given as separate, discontinuous addresses to realize DMA data transfer.

[Embodiment] FIG. 2 is a flowchart showing an embodiment of the control algorithm used in the DMA transfer method of the present invention shown in FIG. It shows.

The operation of the DMA transfer system according to the present invention shown in FIG. 1 will be described below with reference to FIGS. 2 and 3.

First, the CPU 1 sends the transfer source address, transfer destination address, and transfer data length as pseudo addresses to the DMA controller 1-1.
Set it on roller 2 (step 5l-33) in Figure 2.
Next, start the DMA controller 2 (step S
4). At this time, MPU10 is currently the DMA controller 2.
A selection signal SEL indicating that the address is selected is generated and applied to the selector 5, and the output address from the address conversion section 4 constituted by a ROM is selected.

After that, the DMA controller 2 sends the above transfer source address AAAA to the address converter 4 (step S5
). Then, the address converter 4 converts the transfer source address AAAA as shown in FIG.

The transfer source address AAAA is input data.

For example, the transfer source address BBBB□ of the storage area M2 of the storage areas M1 to Ma corresponding to the storage area M2 is output as real address data.

After this, the DMA controller 2 transfers the transfer destination address DDD.
D, and sends it to the address converter 4, which outputs it as the real address EEEEII of the transfer destination storage area 3 such as DPRAM.

Therefore, the data in the storage area M2 specified by the transfer source address BBBB is read out and written to the transfer destination address EEEE++ in the storage area 3 (step 3).
6).

The above steps S5 and S6 are performed for the transfer data length 0 (step S7), and steps S5 and S6 are repeatedly performed before the transfer ends. That is, in the second step S5, the pseudo transfer source address (AAAA+1
) □ is given to the address conversion unit 4 and the actual transfer source address CCCC++ is output, and in the second step S6, the transfer destination address (DDDD+1) □ is given to the address conversion unit 4.
The actual transfer destination address FFFF□ is outputted, and by executing this process n times as shown in the table of FIG. 2, the transfer of the above data length is completed.

In this way, data at a desired address in the storage areas M1 to M7 can be DMA-transferred to the storage area 3.

Note that a memory or a register can be used as the storage area in the above embodiment. Further, although the data is written in the transfer destination storage area sequentially starting from the first address, other methods may also be used in which data is written discontinuously.

〔Effect of the invention〕

As described above, according to the DMA transfer method of the present invention, the DMA
Since the pseudo address for the controller is converted to a real address for the CPU and the storage area made up of discontinuous addresses can be accessed, DMA transfer is possible, resulting in faster data transfer speeds. At the same time, since data transfer is performed only by the DMA controller, the processing load on the CPU is reduced and the processing capacity of the CPU is improved.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing the principle of the DMA transfer method according to the present invention, Fig. 2 is a flowchart showing an embodiment of the DMA transfer method according to the present invention, and Fig. 3 is a block diagram showing the principle of the DMA transfer method according to the present invention. A diagram showing an embodiment of the address conversion unit used in the present invention. FIG. 4 is a schematic diagram for explaining a general conventional example of a DMA transfer method. FIGS. 5 to 7 are about discontinuous addresses. FIG. 2 is a diagram for explaining data transfer of FIG. In FIG. 1, ■...CPU. 2... DMA controller, M, ~M, , 3... Storage area, 4... Address conversion unit, 5... Selector. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] The CPU (1) and the DMA controller (2) store a plurality of storage areas (M_1 to M_n) whose addresses are not consecutive.
) to another storage area (3) via a common bus (B)
This is a method of MA transfer, in which continuous pseudo addresses given to the DMA controller (2) are transferred to the storage area (M
an address conversion unit (4) that converts the pseudo address and the real address into real addresses for the DMA controller (2) and the CPU (1), respectively.
A DMA transfer method comprising: a selector (5) that selects and transfers data.