JP2901631B2 - Image processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image (graphic) processing device for performing multiple screen access.

(Prior Art) Conventionally, as a technique in such a field, for example, there has been a technique as shown in FIGS. Hereinafter, the configuration will be described with reference to the drawings.

FIG. 2 is a schematic configuration diagram of a conventional image processing apparatus.

The image processing apparatus includes a central processing unit (hereinafter, referred to as a CPU) 1 for image processing, and an instruction S1 regarding image processing output from the CPU 1 is supplied to an image control circuit 10.
The image control circuit 10 controls the control signal S11 according to the instruction S1 of the CPU 1.
, And an image operation circuit 12 connected to the output side of the control circuit 11. The image operation circuit 12 is connected to a red (R), green (G), and blue ( A display memory 20 including a RAM (random access memory) for storing image data such as B) is connected. The image operation circuit 12 controls the control signal S1
1 is a circuit for reading predetermined image data from the display memory 20, performing arithmetic processing, and then writing the arithmetic result to the display memory 20. Display memory 20
The red signal R, the green signal G, and the blue signal B output from are supplied to a display 33 such as a CRT via selectors 30, 31, and 32 that are switched and controlled by the output of the CPU 1 or the like. I have.

FIG. 3 is a diagram showing an example of a configuration image of the display memory 20 in FIG.

The display memory 20 has a plurality of sub-screens (for example, a first plane screen 20-1 to a ninth plane screen 20-9) per coordinate, and a first to third plane screen 20-.
1 to 20-3, the first screen 21 is changed to the fourth to sixth plane screens 20.
-4 to 20-6, the second screen 22 is the seventh to ninth plane screens
The third screen 23 is composed of 20-7 to 20-9. In this figure, Origin is a memory address of a specific coordinate value (for example, address 0) for indicating a comparison between a memory address and a coordinate.

FIG. 4 is a diagram showing an example of the memory map of FIG. The memory map is configured for each screen from the first screen data DA21 to the third screen data DA23.
The red signal R, green signal G, and blue signal B of these first to third screen data DA21 to DA23
It is configured to be selected in 32. Each of the first to third screen data DA21 to DA23 has n pieces of image data from coordinates 0 to (n-1). Memory address
The correspondence between AD and the screen coordinates is as follows: the address 0 of the memory address AD corresponds to the coordinate 0 of the first screen, and in the example of FIG.
Since the screen is switched for each address, the n-th address and the 2n-th address indicate the coordinates 0 of each screen.

The operation of the image processing apparatus configured as described above will be described.

For example, the image data of address 0 in the first screen data DA21 is drawn at the coordinate 0 of the display memory 33, and the image data of address n in the second screen data DA22 is displayed thereon. The operation when multi-window display is performed will be described.

When the image processing instruction S1 is output from the CPU 1, the control circuit 11
Outputs a control signal S11 corresponding to the instruction S1, and supplies the control signal S11 to the image operation circuit 12. The image arithmetic circuit 12 reads the 0th image data in the first screen data DA21 in the display memory 20 (or writes the image data to the 0th address in the first screen data DA21) in response to the control signal S11. Are displayed at the coordinates 0 in the display 33 through the selectors 30 to 32. Next, for multi-window display, the image calculation circuit 12 sends the second screen data in the display memory 20 by the control signal S11.
The display data is written to the n-th address in DA22, and the result is subjected to arithmetic processing.
Write to the address. The image data written at the address 0 is transmitted to the coordinates 0 on the display 33 through the selectors 30 to 32.
Will be displayed. Thereby, multi-window display is performed.

(Problems to be solved by the invention) However, the conventional image processing apparatus has the following problems.

As described above, for example, when a point is drawn at the coordinate 0 of the display 33, the point is drawn at the address 0 of the memory address AD on the first screen 21, but the same coordinate value is drawn on the second and third screens 22, 23. , The memory address AD accesses the n-th address and the 2n-th address. Therefore, the image operation circuit 12 must perform an operation for rewriting the origin ORG based on the control signal S11. That is, without performing such arithmetic processing, the same access to any screen is not possible. As a result, the number of accesses increases, and screen access such as multi-window display slows down. It has been difficult to solve the problem.

The present invention provides an image processing apparatus which solves the problem of the prior art that the screen cannot be accessed in the same manner unless the origin is rewritten, and the screen access time for a multi-window or the like is slow. Is what you do.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention reads out predetermined image data from a display memory capable of storing image data for a plurality of screens, performs an arithmetic process, and outputs the arithmetic result. In an image processing device that writes to the display memory,
Each screen of the plurality of image data is composed of a plurality of sub-screens, and a first data indicating the number of the sub-screens and a second data indicating one of the plurality of image data stored in the display memory. A first circuit that outputs instruction information for a bit position to be processed based on the first data and the second data output from the storage circuit; A second circuit for performing an operation on a desired bit position with respect to the image data and the image data of the transfer destination in accordance with the instruction information output from the first circuit, and transferring the result to the display memory. doing.

(Operation) According to the present invention, since the image processing apparatus is configured as described above, when the first data and the second data are output from the storage circuit to the first circuit, the first circuit Based on the first data and the second data, instruction information for a bit position to be processed is output to a second circuit.
The second circuit performs an operation on a desired bit position on the transfer destination image data and the transfer destination image data according to the instruction information. The calculation result is transferred to the display memory and stored. In this way, by specifying the first data and the second data, image processing such as multi-window processing can be performed on the transfer destination image data and the transfer destination image data.

(Embodiment) FIG. 1 is a schematic configuration diagram of an image processing apparatus showing an embodiment of the present invention, in which elements common to the elements in FIG.

This image processing device is capable of independent access for each screen and includes an image control circuit 10A connected to the CPU 1,
The image control circuit 10A includes a control circuit 11A and an image operation circuit.
It is composed of 12A.

The control circuit 11A is a circuit that outputs a control signal S11a related to plane start position data as second data and a control signal S11b related to plane number data as first data according to an image processing command S1 from the CPU 1. .

The image operation circuit 12A includes a storage circuit including a first register 41 that stores plane number data representing R, G, and B image data, and a second register 42 that stores plane start position data. ing. The plane number data is, for example, as shown in FIG. 3, the number of a plurality of plane screens respectively configuring the first screen 21 to the third screen 23, and corresponds to R, G, B in this embodiment. (Ie, 3). The plane start position data indicates one of a plurality of image data. For example, in FIG. 4, if the third screen data DA23 is indicated, the head address of the third screen data DA23, or This is an address corresponding to the start address. An operation valid bit generation circuit 50 as a first circuit is connected to the output side of the storage circuit, and an operation circuit 60 constituting a second circuit is connected to the output side of the operation valid bit generation circuit 50. ing. The operation valid bit generation circuit 50 performs an operation process on the number of planes data and the plane start position data read from the first and second registers 41 and 42, and provides instruction information for operating only specific bits in the image data. This circuit generates a certain operation valid bit S54, and is composed of a decoder 51, a shift circuit 52, an operation type setting register 53, and an AND gate 54. The decoder 51 is a circuit for decoding the output of the first register 41, the shift circuit 52 is a circuit for shifting the output of the decoder 51 by the output of the second register 42, and the operation type setting register 53 sets the operation mode of the operation circuit 60. Circuit. The AND gate 54 is a circuit that calculates the logical product of the output of the shift circuit 52 and the output of the operation type setting register 53 and outputs an operation valid bit S54, and the output side thereof is connected to the operation circuit 60. .

The arithmetic circuit 60 performs an arithmetic operation (addition) of the transfer source image data DAa read from the display memory 20A or the image control circuit 10A and the transfer destination image data DAb read from the display memory 20A based on the operation valid bit S54. , Subtraction, multiplication, division) or logical operation (OR,
(Logical product, exclusive OR, etc.) and output the transfer destination image data DAc for writing. On the output side of this circuit 60, a display memory 20A and selectors 30A to 32A
A display 33 such as a CRT is connected via the.

The display memory 20A stores image data, and is composed of a RAM or the like. Selector 30A, 31A, 32A
Is a circuit for selecting the output of the display memory 20A and outputting the red signal R, the green signal G, and the blue signal B to the display 33 under the control of the CPU 1 or the like.

FIG. 5 is a diagram showing a configuration example of the display memory 20A of FIG.

This display memory 20A stores R, R on the same address.
First screen data DA2 in which data named G and B are grouped
1, a plurality of image data, that is, second screen data DA22, third screen data DA23,..., From address 0 to address (n-1). These screen data DA21 to DA23 are selected by selectors 30A to 32A, respectively.

The operation of the image processing apparatus configured as described above will be described.

When accessing specific screen data on one address in the display memory 20A in FIG. 5, in step 1, the CPU 1 in FIG.
S1 is given to the control circuit 11A. The control circuit 11A generates control signals S11a, S11b, and the like according to a command from the CPU 1. Control circuit 11A
, The transfer source image data DAa is read out from the predetermined address of the display memory 20A to the arithmetic circuit 60 via the display bus. Here, the image control circuit 10
Reads the source image data DAa from A and computes it
May be supplied to 60.

In step 2, the control signals S11a and S11b
1, the plane number data stored in the first register 41 of the second registers 41 and 42 is decoded by the decoder 51, and the decoding result (eg, “111... 1100... 00”) is obtained by the shift circuit 52. Output to The shift circuit 52 shifts the output of the decoder 51 using the value of the plane start position data stored in the second register 42 as a shift amount, and shifts the shifted data (for example, “000... 1111... 11100... 00”).
To the AND gate 54. The AND gate 54 calculates the logical product of the output of the operation type setting register 53 and the output of the shift circuit 52, and only the bit “1” in the output of the shift circuit 52 is
Set the output of the operation type setting register 53 to the operation valid bit S54.
And supplied to the arithmetic circuit 60.

In step 3, the transfer destination image data DAb stored at a predetermined address in the display memory 20A is read out to the arithmetic circuit 60 via the display bus.

In step 4, the operation circuit 60 sets the operation valid bit
By S54, the source image data DAa and the destination image data DA
Operates only the operation valid bit between b and b. The destination image data DAc, which is the result of the calculation, is stored in the display memory 2
It is written to the transfer destination address of 0A. The written transfer destination image data DAc is selected by the selectors 30A to 32A, output to the display 33 in the form of a red signal R, a green signal G, and a blue signal B, and displayed on the display 33.

 This embodiment has the following advantages.

A first register 41 for storing plane number data,
Second register for storing plane start position data
Since 42 is provided, a memory configuration in which a plurality of images exist on the same address as shown in FIG. 5 can be obtained by designating the plane number data and the plane start position data. Data DA21, DA22,
When accessing DA23 ..., any screen data can be accessed in the same manner without having to rewrite the origin ORG, which is a memory address. Therefore, the access time to the multi-window screen can be shortened. Also, in addition to the multi-window display, for example, when a dynamic screen is displayed on a still screen, the access time can be shortened in the same manner as described above.

It should be noted that the present invention is not limited to the illustrated embodiment, and various modifications are possible such as, for example, configuring the operation valid bit generation circuit 50 with another circuit.

(Effects of the Invention) As described in detail above, according to the present invention, the storage circuit, the first circuit, and the second circuit are provided, so that the first data and the second data can be designated. A single address can access a plurality of screens simultaneously or independently.
Therefore, when accessing an arbitrary screen, it is possible to access any screen in the same manner without performing an operation of rewriting the origin, and it is expected that access time for multi-window display and the like can be shortened.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an image processing device showing an embodiment of the present invention, FIG. 2 is a schematic configuration diagram of a conventional image processing device, and FIG. 3 is a configuration image example of a display memory in FIG. FIG. 4 is a diagram showing an example of the memory map of FIG. 3, and FIG.
The figure shows a configuration example of the display memory of FIG. DESCRIPTION OF SYMBOLS 1 ... CPU, 10A ... Image control circuit, 11A ... Control circuit, 12A ... Image arithmetic circuit, 20A ... Display memory, 30A-32A ... Selector, 33 ... Display, 41,42 ... First and second register, 50 ... Operation effective bit generation circuit, 60 ... Operation circuit.

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Toshihiro Honma 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (58) Field surveyed (Int. Cl. ⁶ , DB name) G09G 5 / 36 G09G 5/02

Claims (1)

(57) [Claims] 1. An image processing apparatus for reading predetermined image data from a display memory capable of storing image data for a plurality of screens, performing an arithmetic process, and writing the arithmetic result to the display memory. Each screen of data is composed of a plurality of sub-screens; first data indicating the number of sub-screens; second data indicating one of a plurality of image data stored in the display memory; A first circuit that outputs instruction information on a bit position to be subjected to arithmetic processing based on the first data and the second data output from the storage circuit; and a transfer destination image data. An operation for a desired bit position is performed on the transfer destination image data in accordance with the instruction information output from the first circuit, and the display memo is executed. And a second circuit for transferring the image data to the image processing apparatus.