JPH02239284A - Picture processing device - Google Patents

Abstract

PURPOSE:To increase the access speed of multiwindow display or the like by providing a picture operating circuit which operates contents of registers to transfer data. CONSTITUTION:A control circuit 11A is provided with plural registers 41 to 43 which temporarily store transfer source plane start position data indicating the plane start position of the transfer source of a display memory 20A, transfer destination plane start position data indicating the plane start position of the transfer destination of the display memory 20A, and plane number data indicating the number of planes of the display memory 20A and output them at the time of the picture data access mode. A picture operating circuit 12A generates operation effective bits and transfer destination effective bits based on transfer source plane start position data, transfer destination plane start position data, and plane number data and operates specific bits out of these effective bits to transfer data from the transfer source address to the transfer destination address in the display memory 20A. Thus, the access speed of multiwindow display or the like is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an image processing device for performing multi-screen access in an image (graphics) processing system.

(Prior art) Conventionally, as a technology in this field, for example, Fig. 2~
There was something like Figure 4. The configuration will be explained below using figures.

FIG. 2 is a schematic configuration diagram of a conventional image processing system.

This image processing system uses central processing equipment for image processing (
The image processing device 10 is equipped with a CPU (hereinafter referred to as a CPU) 1, and instructions S related to image processing issued from the CPU 1 are
will be supplied to The image processing device 10 executes the instruction S of the CPU 1.
a restraint circuit 11 that outputs a control signal S11 according to 1;
The image processing circuit 2 is connected to the output side of the image processing circuit 12, and the image processing circuit 2 is connected to the display path 13 to display red (R) and green (G) representing the three color elements.
A display memory 2 consisting of a RAM (random access memory) for storing image data such as , blue (B), etc.
0 is not connected. The image processing circuit 12 is a circuit that reads predetermined image data from the display memory 20 in response to the control σ11 signal S11, performs arithmetic processing on the data, and then stores the result of the arithmetic operation in the display memory 20. The red signal R, green signal @G, and blue signal B output from the display memory 20 are sent to C via selectors 30, 31, and 32 whose switching is controlled by the output of the CPU 1, etc.
The configuration is such that the signal is supplied to a display 33 such as an RT.

FIG. 3 is a diagram showing an example of the configuration of the display memory 20 in FIG. 2.

The display memory 20 has a first plane screen 20-1 to a ninth plane screen 20-9 for each coordinate, and the first to third planes Jη and the first to third planes 20-1 to 20-3.
Screen 2] is the fourth to sixth brain screen 20-4 to 20-
6, the second screen 22 is the seventh to ninth plane screen 20-7
~ 20-9, the third surface 23 is configured respectively. In this figure, the origin (orig+; ORG) is
This is a memory address of a specific coordinate value (for example, address O) to show a comparison between a memory address and coordinates.

FIG. 4 is a diagram showing an example of the memory map of FIG. 3.

The memory map is configured for each screen, from the first screen data DA21 to the third screen data DA23 and C'. These first to third screen data DA21 to DA2
3's let signal R, green signal G, and blue signal B are:
It is configured to be selected by each selector 30 to 32.

Each of the first to third screen data DA21 to DA23
holds n image data from XaO to (n-1>. Memory address AD and screen coordinates j
In this case, the Oth address of the memory address AD corresponds to the second screen O on the first screen, and in the example of FIG. 4, since the i side is switched every nth address, the It points to the coordinate O of each screen.

The operation of the image processing system configured as above will be explained.

For example, the image data at the Oth address in the first screen data DA21 is drawn at the coordinate O of the display 33, and the image data at the nth address in the second screen data DA22 is further displayed on top of that. The operation when performing multi-window display will be explained.

When the image processing command S1 is not output from the CPU 1, the control circuit 11 outputs a control signal S11 corresponding to the command S1,
The control signal S11 is given to the image calculation circuit 12. In the image calculation circuit 12, according to the control signal S11, image data is written to the O-th address in the first screen data DA21 in the display screen 20, and it is sent to the selectors 30 to 3.
2 and displayed at the coordinate O in the display 33.

Next, for multi-window display, the image expansion calculation circuit 12
reads the display data at the nth address l\ in the second screen data DA22 from the display memory 20 according to the control signal @S11, performs arithmetic processing on it, and then transfers the result of the calculation to the first screen data. Write to address O in OA21. The image data written to this O-th address is the selector 30~
32 and is displayed at the coordinate O on the display 33. This allows multi-window display.

(Problems to be Solved by the Invention) However, the image processing apparatus with the above configuration] O had the following problems.

As mentioned above, for example, when drawing a point at the position O on the display 33, the memory address △ is displayed on the first screen 21.
A point is drawn at address O of D, but the second and third screens 22.
In 23, even if points are drawn at the same coordinate values, the memory address AD accesses the n-th address and the 2n-th address. Therefore, the image calculation circuit 12 must perform calculation processing to rewrite the origin ORG based on the control signal @S11. In other words, unless such calculation processing is performed, it is impossible to access any screen using the same coordinate system. As a result, the number of accesses increased and screen access such as multi-window display became slow, which was a problem that was difficult to solve.

The present invention solves the problems that the conventional technology had in that it is not possible to access any screen using the same coordinate system without rewriting the OINOJIN ORG, and the screen access time for multi-windows etc. is slow. A processing device is provided.

(Means for Solving the Problems) In order to solve the above problems, the present invention inputs a command related to image@processing, reads predetermined image data from a display memory, performs processing, and then performs the processing. The image processing device for outputting the image processing results to the display memory includes a control circuit and an image calculation circuit. Here, the control circuit includes transfer source plane start position data indicating a transfer source plane start position of the display memory, transfer destination brain start position data indicating a transfer destination BrainStar 1 position of the display memory, and the display memory. This circuit has a plurality of registers for temporarily storing brain number data indicating the number of memory planes and outputting it when image data is accessed. The image calculation circuit generates a calculation valid bit 1 and a transfer destination valid bit based on the transfer source brain start position data, transfer destination plane start position data, and plane number data, and specifies the specific bit i of these valid bits. } to perform data transfer from the transfer source address to the transfer destination address in the display memory.

(Function) According to the present invention, since the image processing device is configured as described above, the control circuit can process the transfer source plane start position data, the transfer destination brain start position data, and the plane fault position data in the image data access mode. Output the data to the image calculation circuit. Image processing circuit (U) Generates a calculation valid bit and a transfer source valid bit from the data, and uses this data to calculate only the specific bit 1. Therefore, the above-mentioned problem can be solved.

(Example) Figure 1 shows an example of the present invention. 2 is a schematic configuration diagram of an image processing system including an f4i processing device, and a second
Elements common to those in the figures are given the same reference numerals.

This image processing system allows independent access for each screen, and the image processing device 10A connected to the CPU 1.
The image processing unit 10A includes a control circuit 11A and an image calculation circuit 12A.

The control circuit 11A receives an image processing command $1 from the CPIJ1.
Based on this, for example, data related to R, G, B image data is held and outputted, and plane number data S4
1, a second register 42 that temporarily stores destination plane start position data S42, and source plane start position data 843.
It is provided with a third register 43 and the like for temporarily storing and storing the information.

The image calculation circuit 12A connected to the output side of the υ1 control circuit 11A performs an operation on the data read from the display memory 2OA and writes the operation result to the display memory 2OA, thereby generating an operation valid bit. circuit 50
, and a reduction device 60, and a shift circuit 60 on the output side thereof.
, and a color data calculation circuit 62 are connected. The operation valid hit i- generation circuit 50 receives the brain number data 84.1 successively output from the first and second registers 41 and 42.
This is a circuit that calculates and processes the transfer destination brain start position data 342 (C) and generates a numbing effective bit S50 for operating only a specific bit in the image data. The reducer 60 performs shift 1 by subtracting the transfer destination plane start position data S42 read from the second and third registers 42 and 43 and the transfer source plane start position 343.
This is a circuit to obtain 860. The shift circuit 61 transfers the source image data D read out from the display memory 2OA.
It has a function of shifting Aa according to shift ms60 and outputting a transfer source valid hit S61. Based on the operation valid bit 850, the color data calculation circuit 62 performs an arithmetic operation n (addition, reduction, multiplication, This circuit performs division] or logical operations (logical sum, logical product, exclusive logical sum, etc.) and outputs the transfer destination image data DAC for writing.The shift circuit 61 and the calculation circuit 62 include the display memory 2OA and Display 33 such as CRT via selectors 30△ to 32A
is not connected.

The display memory 2OA stores image data and is composed of a RAM and the like. Selector 30A.
31A and 32Δ are circuits that select the output of the display memory 2OA and output a red signal R1, a green signal G, and a blue signal B to the display 33 under the control of the CPU 1 or the like.

FIG. 5 shows the arithmetic valid bit generation circuit 5 in FIG.'1.
0 is a diagram showing a configuration example of 0. FIG.

Performance C! The valid bit generation circuit 50 includes a decoder 51, a shift 1 circuit 52, a sleep type setting register 53, and an AND gate 54. The decoder 51 is a circuit for reading plane number data S41 vf'I, and a shift circuit 62
is a circuit that shifts the output of the decoder 51 by 1 using the transfer destination plane star 1 position data S42 as a shift amount, and the calculation type setting register 53 is a circuit that sets the cylinder mode of the calculation circuit 62.

Further, AND gate 1-54 is a circuit that calculates the logical product of the output of the shift circuit 52 and the output of the performance type setting register 53, and outputs the performance effect pit 354 to the arithmetic circuit 62.

FIG. 6 is a diagram showing a configuration example of the display memory 2OA of FIG. 1.

This display memory 2OA is located on the same address.
,G. A plurality of image data such as first screen data DA21, first screen data OA22, third screen data DA23, etc., which are a set of data named B, are stored from the Oth address to the (n-1)th address. It is configured so that it can be done. These screen data DA21 to DA23 are selected by selectors 30A to 32Δ, respectively.

FIG. 7 is an operation waveform diagram of FIG. 1. Referring to this diagram, the operation is performed when, for example, data is transferred from the second screen 22 of the transfer source image data DAa to the third screen 23 of the transfer destination image data DAb. Explain.

In step 1, the CPU 1 in FIGS. 1 and 5 provides an instruction S1 regarding image processing to the control circuit 11A. Transfer source image data DAa is successively output from a predetermined address of display memory 2OA to shift circuit 6 via the display bus.

In step 2, the transfer source brain start position data S43 and the transfer destination plane start position data 842 stored in the third and second registers 43 and 42 are read out, and are subtracted by the subtractor 60, and the subtraction result is A certain shift 1360 is applied to shift circuit 61. The shift circuit 61 shifts the source image data DAa with a shift IS60, and the source valid bit 861 is at the same bit position as the destination image data DAb, which will be described later.
2 calculation becomes possible.

In step 3, the second and '1st registers 42, 41
Transfer destination Brainstar 1 to location data S4 stored in
2 and plane number data 341 are input to the calculation valid bit generation circuit 50. Arithmetic valid bit I/generation circuit 50
In the plane number data S41, the decoder 5
1, and the decoding result (for example, "11"l
・・・・・・1100・・・・・・00′″》is Sif 1
- Output to circuit 52. The shift circuit 52 shifts the output of the decoder 51 by using 1 shift of the transfer destination brain start position data 842 as a shift amount, and converts the shifted data (for example, "OOO...0011 1.
...11100...oo''> is output to the AND gate 54. Only hits that are "'1" in the output of the circuit 52 are supplied to the arithmetic circuit 62 through the output of the performance type setting register 53 in the form of an arithmetic effective bit 850.

In step 4, the destination image data DAb written at a predetermined address in the display memory 20A is
It is read out to the arithmetic circuit 62 via the display bus.

Based on the calculation valid hit S50, the calculation circuit 62 calculates only the calculation valid bit between the transfer source valid bit 361 and the transfer destination image data DAb. The destination image data DAC, which is the performance result, is occupied by the destination address l\ of the display memory 2OA. The transferred destination image data DAC is selected by the selectors 30A to 32A, outputted to the display 33 in the form of a red signal R, a green signal @G, and a blue signal B, and displayed on the display 33.

This embodiment has the following advantages.

First register 41 that stores brain board failure data 341
Since the second and third registers 42 and 43 are provided to store the transfer destination plane start position data 342 and the transfer source plane star 1 position data S43, respectively, multiple screens can be displayed on the same address as shown in FIG. Since it is possible to have a memory configuration in which DA exists, any image data DA
When accessing 21, DA22, D△23..., is it possible to access any image data with the same address without changing the memory address, origin ORG@MIT? can. Data can also be transferred between any number of screens. Therefore,
You can speed up access to multi-window screens. In addition to roughly multi-window display, for example, even when displaying a dynamic screen on a static screen, the access time can be increased in the same way as described above.

Note that the present invention is not limited to the illustrated embodiment, and for example, the circuit configuration within the image processing device 10Δ including the effective bit generation circuit 50 may be configured using a circuit according to the present invention.

(Effects of the Invention) As described in detail above, according to the present invention, a control circuit having a plurality of registers and an image calculation circuit that operates on the contents of the registers to transfer data to a display memory are provided. This allows you to access multiple screens simultaneously or individually using the same address. Also,
You can also transfer data between any number of screens. When accessing any screen, you can access any screen in the same way without rewriting the origin, which can be expected to speed up access times for multi-window displays, etc.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of an image processing device system having an image processing device according to an embodiment of the present invention, FIG. 2 is a schematic configuration diagram of a conventional image processing device system, and FIG. 3 is a display diagram in FIG. 2. 4 is a diagram showing an example of the memory configuration of FIG. 3, FIG. 5 is a diagram showing an example of the configuration of FIG. 1, and FIG. 6 is a diagram of the display memory configuration of FIG. 1. A diagram showing an example, FIG. 7 is an explanatory diagram of the operation of FIG. 1. 1...CPU, 10A...Image processing device, 11△...Control circuit, 12△...
Image itch circuit, 20A...Display memory, 30A-32A...Selector, 33...
...Display, 41.42.43...1st
, second and third registers, 50... operation valid bit]/generation circuit, 60... subtractor, 61...
...Shift circuit, 62... Arithmetic circuit.

Claims (1)

[Scope of Claims] An image processing device that inputs a command related to image processing, reads predetermined image data from a display memory, performs arithmetic processing, and then writes the result of the arithmetic operation to the display memory, comprising: a transfer source of the display memory; Transfer source plane start position data indicating the plane start position of the transfer destination, transfer destination plane start position data indicating the transfer destination plane start position of the display memory, and plane number data indicating the number of planes of the display memory. a control circuit having a plurality of registers for outputting the data in the image data access mode, and generating an operation valid bit and a transfer destination valid bit based on the transfer source plane start position data, the transfer destination plane suit position data, and the plane number data. , and an image calculation circuit that calculates specific bits of these valid bits to transfer data from a transfer source address to a transfer destination address in the display memory.