JPH07296176A - Polygon paint-out information output system - Google Patents

Abstract

PURPOSE:To enable several-times high-speed access to write in a horizontal one-dimensional arrangement form according to a method not to write a gap between two points on a horizontal axis or bit sequences painted out by a bit map into an image memory as they are but to temporarily store then in the memory of two-dimensional structure and to write them later in the image memory in a two-dimensional arrangement form when painting out a polygon. CONSTITUTION:Horizontal axis coordinate values x0 and x1 crossing an outline on the same scanning line calculated by two straight line generators 5a and 5b pass through address decoders 6a and 6b and generate bit patterns provided with mark and space bits at a pattern generator 7 later. These bit patterns are written through a multiplexer 8 to a memory module 4 provided with two-dimensional arranging structure. The read from the memory module is performed through the multiplexer by two-dimensional arrangement.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to high speed transfer of polygon fill data in computer graphic processing.

[0002]

2. Description of the Related Art Generally, in polygon filling processing, as represented by a scanline algorithm, the points at which the polygon outline intersects the horizontal axis are obtained, the areas between the intersections are filled horizontally, and then the The method of sequentially testing in the direction and filling the whole is adopted. When performing this horizontal filling, there are two methods: a method of filling a space between two points with a straight line generator and a bitmap processing by logical operation.
There is a street. When a fill pattern is generated in any of these, writing in the horizontal direction (one-dimensional array) is performed in the image memory.

[0003]

With the progress of circuit elements, high-speed polyhedron filling processing has become possible up to about 1 million planes per second, but the problem is that when writing filling data to the image memory, it is possible to access at once. If the number of bits that can be created is in units of horizontal words, 10 × 10
The writing operation to the image memory 10 times is required for a polygon having a dot area. Considering that dynamic RAM is used as the image memory, this polygon takes more than 2 microseconds to complete writing. As a result, less than 500,000 planes are written per second. Therefore, writing to the image memory is an obstacle to speedup, and high-speed transfer is required.

[0004]

In order to solve the above-mentioned problems, the present invention first stores fill data temporarily in a high-speed storage element (cache memory),
In this storage, the structure of the cache memory corresponds to an arbitrary n-bit on the horizontal axis to the output terminal of the memory, and a plurality of memories are prepared, and the number corresponds to an arbitrary number m of lines on the vertical axis. Thus, while the n × m bit one-dimensional array data is written, the n × m two-dimensional array data can be read at a time from the entire capacity. Image memory with multiple bit block transfer
A system interfaced by a processor can write and read two-dimensional array data and utilizes this mode to handle the n.times.m data format. In addition, when n × m is set as one block in the total capacity and a write is performed in this block, a flag is set for each block. When all the writing is finished and this is transferred to the image memory, the flag is first tested, and only the flagged block is transferred.

[0005]

With the structure as described above, high speed processing which is about three times as high as that of the horizontal writing method can be performed. Generally, a polyhedron fill is decomposed into minute faces in order to express the highlight effect smoothly or continuously, and at the filling stage, the size of one polygon is 20 to 30.
It is about a dot angle. Therefore, the capacity of the cache buffer is also reduced, and it is possible to incorporate a memory in the LSI.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A practical example of the present invention will be described below with reference to the drawings. FIG. 1 shows a two-dimensional space 1 of a memory for storing polygons according to the present invention and 16 divided areas 2
It is a figure which shows (henceforth a block). In the figure,
Polygon 3 spans multiple blocks (8) in memory. One block can be written to the image memory with one access. Therefore, in the figure, the polygon 3 is stored in the memory by the writing process eight times out of the 16 blocks. When this is decomposed in the horizontal direction and written, if the number of vertical lines in the block is eight, access is required about 32 times. As is clear from the figure, when transferring two-dimensional data, it is natural that the block transfer decomposed into the two-dimensional space is faster than the one-dimensional array transfer. FIG. 2 shows the structure of the memory according to the present invention. The input / output terminals of each of the memory elements 4a to 4d included in the memory 4 are equal to the number of bits in the horizontal direction of the block. The number of memories is equal to the number of vertical lines in the block. For example, when the number of bits in the horizontal direction is n and the number of vertical lines is m, the memory is composed of m elements each having n input / output terminals. In the figure, n = 8,
It is assumed that m = 4 and there are four memory modules 4a to 4d having 8-bit I / 0 terminals. The memory address is given the horizontal and vertical axis coordinate values that are obtained when calculating the intersection of the outlines. Each lower address becomes an address within the block, and the upper address indicates the block number. In FIG. 1 where n = 8 and m = 4, the horizontal and vertical axes each have an area of 32 dots × 16 lines, and one block is composed of 8 dots × 4 lines. FIG. 3 shows an overall view of the filling circuit of the present invention. In FIG. 3, 5a and 5b are straight line generators, which divide a region from one vertex of an outline of a filled polygon into left and right sides, and generate two straight line vertex coordinate values included in each region. It is given to a vessel and moves in parallel at the same time. In the case of a triangle, each of the straight lines in two directions from one vertex is loaded into 5a and 5b, and when one of the straight lines ends, the remaining one straight line is loaded into the straight line generator and the vertices are matched again. Step forward. The straight line generator comprises a DDA that advances the horizontal axis until the vertical axis counts up by one, and when one vertical axis counts up, holds the horizontal axis counter until the other vertical axis counter counts up. By doing so, the horizontal axis coordinate values in which the vertical axis coordinate values of the two DDAs are equal to each other are obtained. This is nothing but the horizontal axis coordinate value that intersects the outline on the same scan line at two points. In this way, the x ₀ , x ₁ coordinate values obtained in 5a and 5b are obtained from the address decoders 6a and 6b.
After passing through, the pattern generator 7 generates a bit pattern having mark and space bits. The pattern generator is a generator that fills in two bit points and mark bit "1", and fills the other with space bit "0", and is composed of a circuit centered on a priority encoder. . In the case of the embodiment comprising the memory of FIG. 2, the pattern output from 7 is 32 bits,
The area surrounded by x ₀ and x ₁ is “1”, and the outside (the left side of x ₀ and the right side of x ₁ ) is “0”. The 32 bits output from the pattern generator 7 are connected to the input / output terminals through the respective multiplexers 8 at the inputs of the four memory modules 4a to 4d constituting the memory 4 of FIG. It is written in the memory 4 every time the axis advances. On the other hand, the memory is not read as a one-dimensional array pattern on the horizontal axis at the time of writing, but must be read as a two-dimensional array pattern. For this purpose, array conversion processing is required at the time of storing the one-dimensional array pattern in the memory 4 from the pattern generator. FIG. 4 shows this relationship. 1 separated by alphabet in the figure
One block is an array in which the horizontal and vertical axes are composed of 8 bits × 1 line. Further, the 32-bit pattern generated by the pattern generator 7 has four byte arrays a ₀ , a ₁ , when the lower 2 bits of the vertical axis address are 0.
a ₂ , a ₃ , and when 1, b ₀ , b ₁ , b ₂ , b
_{When 3} , 2, c ₀ , c ₁ , c ₂ , c ₃ , when d 3, d ₀ ,
Let d ₁ , d ₂ , and d ₃ . In this case, in the memory modules 4a to 4d of FIG. 2, the respective patterns shown in FIG. 4 are distributed in 8-bit units to the respective memories 4a to 4d shown in the upper column of the figure. This allocation is performed by the multiplexer of FIG. 3 according to the lower bits of the vertical address. The horizontal 32-bit pattern is divided into 8-bit patterns, the arrangement is changed as shown in FIG. 4, and then the data is written in the memory 4, so that the blocks shown in FIG. 1 can be read out as a ₀ , b ₀ , c ₀ , d ₀
Alternatively, a ₁ , b ₁ , c ₁ , d _{1 and the} like can be read in parallel by a similar method. Read sequence the two dimensions can be read by providing a signal determined by x _3, x ₄ bits of the horizontal axis address as part of the address of each memory module. Also, in order to always output the lowest row of the two-dimensional array as the left end, block numbers or horizontal axis addresses x ₃ , x ₄
A signal determined by the bits can be given to the multiplexer 9 to be rearranged. As described above, it is possible to temporarily store the one-dimensional array pattern on the horizontal axis in the memory by the address control and the multiplexer and then read it as the two-dimensional array pattern in the same memory bus structure. Further, when setting a filled bit in a block, the block number (address) is stored in the memory 10 having a capacity corresponding to the number of blocks in the accessed block, and the flag is set. Memory 1
When the address of 0 is associated with the block number, a memory having a capacity of 1 bit / block for setting only a flag may be used. When the read mode is entered and the data is read from the memory 4, the contents of the memory 10 are first read, and only the block number of which the flag is set is read. The address given to the image memory is the sum of the address preset for positioning the polygon at the absolute coordinates on the image memory and the address of the block number.

[0007]

As described above, when painting is performed, a bit string filled between two points on the horizontal axis or by a bit map is not stored in the image memory as it is, but once stored in a memory having a two-dimensional array structure. After that, the method of storing in the image memory in the two-dimensional array format and then writing in the image memory in the two-dimensional array format enables high-speed access several times as high as writing in the horizontal one-dimensional array format. This makes it possible to obtain dynamic image drawing.

[Brief description of drawings]

FIG. 1 shows a memory space and divided blocks according to an embodiment of the present invention. First

FIG. 2 shows a two-dimensional array memory structure.

FIG. 3 is an overall circuit block diagram of the present invention, and FIG. 4 shows data array conversion. 1: memory space 2: divided block 3: polygon 4a-4d: memory module 5a, 5b: straight line generator 6a, 6b: address decoder 7: pattern generator 8: input multiplexer 9: output multiplexer 10: flag memory

Claims (1)

[Claims] 1. In a filling method for filling a space between two points where a polygonal contour line intersects a horizontal axis, a storage element consisting of bits corresponding to the area of a quadrangle surrounding the polygon is provided, and the area of the quadrangle is arbitrary. The number of outputs corresponding to the horizontal axis and the vertical axis of the divided area are set in order to provide a memory circuit with input / output signals equal to the number of all bits included in the divided area. The memory element is composed of a number of memory cells, and a fill pattern consisting of a one-dimensional array is stored in this memory circuit. When the fill process is completed, two-dimensional array data equal to the number of bits of the divided area is once stored from this memory circuit. The first means for outputting to and the process of filling between two points on the horizontal axis, divide the divided area into blocks and write to that block. If there is, a polygon-filling information having a second means for providing a storage element for setting a write flag, determining the presence or absence of this flag at the time of output, and outputting only the two-dimensional array data of the block having the flag Output method.