JPH0581940B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention can reduce the number of memory modules and access any image point group or sub-array in the row or column direction with the same memory access time. The present invention relates to an image data memory system.

Data handled by an information processing device includes image data. In processing this type of data, image data is stored in memory as an image array, which can be thought of as a two-dimensional array of image points consisting of an integer, and a sequence of image points in a single row or column in the array. , such as a group of image points in a small rectangle (subarray),
It may be necessary to apply processing to selected image point clouds simultaneously.

In such processing as well, it is desirable to be able to process image data at high speed and with a small amount of hardware.

[Conventional technology]

Examples of the above-mentioned processing include displaying and printing image data, and in such cases it is generally necessary to read out image points at high speed in the scanning direction. For this reason, image memories are generally organized in words to increase speed by reading out multiple image points at once.

This word organization of the image memory is satisfactory as long as the scanning direction for display and printing is constant (line direction); The frequency of output is also quite large.
In that case, the scanning direction must be vertical. However, conventional word-organized memories do not allow simultaneous access to consecutive image points in the vertical direction. Therefore, conventionally, all image data is rearranged using a central processing unit to obtain the necessary vertical data. Due to the large amount of data, the load on the central processing unit increases.

Furthermore, in order to be able to perform block insertion and extraction processing such as insertion and extraction of character data into image data, it is required to be able to access rectangular blocks (subarrays) of image points at high speed. Ru.

Techniques have also been developed to perform such continuous data access in the row or column direction or submatrix access. The first method shifts the allocation to memory modules by one each time the column changes, and the second method performs memory module allocation and address allocation of image points according to specific rules. It is. FIG. 4 is a diagram of the system configuration.

In Fig. 4, the image memory is divided into n memory modules a ₁ , a ₂ , ...a _o , and address signals are sent from the memory access control device b to these memory modules to output output from these memory modules. The n bits sent are sent as they are to the central processing unit c, or are parallel-to-serial converted by a multiplexer d and sent to a printer e and a display f. The fifth example shows an example in which the allocation to memory modules in this system is shifted by one each time the column changes.
It is a diagram. 5-1 in this figure is image data 2
represents a portion of a dimensional array, each cell of which
One image point is shown. The number in each box indicates the number of the memory module to be allocated. That is, image points written with the same number are stored at different addresses of the same module. 5-2 in FIG. 5 shows the allocation of addresses to each image point.

By doing this, by specifying the address "0" to all memory modules, the 8 bits from the left of the most significant row can be read out from the memory at the same time. Also, address “0” to memory module 0, address “1” to memory module 1, etc.
By designating address "7" to the memory module 7, 8 bits from the top of the leftmost column can be read out at the same time.

FIG. 6 shows an example of memory module allocation and address allocation of image points according to specific rules. The allocation rule is that if the number of image points in the row direction of the image data is P, and the number of image points that can be accessed simultaneously is ⁿ² , then the module number M _ij and address for the image point I _ij in the i row and j column.
A _ij can be expressed as M _ij =n ² [(j/n)2] + (jn+i+j/2n)n ² A _ij =(j/2n)·P/n+(i/n). However, / and represent the quotient and remainder of an integer, respectively. ) 6-1 in FIG. 6 represents the allocation of image points to memory modules, and 6-2 in FIG. 6 represents the allocation of addresses. In this example, there are 32 memory modules, a 4x4 image subarray,
The image points in the 1×16 row-direction continuous image point group and the 16×1 column-direction image point group are prevented from being allocated to the same memory module, so that they can be accessed simultaneously.

[Problem that the invention seeks to solve]

As is clear from the above, according to the first method, it is possible to simultaneously read out consecutive image points in n arbitrary rows or columns from n memory modules. There is a problem that you cannot access . The second method solves this problem, but it requires 2n ² memory modules to access n ² image points simultaneously, and the memory address control becomes complicated. I end up.

[Means for solving problems]

The present invention provides an image data memory system capable of solving the above-mentioned problems, and the present invention provides an image data memory system that stores two-dimensional image data in units of image points. is the maximum number of rows of a submatrix that can be accessed simultaneously, n is the maximum number of columns of a submatrix that can be accessed simultaneously, t is an integer that specifies the number of rows of 2D image data, and s specifies the number of columns of 2D image data t as a parameter
A memory device comprising (mn+1) memory modules in which only one storage cell is accessed at a time for storing two-dimensional image data in (mn+1) rows and s(mn+1) columns, and two-dimensional image data. The image point I _ij determined by row i and column j within is surrounded as the writing start image point, and I _j 〓〓. _j+o 〓 and I _i+n 〓． _j± 〓(However, the signs are in the same order,
Let θ and φ be arbitrary natural numbers within the allocatable range. ) image point data supply means for supplying each image point in any one of the image point groups represented by the image point group to a memory module M _ij ; and a write address _{A ij} to the memory module M ij.
=j/(mn+1)±si and A _ij =j/(mn+1)±
write address supply means for supplying any address A _ij of ti to the memory module M _ij ; a read start image point (i, j) and the number of rows α and the number of columns β from the read start image point; is received, and read addresses A _ij to A i+ 〓, A j+ determined from the address calculation formula used for writing to memory cells M _ij to M _i+ 〓, _{j +} 〓 within the range determined by the number of rows α and the number of _{columns β.} read address supply means for supplying 〓 to the memory cells M _ij to M _i+ 〓, _j+ 〓; and receiving the read start image point (i, j) and the number of rows α and the number of columns β from the read start image point. and image point data output means for outputting image point data read from the memory cells M _ij to M _i+ 〓, _j+ 〓.

[Effect]

According to the system of the present invention, an arbitrary image point I ij of two-dimensional image data of t (mn+1) rows and s (mn+1) columns with m, n, t, and s of (mn+1) memory modules as parameters _. The image points I _I 〓〓, _j+o 〓 and I _i+n 〓, _j± 〓 are assigned to the memory module M _ij to which θ and φ can be assigned. ) and assign addresses to these image points.
A _ij =j/(mn+1)±si and A _ij =i/(mn+
1) Since the image points are accessed by giving ±tj, any one row γ
Image points in consecutive rows or columns of columns or γ rows and 1 column (γ≦mn+1), or α rows and β columns (2
The image points in the submatrix of ≦α≦m, 2≦β≦n can be accessed simultaneously by one access.

〔Example〕

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows an embodiment of the invention. In this figure, 1 is a central processing unit (hereinafter abbreviated as CPU), which is connected via a data bus 2 to a write data selector 3, a read data selector 4,
It is also connected to the peripheral control circuit 5. Reference numeral 6 denotes a control line, through which control signals i,
j; α and β are supplied from the CPU 1 or the peripheral control circuit 5 to the write data selector 3, read data selector 4, and address generation circuit 7. Outputs 7 ₁ , 7 ₂ ,... of the address generation circuit 7
7 _no+1 is connected to memory modules 8 ₁ , 8 ₂ , . . . 8 _no+1 . These memory modules are 1
Sometimes one memory cell is accessed. Each of the memory modules is connected to the output lines 9 ₁ , 9 ₂ , ...9 _no+1 of the corresponding write data selector 3, and the read output lines 10 ₁ , 10 of each memory module
₂ , . . . 10 _no+1 are connected to the read data selector 4.

A CRT display device 11, a printer 12, etc. are connected to the peripheral control circuit 5.

Next, the operation of the above-described configuration will be explained.

t of (mn+1) memory modules in this system, where m, n, t, and s are parameters.
Image point I _i 〓〓〓 _{, j+o} 〓 I _{i +n} 〓, _j± 〓 ...(1) (However, in the above formula, the signs are in the same order, and θ and φ are arbitrary natural numbers within the assignable range.), and address A _ij = j to these image points. /(mn+1)±si A _ij =j/(mn+1)±tj ...(2) (However, / in the above equation is the integer part of the quotient.) Access each memory module. In particular, there is a characteristic feature of the present invention.

As a specific example of access, let m = 3, n = 4, and the image points allocated to the same memory module are I _ij I _i+ 〓, _j+4 〓 I _i+3 〓, _j- 〓 ...(3) , M _ij are arranged in ascending order in the j direction, and the address A _ij of I _ij is set as A _ij =j/13+2i (4). The operation of the system shown in FIG. 1 will be explained.

Parameters i, j; α, β are supplied from the CPU 1 or peripheral control circuit 5 to the address generation circuit 7, write data selector 3, and read data selector 4 via a control line 6. Here, i, j represent the coordinates (row i, column j) of the upper left image point of the subarray in the image data you want to access, and α, β
represents the number of rows and columns.

In the address generation circuit 7, the received i,
j; From α and β, the address of each image point in the α row and β column that is accessed according to equation (4) is calculated, and the addresses are supplied to each memory module.

When the system is in write mode, the write data selector 3 allocates image point data to each memory module based on equation (3), and the image point data allocated to each memory module is assigned to an address. It is specified by the address supplied from the generation circuit 7 to each memory module and written into the memory cell.

Furthermore, when the system is in the read mode, image point data is read from the memory cell specified by the address supplied from the address generation circuit 7 to each memory module, and the output from each memory module is read out. The data are selected and rearranged by the data register 4, that is, subjected to the above-mentioned allocation restoration process, and then output to the data bus 2. The data bus 2 signal is the CRT display device 1.
1 and/or printer 12.

FIGS. 2 and 3 show the allocation of image point data and address allocation of image points for writing image point data into such a memory module. As is clear from these figures, arbitrary 1st row, 13th column, 13th row, 1st column, 3rd row, 4th column, 3
Row 3, row 3, column 2, row 2, column 4, row 2, column 3, row 2
The partial image points (subarrays) of a column can all be allocated to different memory modules, and these partial image points can be accessed in one memory cycle. For example, to access partial image points in rows 3 and 4 and columns 7, 8, and 9 in FIG. 2, i=3, j=7,
The data of α=2, β=3 is sent to the address generation circuit 7,
By supplying the data to the write data selector 3 and the read data selector 4, the partial image point can be written or read.

Furthermore, the memory module M _ij to which the image point I _ij is allocated may be M _ij =(j+in)(mn+1) or M _ij =(j-in)(mn+1). However, in the above formula, represents the remainder.

Furthermore, I _ij I _i- 〓, _j+o 〓 I _i+n 〓, _j+ 〓 are allocated to the same memory module M _ij , and
By arranging M _ij in ascending order in the j direction, it is also possible to set M _ij =(j+in)〓(mn+1).

Also, Mo _j can be arranged in any way as long as the memory modules are all different from 0 row, 0 column to 0 row, mn column (mn+1)! There is a combination of

Also, by arranging M _ij in descending order in the j direction, it is also possible to set M _ij = (in-j) (mn+1) M _ij = (-j-in) (mn+1), and then arrange M _ij in the i direction. They may be arranged in ascending/descending order.

〔Effect of the invention〕

As described above, according to the present invention, by using (mn+1) modules, (mn+1) rows and 1 column, 1 row and (mn+1)
It is possible to simultaneously access any image point in a submatrix of columns, m rows and n columns, and to perform high-speed image data transfer.The number of memory modules is approximately half that of conventional methods, and address calculation and memory This simplifies module allocation, reduces hardware requirements, and so on.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of assignment of image points to memory modules, FIG. 3 is a diagram showing an example of address assignment of image points, and FIG. 4 is a diagram showing an example of address assignment of image points. 5-1 and 5 in FIG. 5, a diagram showing an example of the configuration of a conventional image data memory system.
-2 is a diagram showing an example of assignment of image points to memory modules and address assignment of image points according to one conventional method, 6-1 and 6- of FIG.
2 is a diagram showing an example of allocating image points to memory modules and allocating addresses of image points according to another conventional method. In the figure, 1 is the CPU, 2 is a data bus, 3 is a write data bus, 4 is a read data bus, 5 is a peripheral control circuit, 6 is a control line, 7 is an address generation circuit, 8 ₁ , 8 ₂ ,...8 _{no +1} is memory module, 1
1 is a CRT display device, and 12 is a printer.

Claims (1)

[Claims] 1. In a memory system that stores two-dimensional image data in units of image points, m, n, t, s (m is the maximum number of rows of a submatrix that can be accessed simultaneously, n is a part that can be accessed simultaneously) The maximum number of columns in the matrix, t is an integer that specifies the number of rows of two-dimensional image data, and s is an integer that specifies the number of columns of two-dimensional image data) is used as a parameter.
A memory device comprising (mn+1) memory modules in which only one storage cell is accessed at a time for storing two-dimensional image data in (mn+1) rows and s(mn+1) columns, and two-dimensional image data. The image point I _ij determined by row i and column j within is surrounded as the writing start image point, and I _j 〓〓. _j+o 〓 and I _i+n 〓． _j± 〓(However, the signs are in the same order,
Let θ and φ be arbitrary natural numbers within the allocatable range. ) image point data supply means for supplying each image point in any one of the image point groups represented by the image point group to a memory module M _ij ; and a write address _{A ij} to the memory module M ij.
=j/(mn+1)±si and A _ij =j/(mn+1)±
write address supply means for supplying any address A _ij of ti to the memory module M _ij ; a read start image point (i, j) and the number of rows α and the number of columns β from the read start image point; is received, and read addresses A _ij to A i+ 〓, A j+ determined from the address calculation formula used for writing to memory cells M _ij to M _i+ 〓, _{j +} 〓 within the range determined by the number of rows α and the number of _{columns β.} read address supply means for supplying 〓 to the memory cells M _ij to M _i+ 〓, _j+ 〓; and receiving the read start image point (i, j) and the number of rows α and the number of columns β from the read start image point. and image point data output means for outputting image point data read from the memory cells M _ij to M _i+ 〓, _j+ 〓.