JPS59154488A - Memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Section of the Invention] The present invention relates to the memory of a computer system, and the present invention relates to the memory of a computer system. (- also used, t memory configuration Q
Regarding U.

[Prior art]

In the computer industry, there are 41, 11, 11, 100,000 pieces of information in the computer industry, that is, there are necks A-C that use images to provide information to users and scold them. This image (・yo, letters and numbers.

Graphs such as 1L1 sentence graphs, and other forms such as the upper part of the graph are often used. In many cases, 4-digital images (
=11, e.g. video monitor, printer, etc.ft
t((' is displayed to the user. In theory, in image manipulation, a quadratic array of bits is represented. The membership fee is the ability to perform parallel operations in memory.Therefore, 1. Select the 11 peaks in the memory ``I''Lk cluster ``yJ: ζ- accessed within 1 memory resource.
and Bonen-noh (become what your heart says) 3゜Conventional (-1) Generate, store, and manipulate digital images 5
, display / kome (・de] tλ meka or 8 less and 6-8 7 sacrifices) the simplest, 〃water, in 2shi? j1. How to allocate a block of memory in the boot process log/sudemun L7. ). System Teke J1 Each memory bit (1 or 0) corresponding element on the car display system (i
mi tree). Therefore, the statue and/or the form of 17j Akist, the entire data person (page) of 1.
The 1-bit map 1 and 7L are represented as 0 and 1 in the target block of memory. Each bit Mazda has one color or so, so 11 colors + 1 or more multicolor images are shown; ■<6, explore! V (
It can be created in the memory of 1.n Bitmapke Combi Coaters. 1. Beep for image generation and manipulation.
After many bits in the map are changed (history p1) 1.
That's all you need.

Bit map V (=represented DigiMole image 11
The speed at which the computer system can generate and operate (1, 4 configurations) is driven by the access speed of the memory element (1 cycle time - 1), K.

In many cases, each memory element value is represented by a block of display elements forming an adjacent diagonal or other digital image. is represented by a number of pixels whose state (4, 4, 4) is recorded in one of the memory elements representing a portion of the bit map. In applied fields that require chanting!':j:
% Computer System Sword Digital Painting a” (
The speed k ii obtained by updating Table 71 depends on the cycle time of the round element. A memory element such as a dynamic spring access Φ memory (D-RAΔf1) has a cycle time of about 330 nanoseconds.

In the field of high-speed computer graphics applications, it is well known that this level of access time is insufficient.
-C(・)ru4, Therefore, it is possible to process the data for the convenience store by 70%, and for the entire system -1, the pixels of the prisoner's neck. Representative 2) Limited Zagokuru 11 IMJ'l (-therefore, total 7δ) of the Megohiri deposit -jz,.

Approximate summary of ``lJ,
J6J: +iQ image heat, fee (-su town [U',] normal memory element's current time light, borrow (-5 Kuya 1 pass 4
) You (τ, -iI version's size, size (D -RAM1
1-(511 Prize/Upper Computer Crano'I:>ri-dokoro'-11).
Q K-fru improved reading A-mail +11. Provide by-jbe)(, Invention 1 (provisional, digital communication)) DA °7 no 1 Noah multi-face j, Kura ``Chikaraishi-1 noeru 2inhi'Yuta's no 1 niri's tI'L season ν: 'tC11
': i j4). Illusion” 1. In the example, N +i
A computer memory with i↓ next Melori tree E'- is constructed (/L, '- et al, !shi, each binary one:tsuh (o father(, , l: ], ) +d, table>j<'Au'swork; k is mapped to an element (pixel).Display device: all pixels to be defined are 0, F bit map; The pixels are arranged in a plurality of water scan lines, each pixel being specified by its X and Y coordinates.

The N memory elements of the present invention are different from the two memory elements used to represent the state of each pixel of the display device, adjacent pixels Q' (denoted by Structured as follows:
Expressed in two elements. Furthermore, ? of consecutive vertical (Y) addresses? The memory index number for storing 'f pixels is increased by a predetermined number. By selecting the appropriate number of stones from this table/J:, the art book that constitutes the device ff, the line that crosses the image of the shape of (Ikuno L, (J5 between r- The pixel in the same memory element is set to [enable]L or set to "j" power, and set to A.
-9: It can be represented in a bit map as shown below. This unique feature allows image manipulation and updating to occur faster than the time required for each individual mechanical element. Disclosed is a method and apparatus that enables the use of the ycR, T (cathode) gland, etc. in combination with standard display systems.

[Heavenly Example]

The structure of an improved computer memory that has been applied to a digital computer to provide high speed graphics capabilities is discussed below.In the following description, a thorough understanding of the invention will be provided.

Bits, memory element allocation, addresses, etc. are recorded.

[-It will be appreciated that those skilled in the art will be able to carry out the present invention even without the detailed description of these specific numbers, etc.]
It is clearly 〃・. Other embodiments are shown using block diagrams of well-known circuits and elements in order to avoid making the present invention unnecessarily unclear. .

Hereinafter, a complete explanation of misfire + pH will be explained with reference to the accompanying drawings.

FIG. 1 shows a computer system that generates a quadruple digital image in accordance with the present invention. The system processor 10 (in the current preferred embodiment, an 8086-based and 16-bit microprocessor) performs various utility functions, including managing the overall system. Go big. Furthermore, the system processor 10frI1,
Performs overall system timing and necessary interfaces with the host computer and other computers. System processor 10, main bus 12
connected to other modules of the computer system through. Vector memo IJ 14 I': t, connected to the main bus 12, generates all graphics (7 υ images, moves 1. - The vector memory 14 contains x -y U sl-(rat, which describes various images that should be generated and displayed by the system processor 1 in order to change the graphics display.
Can be updated via 0. The display generator 16 is connected to the main bus 12 and converts the X-Y end point data in the vector memory 14 into a series of X-Y pixel coordinates that approximate the line locus defined by the vector end point.

The X-Y coordinates corresponding to a particular plurality of pixels defining an image are transmitted via a C1 pixel bus 17 to a high speed pixel memory 18. Stored in vector memory 1411. The /ζ digital image produced by display generator 16 based on vector endpoint coordinates typically consists of several hundred discrete lines. The user, through the system processor 10, can update and modify the generated digital image stored in the high speed pixel memory 18 by identifying new vector endpoints corresponding to the desired image. Vector memory 14*
Through all the endpoints stored in the second fast pixel memory 19, as each cycle is completed, the contents of the fast pixel memory 18 are transferred via the local copy bus 20 to the second fast pixel memory 19. Video output module 22 accesses the digital images stored in pixel memory 19 via a video bus 24;

The video output module 22 includes a cathode ray tube (CRT) 2
6. Display the digital image on another suitable display means, such as a printer or plotter. As will be appreciated from the following description, the unique high speed pixel memory configuration of the present invention is applicable not only to the system shown in FIG. 1, but also to other computer graphics systems.

In my case, I used high-speed pixel memo IJ 18, 19 (hydraulic), commercially available 64. K dynamic f9 A
M”s) formed using 024
1 f-) consists of a 24 x 4-array.

As explained below, the existing 64K da 1 namic RAM technology
'', in about 3:30 nanoseconds, or the present invention (1, about 83 nanoseconds, in 1 bit speed L).Arm memory operation for digital image processing : 'j'c
do. In the present invention, each pixel (or C' or other display element) is encoded by 4 bits, K,\'×,1''.
Each of the memory planes VC1 corresponding to the tegonition t
Uses 6 dynamic RAMs. Each of the four memory planes is associated with a color of 1%, -., and only 16 color combinations are possible.

For simplicity, the structure and operation of only one memory plane within the 1.6 speed pixel memory 19 will be described herein.
4X 1024×1 This is an explanation regarding the pitch I/plane. Factors such as bus capacity and binary word length are reduced accordingly)1. 1, while the present invention can be implemented using a multilayered pitch plane, i), i
5 i+=, I-clear; 01]1. History V・=,
The high speed 1111 memory is represented in the device consisting of the memory 19.
The explanation for "one pixel per 1" is that -11 to the corresponding binary value (1 or 0),
Akira and J No 1! Solution 7 Zasai L/ζ.

Figure 2 (/shown/In this way, the individual Q and purple that make up the manpower, j, JI + ¥, also use the X-Y coordinates -C 3 (
- or something like that). Ita 112-ba, 1σ) 1 system (0,0
) is a concave j element of 111·1 on the left side of the display iMi surface/). 1 [Pixel C], 024, 0) originates from the pixel T'' on the right side of the lower blade of both jY+i. High-speed pixel memory 1
The 16 memory elements (0, element #0 to #p (decimal notation -) consisting of 9 elements are specified as (/(
As stated above, the memory elements of li, il- are accessed for adjacent pixels, and image generation and display is limited by the time of the memory elements.The memory structure of the present invention . . . does not enable pixels represented within the same element within the cycle time of any vector or element that creates an arbitrary ++ji image.

As shown in FIG. 2, the state of the pixel having coordinates (0,0)' is stored in memory element #O.

Similarly, the state of the pixel at the coordinates (1, 0) is stored in memory node #1, and the subsequent painting operation is performed, for example, at the coordinates (15, 0).
) The state of the pixel having i is represented in memory element #F and stored sequentially in the memory element. As shown, the pixel with coordinates (16,0) is again stored in memory element f#().

It can be seen that the vector drawn from coordinates (0,0) to coordinates (16,0) accesses element #0 only once within 16 cycles. However, for vectors in directions other than horizontal, the simple succession of sequential lateral/memory element patterns described above does not guarantee that a particular memory element will not be accessed faster than its cycle time.

As shown in FIGS. 2 and 5(a), in accordance with the present invention, pixels having different vertical Y addresses in a memory device are numerically "offset" from the memory device representing all adjacent rows of pixels. ” has been.

For example, in the memory configuration of the present invention disclosed herein,
Using 4 as the offset number, 4 consecutive pixels are stored in 4 different memory indexes. In other words, the state of the drawing with coordinates (0, 0) is memory element #
0, but the state of the pixel with coordinates (0,1)k is stored in memory element #4. Similarly, the coordinate (0+
2) The state of the pixel with 'c is stored in element #8, and the state of all pixels with coordinates (0,:3) (the memory element #C
(in decimal notation, element 12). It is clear from Figure 2 that in the best case, the water and K lines are accessed only once per 16 pixels per pixel.

By the way, the vertical edge corresponds to the worst case where the same pixel is accessed every fourth cycle. 10
For a 24 to 1024 pixel bitmap, any offset number other than 4 or ]2 does not result in a memory configuration that allows all 64 K dynamic RAM to be used at a continuous apparent rate of four times its cycle time. It has been found that Any even number (2, 4
, 6, etc.), it is possible to achieve an access speed that is twice the cycle time.

The present invention uses a repeating NXM memory element pattern to
Map onto the pixel of RT26. In the embodiment of Figures 2 and 5(e), the pattern is 65. This array is repeated symmetrically to produce a complete bitmap representing each pixel of the display. The 16x4 pattern of the present invention, such as 7D\, in which the number of repetitions of the NxM pattern simply changes depending on the number of pixels, is suitable for CRT2.
(independent of the number of pixels used for 6). Therefore,
The cycle time Q of memory elements #0 to #N is not affected by the size of the memory 18, and the same memory element is cycled every 4 pixels (
'This is just a VC that can be accessed once. (34 ni da〈
Although the present invention has been fully described in connection with a Namic RAM and a fixed number (1024) of pixels, the present invention concept of offsetting memory elements corresponding to pixels in adjacent rows (1. Displays and memory systems of various sizes) Applicable to

As shown in FIG. 1, the high-speed pixel memory 19 is
9 is connected to the video output module 22 via the video bus 24 for display on the CCRT 26. According to the memory configuration of the present invention, one of all memory elements (O to F) in the bitmap is connected to the video output module 22 for display on the CCRT 26. By accessing the next address simultaneously, the high speed pixel memory 19 can be output.

As shown in Figure 4, the dynamic 1NAM+, which consists of 19 high-speed art collections, is a single row (1eOW).
address and its corresponding row address 1 +3 (RA
S) or the scan line occurs when the column (COL')
Addresses and their corresponding address numbers (CAS) are each 16-bit word (with 2 and 4 bits).
It is possible to operate in [page mode]. Therefore, row (■guy) 8 people') ' + column (COL
The states of pixels UMN'S)] to ]6 are read simultaneously from address 0 of the 16 dynamic RAMs. Kov-) Ql: Out, &-j2, generally 160
It takes only nanoseconds, or allows an output speed of about 10 nanoseconds per pixel. Therefore, the architecture of the present invention allows simultaneous high-speed extraction and display of the states of successive pixel bits in blocks of 16 columns in each row. In fact, it has been shown that this apparent access [fHLl] of the 7-1 card operation is limited by the scanning speed Q'ζ of the CRT 26.5Referring to FIG. Because of the memory configuration of seconds (
・The predetermined 16-bit word header 5° (1 deg.
ntification ) B the word (7-) 41
It can be seen that j + M (Y) changes depending on the address (
For example, iIr, (,) ends with (,), h) vertical address field a), ji%I'J U) l 6 Hilar word or state of pixels 0 to 15 including (-7, second] The 6-bit word is f,' for pixels 16 to 31: 7ai
'JJ, including) 5. Simplify the circuit basis of the high-speed pixel memory 19.
Sections 32, 34, 36, and 38 in the figure;
"L-f", each of the four adjacent pixels (i.e. 0~
; 3, 4 to 7, etc.) - Divided into one section. The data input route 40 (I-left-1 manual route 40) and the 84 (D
Data output path 42 (1-left 1 output path 42) K-
share. Similarly, the memory sections 36.38 share a common manpower path 44 ([Right-1 Manpower Path 44) and a common output path 46 ([Right-!Output Path 46) all 11
As shown in FIG. 7, section 32 includes memory elements #0 to
#3, and section 34 includes metal elements #8 to #B
Full inclusion L, section 36 is memory element 'f-#4 to #7
蓓・include, sexy:con 38 is memory element x C-#
It has a structure that includes "F".

Memory 19 tie bang and $11 wander! I II, each memory 18 of memory 18 via mink bus 62
N (teneri P issued ta 4 mink: 10i!I control means 60
V(, i: One suitable pixel address is assigned to address line 66 and read address line 67.
l to the pixel storage location of the sum by supplying it:
%tt insertion operation and bladder expulsion operation are performed.

The entire graphic image to be displayed on a CRT 24, etc., is displayed on a 20-bit parallel bus (1024x:
The display generator 16 is connected to the high speed pixel memory 1 via a 1024x1 pixel bus 17 (in the 1024x1 example).
Transferred to 8. When the scanning of the data in vector memory 14 is completed, the contents of pixel memory 18 are transferred to pixel memory 19 via 20 copy buses. The 16-bit data word originating from pixel memory 18 is
The 8-bit copy bus 21 must be multiplexed two-to-one. The address of each tip state to be stored is supplied to the timing control means 60 on a write address line 66. The data on write address lines 66 includes Y pixel addresses, X word addresses, and memory element index numbers (#0-#F'). Timing control means 6
0 provides a signal on timing bus 62 so that the memory element is accessed as a function of the Y-bit address of the pixel with Bfj as shown in FIG. 5(b).

As shown in FIG. 5(b), the pixel memory 18 supplies the pixel location Q address and the pixel status to the full pixel memory 19 via a copy bus 20.

For example, a pixel (pixel (
0, 0) to (1023, 0), etc.), the pixel memory 18 first updates (at time t = O) memory elements #0 to *3 (c , the pixel memory 1B accesses the memory elements f#4 to #7 of the memory section 36 through the manned pixel 44. At time t-1, the pixel memory 1B
0e: Right human power bus 44 to memory elements #8 to #B via
The memory element -f4#C~#Fp(, is accessed via the memory element -f4#C~#Fp(,. -The pixel bit states of the pixel memory 18 and CRT 26 are sequentially output according to the scanning line order of the CRT 26 as shown in Figure 2. In operation, the 1 and 4 busses 40 and the "right" input 44 each simply represent four of the eight parallel lines that make up the copy bus 20. , therefore, due to the multiplexing described above, 1 representing the 1611III element
Updating 6 bits [-word-1 requires two cycles of time on the copy bus. This multiplexing, 11, is done solely to reduce interconnections.

FIG. 6 is a schematic block diagram of the video output module 22.
7J<su. Video output module 22I/', f, .
The CRT 26 and other display means V'C receive a table of pixel bit states to be displayed and perform parallel-to-serial conversion on the pixel state data to supply the CRT 26 with video conversion.

In read 2 mode, Y vertical address with subsequent horizontal word address h of timing control means 60
The timing control means 60, which is multiplexed on the output address line 67, connects the timing bus 62 to the appropriate memory element (e.g. memory elements 1, 2, etc.) which stores the number of words to be addressed by the pixel. Shingetsu is generated. In this example, (1 phrase, whole word (i.e. 1024X10
16 bits for 24X1 systems) or temporary VrC is read. As mentioned earlier, the (f) words are organized as shown in FIG. , 36 or 38), the entire state of the addressed pixel is supplied to the left output line 42 or the right output line 46, depending on whether it is enabled. For example, word 1 (pixel (0°0) or 15, O )), elements #0-3 provide their pixel states to left output bus 42, and elements #4-7 provide their pixel states to right output bus 46. Similarly, elements #8-B and #C-F are similarly connected to the full video bus 24 with their pixel status (-7). :, each] 6-bit word readout continues for [7].

A word representing a pixel in the scan field (e.g. words 1-6)
As a result of the 1111-order extraction operation in 3), the series of states of each pixel constituting the scanning line is transferred to the video bus 2 in a 4-bit slice.
4-2 alternate left-: 6□/' right-left pattern;
4-bit register 70 that acts as a multiplexer multiplexes (2:1) the 8-bit data on the video bus 24 into 4-bit data and supplies it to the bus γ3.
．． Included in 72. By the operation of registers 70 and 72, the appropriate sequence logic circuit 74, and an exclusive OR gate 75 connected to an inverter 77, the video bus 2
5(c) so that the data on FIG. 4 are processed in the order shown in FIG. 5(c). The video output module 22 gives priority to register 70 over register 72 if the monthly 1Lμ(y) address of the word is an even number.
However, if the Y address is an odd number, the enable order of the chip is reversed. The evenness of the Y address is determined using the least significant bit (VERT) of the vertical address using a known method.
LSB ) and the signal from the j1-order logic circuit 74 by performing an exclusive zero operation.

The above video output module processing order results are as follows: CRT
The pixel bit states can be provided on bus 73 in 4-bit parallel slices in the order in which they are scanned. These 4-bit pixel slices are then stored in 4-bit registers 8
0 to serial video data. The output of the shift register 80 is connected to a CRT Z 6 or other display means for display.

Although the invention has been described above in terms of a single 1024×IQ24X1 high-speed pixel memory, it is possible to create additional bit planes in parallel format so that each plane is associated with a color. .High speed pixel memory 1
Multiple planes can be provided so that 9 is actually fixed to f2 1024 x JO 24 x 4 bits. In addition, the word length of the high-speed pixel memory 18 is multiplexed into the 32-bit parallel parsing bus 20 and the video bus 24 (2 pairs
J? It consists of 64 bits. Furthermore, the memory of the third quotient
Section 32°34.36.38 is similarly 644(x
It can be configured as 4X4. Therefore, CRT2
Each pixel, such as 6, can be defined by a total of 4 bits, each of which is defined in a parallel hit plane of the high speed pixel memory 19. If such a collar mechanism is desired, the left output bus 42. Right output bus 46, /;h input bus 40, and right input bus 44U1, to accommodate the 4-bit plane.
It is clear that it consists of 16-bit parallel paths.The high speed pixel memory 18 is similarly constructed.

Thus, an improved computer memory organization and structure has been disclosed. The present invention enables high-speed graphical operations using independent memory structures in which line vectors defined across four consecutive pixels on a display system are stored in four different memory elements. The geometry of the memory elements representing the pixels defining the display is achieved by offsetting the memory elements representing each row of pixels from adjacent rows. Furthermore, the present invention has been disclosed to match/readout and 1-include all commercially available video displays.

[Brief explanation of the drawing]

FIG. 1 shows a complete view of a compiro router head/stem employing the present invention. FIG. 2 shows a memory configuration of the present invention in which all storage elements for each display element are specified, with the horizontal axis representing the X address and the vertical axis representing the Y address. FIG. 3 schematically depicts a memory section of the present invention using standard dynamic random access memory devices. FIG. 4 is a diagram showing the entire word address/space allocation of the present invention, with X addresses horizontally and Y addresses vertically. Figure 5(a) is shown in Figure 2.
Display address layout knrX-j"'
. FIG. 5(b) υ8, vertical display element γ) shows the contents of the copy data bus of the present invention as a function of palace and time. Figure 5 shows the video output module processing unit 22 of the video output module 22 of the present invention. Figure 6 shows a block diagram of the video output module 22 of the present invention. .../Stem processor ν, 12・◆・φ main bus, 14-・write・vector 1) l memory, 16...
Display ◆ Generator, 17... pixel bus,
18.19...high-speed pixel memo'no, 2υ...transcription bus, 22...medium video output module, 24...
...Video bus, 26...CRT, 4υ...Left input path, 42...Left output path, 44...Right input path, 46...Right output path, 32, 34, 36,
38. See memory section, 60. Timing control means, 62-. Timing bus, 66.
・-”4 address line, 67...Read, address 7.70+72.80...Register, 73...
・Bus, 14...1ljl Ordinal logic circuit. H+:'Applicant Subektrakurano4x Corporation Agent Masaki Yamakawa (and 1 other person) 615- Yuwata? I-re? -I↑Saku≦7.5t26ノ-4 5'c) +

Claims (1)

[Scope of Claims] ('') A display device, with a memory for storing a display of a selectively enabled element of the display device; 2) The M5r memory stage includes N memory elements, and each of the elements stores a constant point among the points. ;The N j memory photons are
Q' is configured such that the points representing adjacent display elements are stored in different memory elements; the user can enable the adjacent display elements faster than the four cycles of said memory element; Memory that can be used as a rough F4 characteristic. (2) The memory according to claim 1, wherein the elements are arranged in a two-dimensional (X-Y, Number #0~
3. The memory according to claim 2, characterized in that N is assigned. (4) The states of display elements with different Y addresses are determined by a predetermined number of said elements p, memory elements offset numerically by (.
4. The memory according to claim 3, wherein the memory is stored in . (5) The memory element records points representing the display elements in a repeating NXM pattern that is symmetrically repeated such that all of the display elements are represented in the storage means.
Fi, what I want to do! Claim 4 (Memory as described in lζ. (6) When the display elements are arranged in 1024 y [24 arrays] IT'F as described in Claim 5) memory. (7) N --1, number for 6 memory elements! r Q~
The memory according to claim 6, characterized in that the number 15 is given by 9. (8) The memory element (d2, element on the display device?
The Y address function and j ~ are offset by a factor of 4: n: The same memory element is accessed no more than N times in 4 cycle times.
A memory according to claim 7. (9> r) iJ ii Self-memory retrieval - consists of 64 dynamic ■ AM Kani) Claim 8, 7, one self-mounted memory (10) the display element is raster scan display Hf! , the pixel of 0 is made of Sakae! Characteristic Patent 1 Kiyogu 0 Sword iI
α Section 91 (・'Ko 1 Self 4 Memories. (11) MiJ Memory Elements V14 Memory Sections (・'Ko 1・, li[1 Hundred Said 1, Said 1st and 2nd
The section contains all the features (the first and second sections are connected to a common input bus and output bus). 't*MClaim 8(・'(memory described. Claim 11, characterized in that the third and fourth sectors are in contact with a common input bus and an output bus V. (13) said common llT1 cover of said section is connected to video output module means for displaying the contents of said storage means (I-Memory according to claim 12 characterized in 1, (14) The storage means C1
, the above-mentioned Yasukami is enabled from the previous i-pi display device i7 (・'
ζchi71. Rujun J'! 14. The memory according to claim 13, further characterized in that it includes control means for reading out the state of the stored/hit point on the A-th day. 05) The video module means (・) 11.11(r
rc, represents the data points supplied to the output bus as a function of the Y address of the subelement f.
14♂F A memory according to claim 13 Q'ζ. (1(5) Said person's J bus (・'KOHA, 6田, Hatoji) ≧ Indicates the data points that define the part of the image 1 F (spray) supplied to the storage means - The memory according to claim 15 of claim 2, characterized in that a generator means is connected. (17) 'ffff display generator f
Dan? 7j a function of the vertical address of the display element and 1. −(
- all the features of supplying all the points and the storage means 1tζ -
The memory according to item 16 of KCNil, which specifically claims 1γF. 18. The memory according to claim 17, wherein each of the parallel planes of the memory element (1, 8) and r3U represents an element associated with a single color combination. (19) providing a computer display system having a display means running thereon, wherein the display means includes one or more selectively arranged display means; -), the entire representation of said elements is stored in memory; The display means includes N memory elements, each of the njj memory elements representing a predetermined number of previous 6I points δ1:memory1 . the N memory elements or the points represented by the adjacent display elements 6 are configured so that they are stored in different memory elements; the user or the cycle time of the memory elements is Memory that can quickly enable adjacent display elements. (20) The memory according to claim 19, wherein the elements are arranged in two dimensions (X>Y) L/-. (21) The display element is 1024X1024 Al/
−(in array)'IY: Ship mark and E2, memory 3° (22) N = 16 memory elements consecutively β2 number 0
~] Bamboo 1 with 7 as an additional sign that 5 is in power? 'Memory described in item 2j of the range of evaluation 3. (23) Is it the state of an imprisoning element that has a different Y address?
A patent claim characterized in that, by means of four of the above-mentioned elements, the numerical value t/iTh is stored in a memory cumulative f- with seven sets of numerical values t/iTh from the memory element representing the ^11th cumulative tooth of the instantaneous contact f Z] row. (24) The memory element (is either all of the element or the NI
repeated symmetrically as represented by the L memory means 7
,) Repeatedly, a 16x4 pattern is used to store the points that the display element represents. (25) The memory element is 64 in 4 nm RAM.
25. A memory according to claim 24, characterized in that it consists of %. (26) The memory according to claim 25, wherein the display element comprises a pixel element of a raster scan display device. (27) Multi-color display/;-, each representing elements with a single color. The memory according to range item 26.