JPH05108467A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To easily execute the operation of the Bit BLT and the pattern filling of a memory device at high speed. CONSTITUTION:A semiconductor storage device consists of a memory cell array 9, a data storage register file 2 into which data is written, a selection circuit 14 selecting an address for the register file 2, a logical operation device 8 which logically operates the output of the register file 2 with destination data in the memory 9, a read counter 4 and a write counter 5, with which the selection circuit 14 increments the address of the register file, a selection gate 11 selecting an address bus or the address of the read counter 4 by a selection signal showing the pattern filling or Bit-BLT and a selection gate 12 selecting the output of the selection gate 11 or the address of the write counter 5 by the signal showing reading or writing. Thus, one storage element can be used as FIFO for Bit BLT and the registet for pattern filling, and it is not necessary to repeat the same writing at the time of repeating the same pattern for more than twice.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a high speed writing circuit which is effective when used in a video memory used as an image frame memory in an information device such as a personal computer or a workstation. It is a thing.

[0002]

2. Description of the Related Art In recent years, a memory having an internal function has been used as an image memory. Conventionally, such a memory has a structure shown in FIG. The configuration will be described below with reference to FIG.

Reference numeral 9 denotes a memory cell array for storing data,
Reference numeral 6 is a latch for storing source data from the outside, 7 is a latch for storing word data read from the memory cell array 9, 8 is a logical operation device for performing logical operation processing on the data stored in the latches 6 and 7, and 13 is A latch 10 for storing the logical operation mode of the logical operation device given from the data bus is a write mask logic for controlling whether or not the word data in the memory cell array 9 is updated with the output data of the logical operation device 8 by a mask signal Mask. Is.

First, the operations of scroll transfer, Bit-BLT, and pattern fill using a conventional memory will be described. In conventional memory, scroll transfer and Bi
When performing t-BLT, an arbitrary word is read from the memory cell array in the read mode, scrolling or Bit-BLT is performed by an external circuit, and written in the memory cell in the write mode. The details of scroll transfer and Bit-BLT operation are explained below.

First, the operation of scroll transfer using a conventional memory will be described. FIG. 5 shows an example of access in scroll transfer of a memory device using the conventional method. In this example, 12-bit data (aa) at a certain location on the memory shown in A is replaced with 1-bit data at another location shown in B.
This is a case of transferring to a 2-bit area (bb). In addition,
In this conventional example, the data width is described as 4 bits.

As shown by D in the figure, first, the first 4 bits (a1) of the data group of the transfer source A are read by the memory read cycle and held in the register outside the memory device. Then, the 4-bit data (a1)
Is written as write data (d1) in the write cycle of the memory. At this time, the transfer destination B ((b
In 1), the transferred bit is the rightmost one bit, so
The value of the mask data during the write cycle is also (d2).

Similar operations are performed in the following cycles E, F, G, and individual data in the area (aa) of the transfer source A is transferred to the area (bb) of the transfer destination B. Therefore, the transfer result of H in the figure is obtained, and it is understood that the scroll transfer is correctly performed.

Next, when a data group in a continuous area is transferred to another place by using a conventional memory (B
(ItBLT) will be described. FIG. 6 shows an access example in BitBLT of a memory device using a conventional method. In this example, 12-bit data (aa) at a certain location on the memory as shown in A is transferred to a 12-bit area (bb) at another location as shown in B.

As shown in D of the same figure, first, the first 4 bits (a1) of the data group of the transfer source A are read by the read cycle of the memory and held in the register outside the memory device. At that time, the same 4-bit arbitrary data (d0) is concatenated with the higher order of the stored data (d1). Then, the 8-bit data (d0) and (d1) are shifted downward by two by barrel shift, resulting in the data (d2). Lower 4 of data (d2)
The bit is written as write data (d3) in the memory write cycle. Transfer destination B at this time
In (b1), since only the lower one bit is transferred, the mask data value in the write cycle is also (d4).

Next, as shown by E in the same figure, the second 4 bits (a2) of the data group of the transfer source A are read by the memory read cycle and held in the register outside the memory device. .. At that time, the data (e0) of (a1) read and stored in D of the same figure is linked to the higher order of the data (e1) read this time. Then, 8-bit data (e0) (e1) becomes 2 by barrel shift.
By one lower, resulting in data (e2). The lower 4 bits of the data (e2) are written as write data (e3) in the memory write cycle. At this time, in (b2) of the transfer destination B, since all the bits are transferred, the value of the mask data in the write cycle is also (e4).

Similar operations are performed for the following cycles F and G, and the individual data in the area (aa) of the transfer source A is transferred to the area (bb) of the transfer destination B. Therefore, it is understood that the transfer result of H in the figure is obtained, and BitBLT is correctly performed.

Next, the operation of the BitBLT accompanied by the raster calculation processing will be described using a conventional memory. The raster operation is a logical operation between the data before transfer (destination data) in the transfer destination B and the transferred pattern data (aa), and is frequently used in graphics processing. This is one of the processes. FIG. 7 shows an access example in BitBLT with raster operation processing of the memory device using the conventional method. In this example, 12-bit data (aa) at a certain location on the memory shown in A is replaced with 1-bit data at another location shown in B.
This is a case where the logical product operation processing is performed and transferred to the 2-bit area (bb).

As shown by D in the figure, first, the first 4 bits (a1) of the data group of the transfer source A are read by the read cycle of the memory and stored in the register outside the memory device. At that time, the same 4-bit arbitrary data (d0) is concatenated with the higher order of the stored data (d1). Then, the 8-bit data (d0) and (d1) are shifted downward by two by barrel shift, resulting in the data (d2). Next, the first 4 bits (b
1) is read and held in a register outside the memory device. Then, the destination data (d
3) and the lower 4 of the data (d2) after the barrel shift.
Raster operation is performed with bits. The resulting data (d4) is written to the memory in the write cycle. At this time, in (b1) of the transfer destination B, since the transferred bit is the lower one bit, the value of the mask data in the write cycle is also (d5).

Next, as shown in E of the same figure, the second 4 bits (a2) of the data group of the transfer source A are read by the memory read cycle and held in the register outside the memory device. .. At that time, the data (e0) of (a1) read and stored in D of the same figure is linked to the higher order of the data (e1) read this time. Then, 8-bit data (e0) (e1) becomes 2 by barrel shift.
By one lower, resulting in data (e2). Next, the second 4 bits (b2) of the data group of the transfer destination B is read by the memory read cycle and held in the register outside the memory device. Then, a raster operation is performed between the destination data (e3) and the lower 4 bits of the data (e2) after the barrel shift. The resulting data (e4) is written to the memory in the write cycle. At this time, in (b2) of the transfer destination B, since all the bits are transferred, the value of the mask data in the write cycle is also (e4).

Similar operations are performed in the following cycles F and G, and individual data in the area (aa) of the transfer source A is raster-processed and transferred to the area (bb) of the transfer destination B. .. Therefore, it is understood that the transfer result of H in the figure is obtained, and that BitBLT with raster operation processing is correctly performed.

Next, the operation of pattern fill using this conventional memory will be described. FIG. 8 shows an example of access in the pattern fill of the memory device using the conventional method. In this example, 16
This is a case where the bit pattern data (p1) to (p4) are written in the 32-bit area in the memory cell array shown in (a0). In this conventional example, the data width will be described as 4 bits.

As indicated by A1 in the figure, first, the pattern data designated by the row address is written in the portion designated by the same row address by the page mode write cycle. That is, as shown by A1, the pattern data (p1) is written in the memory cell array at the row address and the first column address as shown in (a1), and the pattern data (p1) is written in the memory cell array at the next column address. It is written as (a2). B1, B2,
The same operation is repeated for C1, C2, D1 and D2, and the pattern data (p2), (p3) and (p4) are sequentially written into the memory cell array, and finally the memory cell array is patterned as shown in (d2). Fill is written.

Next, the operation of pattern filling of an arbitrary area using this conventional memory will be described. FIG. 9 shows an access example in pattern fill of an arbitrary area of a memory device using the conventional method. In this example, 16-bit pattern data (p1) on the external storage element as shown in P
Pattern filling is performed for (p4) to the area specified by the mask data (m0).

As indicated by A1 in the figure, first, the pattern data (p1) is output from the external storage element by the row address of the page mode write cycle, and the pattern data (p1) is input at the same time as the input of the first column address. Is read into the latch in the memory as input data. Input data (p
In the case of 1), the data of the memory cell array is updated only in the area designated by the mask data (m1) and becomes as shown in (a1). A2
As shown in, the pattern data pattern data (p1) is read into the latch in the memory as input data again at the same time when the second column address is input. Input data
In (p1), the data of the memory cell array is updated only in the area designated by the mask data (m2), and becomes like (a2).
The same operation is performed for B1, B2, C1, C2, D1, D2,
Finally, it can be seen that data is input to the memory cell array as shown in (d2) and arbitrary pattern filling is performed.

[0020]

The first problem in such a conventional configuration is scroll transfer and BitB.
For the LT, a means for holding the transfer source data must be prepared outside the memory device. In addition, the exchange of data between the memory device and the outside causes a large time delay, which is not suitable for speeding up.

As a second problem in the conventional configuration, it is necessary to hold the transfer source data or perform barrel shift outside the memory device when performing BitBLT. For this reason, particularly in graphics, the load on the CPU becomes large, and the processing speed does not increase.

As a third problem in the conventional structure, a means for holding the pattern data in performing the pattern fill must be prepared outside the memory device. In addition, the exchange of data between the memory device and the outside causes a large time delay, which is not suitable for speeding up.

The present invention has been made in view of the above points, and by providing a register file having both functions of a FIFO and a register, a barrel shifter or pixel align function, and a raster operation function in the memory device, an extra memory is provided. Memory that can process BitBLT and pattern fill easily and at high speed by omitting the control and holding device and the time required for such cycle and external barrel shift process, raster operation process and pattern fill. The purpose is to provide.

[0024]

A semiconductor memory device according to the present invention includes a memory cell array, a register file for storing a part of data to be written in the memory, a selection circuit for selecting an address to the register file, and And a logical operation device that logically operates the output of the register file with the destination data in the memory.

The selection circuit for selecting the address to the register file increments the address of the register file by using the read counter for reading and the write counter for writing, and the selection signal representing pattern fill or Bit-BLT for the address bus or It comprises a first select gate for selecting the address of the read counter and a second select gate for selecting the output of the first select gate or the address of the write counter by a signal indicating read or write.

[0026]

According to the present invention, the above configuration eliminates the need for holding data externally, and requires less time delay due to the exchange of data between the memory device and the outside. Therefore, it is fast, and is easy to perform scroll transfer or BitBLT. Pattern fill can be performed. In addition, since the register file is made to have both FIFO and register functions by using the selection circuit and this register file is held in the memory, it is possible to use a single storage element for Bi.
Since it can be used as a FIFO for tBLT and also as a register for pattern fill, it is not necessary to repeat the same writing when the same pattern is repeated twice or more.

Further, when the register file is used as a FIFO, the read and write counters are also provided inside the selection circuit, so that a control signal from the outside is unnecessary.

[0028]

1 shows the structure of a memory device according to an embodiment of the present invention.

In FIG. 1, 1 is a barrel shifter for shifting word data in arbitrary bit units, 2 is a register file for storing a plurality of word data, 14 is a selection circuit for selecting an address to the register file 2, and 4 is a register file. When 2 is used as a FIFO for BitBLT, a read counter that counts the reading of words, 5 is a FI for register file 2 for BitBLT
When used as an FO, a write counter that counts word writing, 11 is a pattern fill or Bit-BLT
A select gate F that selects either the address bus or the address pointed to by the read counter 4 by a select signal F / B that represents the output of the select gate 11 or the write counter 5 by the signal R / W that represents read or write.
Select gate for selecting either of the addresses pointed to by, 6 is a latch for storing word data input from the outside by a data bus, 9 is a memory cell array for storing data, 7 is word data read from the memory cell array 9. Latch 8 is a logical operation device for performing logical operation processing between the source data stored in the latch 6, the data output from the register file 2 and the destination data stored in the latch 7, and 13 is the data A latch 10 for storing the logical operation mode of the logical operation device given from the bus is a write mask logic for controlling the update of the memory cell array 9 with the output of the logical operation device 8 by a mask signal.

Next, the operation of the memory device according to the embodiment of the present invention will be described. First, when performing BitBLT,
The word data in the memory cell array 9 is read in the page read mode and sequentially written in the register file 2. Next, in the page write mode, the data output from the register file 2 is shifted by the barrel shifter 1 according to the transfer destination of the memory cell array, raster operation processing is performed by the logical operation unit 8, and the update of writing is performed by the write mask logic by the mask signal. The data is written in the transfer destination of the memory cell array 9 in step 10.

Next, when performing pattern filling, first, a necessary pattern is written in the register file 2. Next, one word data of the register file is read at a part of the row address in the page write mode, logical operation processing is performed by the logical operation device 8, and the write mask logic 10 updates the writing by the mask signal.
It is written in the memory cell array 9 by the mn address.
Therefore, 1 word data is repeatedly written in 1 row for the area where pattern fill is performed by the number of column addresses. By repeating this repetition for the number of rows in the area, pattern filling is performed.

The operations of Bit-BLT and pattern fill will be described in detail below. First, the operation of the BitBLT using the memory device of the present invention and involving logical operation processing will be described. FIG. 3 shows an access example in BitBLT with raster operation processing using the memory device of the present invention. In this example, 12-bit data (aa) at a certain location on the memory as shown in A is subjected to a logical AND operation and transferred to a 12-bit area (bb) at another location shown in B. ..

As shown by P in the figure, first, in a page read cycle of the memory, the word data of the transfer source A is written to the address indicated by the write counter 5 of the register file, and the value of the read counter 4 is incremented by one. Repeating this, (a1) becomes (p1), (a2) becomes (p2), (a3) becomes
Writing (p3) and (a4) to (p4) is performed sequentially.

Next, as shown by D in the same figure, the data of the transfer destination is stored in the destination latch 7 by the read-modify-write cycle in the memory.
Next, 4 bits (p1) of the first address indicated by the read counter 4 of the register file P is read, and at that time,
The same 4-bit arbitrary data (d0) is the saved data
Connected on top of (d1). And 8 by barrel shift
Bit data (d0) (d1) is shifted down by two,
As a result, data (d2) is generated. Then, a raster operation is performed between the data (d3) stored in the destination latch 7 and the lower 4 bits of the data (d2) after the barrel shift. The resulting data (d4) is written to the memory by the write cycle. At this time, (b of transfer destination B
In 1), since the transferred bit is the lower 1 bit, the mask data value in the write cycle is also (d5).

Next, the read counter 4 is incremented by one. Then, as shown by E in the figure, the data of the transfer destination is stored in the destination latch 7 by the read by the read modify write cycle in the memory,
Next, 4 bits (p2) of the address indicated by the read counter 4 of the register file P is read, and at that time, the same 4-bit arbitrary data (e0) is stored data (e1).
Is connected on. Then, the barrel shift shifts the 8-bit data (e0) and (e1) by two to the lower order, resulting in the data (e2). Then, a raster operation is performed between the data (e3) stored in the destination latch 7 and the lower 4 bits of the data (e2) after the barrel shift. The resulting data (e4) is written to the memory by the write cycle. At this time, in (b2) of the transfer destination B, since all the bits are transferred, the mask data value in the write cycle is also (e5). The same operation is performed for the following cycles F and G, and individual data in the transfer source A area (aa) is transferred to the transfer destination B area (b).
It is rasterized and transferred to b). Therefore, H in the figure
BitBLT with raster calculation processing
It turns out that is done correctly.

Next, the pattern filling operation of an arbitrary area using the memory device of the present invention will be described. FIG. 4 shows an access example in pattern fill of an arbitrary area using the memory device of the present invention. In this example, 16-bit pattern data (p1) to (p4) of the register file as shown in P
Is pattern-filled in the area specified by the mask data (m0).

As shown by P in the figure, first, pattern data is written to an address given from the address bus in the register write cycle. Next, in the figure
As shown in A1, the pattern data (p1) is output from the register file 2 by a part of the row address of the page mode write cycle.
In (p1), the data of the memory cell array 9 is updated only in the area designated by the mask data (m1), and becomes like (a1) when the first column address is input. Next, as shown in A2, in the pattern data (p1) output from the register file 2, the data in the memory cell array 9 is updated only in the area designated by the mask data (m2), and the second column address is input. Therefore, it becomes like (a2). B1, B
With respect to 2, C1, C2, D1, D2, the same operation is performed by judging the data read from the register file 2 based on a part of the row address, and finally, in the memory cell array, as shown in (d2). It can be seen that data is input and arbitrary pattern fill is performed. In FIG. 1, the memory cell array 9 is accessed for each word, but the memory cell array 9 is used.
When a memory device that can be accessed in bit units with a data width in word units is used, the same function can be realized without using the barrel shifter.

[0038]

As described above, as the effect of the present invention, firstly, it becomes unnecessary to hold data externally, and the time delay due to the exchange of data between the memory device and the external is small, and the page Scroll transfer can be performed quickly and easily using the mode. Second, since the pattern data is held in the register file inside the memory when performing the pattern fill, the CPU
Load is reduced, access can be performed using page mode, and processing can be speeded up. The third is
Since the register file realizes both register and FIFO functions using the selection circuit, the circuit scale can be small, and since it functions as a register during pattern fill, once a pattern is written until the next write. It can be held and data can be read any number of times during that time.

Therefore, the semiconductor memory device of the present invention can perform BitBLT and pattern fill operations at high speed and easily as compared with the memory device having the conventional structure.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a memory device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional memory device.

FIG. 3 is a BitB of a memory device according to an embodiment of the present invention.
Diagram showing an example of LT access

FIG. 4 is a diagram showing an example of accessing a pattern fill of a memory device according to an embodiment of the present invention.

FIG. 5 is a diagram showing an access example of scroll transfer in a conventional memory device.

FIG. 6 is a diagram showing an access example of BitBLT of a conventional memory device.

FIG. 7 is a diagram showing an access example of BitBLT with raster operation processing of a conventional memory device.

FIG. 8 is a diagram showing an example of accessing a pattern fill of a conventional memory device.

FIG. 9 is a diagram showing an example of accessing a pattern fill with a mask in a conventional memory device.

[Explanation of symbols]

 1 Barrel Shifter 2 Register File 4 Read Counter 5 Write Counter 6, 7, 13 Latch 8 Logical Operation Unit 9 Memory Cell Array 10 Write Mask Logic 11, 12 Selector 14 Register File Address Select Circuit

Claims (2)

[Claims] 1. A memory cell array, a register file for storing a part of data to be written in the memory, a selection circuit for selecting an address to the register file, and an output of the register file for destination data in the memory. A semiconductor memory device having a logical operation device for performing a logical operation according to. 2. A read circuit for reading and a write counter for writing in which a selection circuit for selecting an address to the register file according to claim 1 increments the address of the register file, a pattern fill or a Bit-
A first select gate for selecting an address of the address bus or the read counter with a select signal representing BLT, and a second select gate for selecting the output of the first select gate or the address of the write counter with a signal representing read or write. Memory consisting of select gates.