JP3081037B2 - Memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer memory device used for graphics.

[0002]

2. Description of the Related Art In a computer used for graphics, in order to improve a drawing speed, drawing processing which has been performed by software is now being performed by hardware. FIG. 11 shows an example of a conventional memory device. This memory device comprises a memory array 1 having a large number of rows and columns of memories, and a row address Ro input from the outside.
w, a row decoder 4 for selecting row data in the memory array 1 based on w, a sense amplifier 2 for amplifying row data selected by the row decoder 4 based on a column address Col also input from the outside, When reading data, the column decoder 3 outputs the row data amplified by the sense amplifier 2 to the internal data bus 7 four bits at a time from the most significant bit, and masks data (source data) to be newly written when writing data. A write mask logic 5 for writing data to the memory array 1 based on data.

The operation of scroll transfer in this memory device will be described with reference to FIG. In this example, FIG.
As shown in (1), the 12-bit data stored in the predetermined memory area (aa) of the row data in the memory array 1 is changed to the 12-bit memory area at another position shown in FIG. (Bb). In this conventional example, the data width will be described as 4 bits.

[0006] As shown in FIG. 12 (3), first,
The first four bits (a1) of the transfer source data group shown in FIG.
It is held in a register external to the memory device. Next, the 4-bit data (a1) is written as write data (d1) to the transfer destination (b1) in a memory write cycle. At this time, since the bits to store the transfer data of the transfer destination (b1) are the rightmost three bits, the mask data in this write cycle is set as shown in (d2). Here, it is shown that data access is performed only to bits corresponding to the hatched portions of the mask data (d2).

A similar operation is performed in the following cycles shown in FIGS. 12 (4), (5) and (6).
The individual data in the transfer source area (aa) in (1) is transferred to the transfer destination area (bb) in FIG. 12 (2). In this way, the transfer result shown in FIG. 12 (7) is obtained, and the scroll transfer is performed correctly.

Next, in the conventional memory device shown in FIG. 11, a data group stored in a predetermined continuous memory area is transferred to another memory area (hereinafter referred to as "BitBL").
T)) will be described with reference to FIGS. In this example, row data 1 stored in a predetermined memory area (aa) of the memory array 1 shown in FIG.
This is a case where 2-bit data is transferred to a 12-bit memory area (bb) at another position shown in FIG.

First, as shown in FIG. 15, the most significant 4 bits (a1) of the row data including the transfer data (aa) of FIG. 13 are read out by a memory read cycle, and the data is stored in a register external to the memory device. (D1). At this time, arbitrary 4-bit data (d0) is connected to the upper part of the stored data (d1). Then, the 8-bit data (d0) and (d1) are shifted lower by 2 bits by the barrel shift, and as a result, the data (d2)
Is obtained. The lower 4 bits of this data (d2) are
The write data (d3) is written in the memory in which the data (b1) of the transfer destination in FIG. 14 is stored in the write cycle of the memory. At this time, the destination (b)
Since only the lower 1 bit stores the transfer data of 1), the mask data in this write cycle is also set as shown in (d4).

Next, as shown in FIG. 16, the next four bits (a2) of the four most significant bits in the row data including the transfer data of FIG. The data is held as data (e1) in the register. At this time, the data (a1) that has been read and held earlier is linked to the data (e1) as data (e0). Next, the 8-bit data (e0) (e1) is shifted downward by 2 bits by barrel shift, and as a result, data (e2) is obtained. The lower 4 bits of the data (e2) are the write data (e2).
As 3), in the write cycle of the memory, the data (b2) of the transfer destination in FIG. At this time, since the transfer data is stored in all the bits of the transfer destination (b2) in FIG. 14, the mask data in the write cycle is set as shown in (e4).

Similar operations are performed in the following cycles shown in FIGS. 17 and 18. Individual data constituting transfer data stored in the memory area (aa) in FIG. 13 is transferred to the transfer destination in FIG. Is transferred to the memory area (bb). In this way, the transfer result of FIG. 19 is obtained,
BitBLT is performed correctly.

Next, the operation of BitBLT involving raster operation processing in the conventional memory device of FIG. 11 will be described with reference to FIGS. The raster operation corresponds to the above-described FIG.
Is to perform a logical operation between the destination data stored in the destination memory area (bb) and the pattern data stored in the source memory area (aa). This is one of the processes frequently used in the process. In this example, the 12-bit transfer data stored in the memory area (aa) in the memory array 1 as shown in FIG. 20 is rasterized into a 12-bit area (bb) at another position shown in FIG. The case of processing and transfer is shown.

First, as shown in FIG. 22, the most significant four bits (a1) of the row data including the transfer data shown in FIG. 20 are read out by a memory read cycle, and the data (d1) is stored in a register external to the memory device. Is held as At this time, 4-bit arbitrary data (d0) is connected to the upper part of the held data (d1). Next, the 8-bit data (d0) and (d1) are shifted lower by 2 bits by barrel shift, and as a result, data (d2) is obtained.
Next, the most significant four bits (b1) of the row data at the transfer destination in FIG. 21 are read out by the memory read cycle, and held as destination data (d3) in a register external to the memory device. Next, the destination data (d3) and the data after barrel shift (d2)
A raster operation is performed between the lower 4 bits of the operation and the operation result (d4) is obtained. The operation result (d4) is written to the memory area of FIG. 21 in which the data (b1) of the transfer destination is stored by a write cycle. At this time,
Since the transfer data is stored in the lower one bit in the memory area storing the transfer destination data (b1), the mask data in the write cycle is set as shown in (d5).

Next, as shown in FIG. 23, the next four bits (a2) of the four most significant bits of the row data including the transfer data of FIG.
The data is stored in a register outside the memory device as data (e1). At that time, the data (a1) that has been read and held earlier is placed above the data (e1) by the data (e1).
0). Next, the 8-bit data (e0) (e1) is shifted downward by 2 bits by barrel shift, and as a result, data (e2) is obtained. Next, the next four bits (b2) of the four most significant bits of the transfer destination row data in FIG. 21 are read out by the memory read cycle, and held as destination data (e3) in a register external to the memory device. You. Next, a raster operation is performed between the destination data (e3) and the lower four bits of the data (e2) after barrel shift, and an operation result (e4) is obtained. Calculation result (e4)
Is written to the transfer destination (b2) in FIG. 21 by a write cycle. At this time, since the transfer data is stored in all bits of the memory area where the data (b2) of the transfer destination is stored, the mask data in this write cycle is set as shown in (e5).

Similar operations are performed in the following cycles shown in FIGS. 24 and 25. Individual data in the transfer source area (aa) in FIG. 20 is stored in the transfer destination area (bb) in FIG. Raster operation processing is performed and transferred. In this way, the transfer result shown in FIG. 26 is obtained, and BitBLT involving raster operation processing is correctly performed.

[0014]

The conventional memory device having such a configuration has the following problems. First, when performing scroll transfer or BitBLT, it is necessary to provide a means for holding the data of the transfer source outside the memory device. Therefore, the delay time associated with data access between the memory device and the outside is required. It becomes large and is not suitable for speeding up. Second, when performing BitBLT,
Since the holding of the data at the transfer source, the barrel shift, and the like must be performed outside the memory device, the load on the CPU particularly in graphics processing increases, and the processing speed cannot be increased. Third, since the raster operation must be performed by the CPU outside the memory device, the
The load on U increases, which is not suitable for high-speed processing.

The present invention solves such a problem, and an object of the present invention is to provide scroll transfer, BitBLT,
When performing BitBLT or the like that involves raster operation processing, an extra cycle for accessing the memory can be omitted, and the time required for data retention, barrel shift processing, and raster operation processing can be shortened. The object is to provide a memory device that can be processed.

[0016]

[MEANS FOR SOLVING THE PROBLEMS] To achieve the above object
To, the invention of claim 1, further Bi performs raster operation processing
data storage means for temporarily storing row data including transfer data to be subjected to tBLT and outputting a predetermined number of bits from the most significant bit, and a barrel shifter for shifting data of a predetermined number of bits output from the data storage means; Data holding means for sequentially storing and outputting row data of a transfer destination stored in a row including a memory in which a calculation result after the raster calculation processing is to be stored in a predetermined number of bits starting from the most significant bit, and a raster calculation circuit; The data including a predetermined number of bits of data in the row data including the transfer data as the least significant bit is sequentially output from the data storage means to the barrel shifter and shifted, and the shifted data and the data output from the data holding means are provided. Raster operation processing is performed in the raster operation circuit based on the data and It is intended to write only a portion respond to the transfer destination memory of the memory array.

Specifically, the solution means taken by the invention of claim 1 is based on the premise that a memory device that outputs a calculation result obtained by performing a raster calculation process on transfer data to a transfer destination memory is provided. A memory array having memories forming columns, a row decoder for selecting row data including the transfer data in the memory array, a sense amplifier for amplifying the row data selected by the row decoder, and amplification by the sense amplifier A column decoder for sequentially outputting the selected row data by a predetermined number of bits from the most significant bit, and the predetermined number of bits of data output from the column decoder are sequentially input, and each of the predetermined number of bits of data is converted to the least significant bit. Data storage means for sequentially outputting output data having a larger number of bits than the predetermined number of bits included as bits; A barrel shifter for shifting output data from the stage by a predetermined number of bits and outputting the data, and a transfer destination row data stored in a row including a memory in which a calculation result of the raster calculation processing is to be stored, is stored in the predetermined order from the most significant bit. A data holding means for sequentially holding and outputting bit by bit, a raster operation circuit to which at least an output from the barrel shifter and an output from the data holding means are input and perform a raster operation based on at least an output from the barrel shifter; Writing means for writing only a portion corresponding to the transfer data in a calculation result of the raster calculation circuit to a transfer destination memory of the memory array is provided.

According to a second aspect of the present invention, there is provided a column decoder for sequentially outputting transfer data to be subjected to BitBLT after raster processing by a predetermined number of bits from the most significant bit, and data of a predetermined number of bits output from the column decoder. Data storage means for outputting first-in first-out data, and data holding means for sequentially holding and outputting the transfer destination data stored in the memory in which the operation result after the raster operation processing is to be stored by a predetermined number of bits from the most significant bit, A raster operation circuit, and performs a raster operation process in the raster operation circuit based on the output data from the data storage means and the output data from the data holding means, and stores the obtained operation result in the transfer destination memory of the memory array. What to write.

Specifically, the solution means taken by the invention of claim 2 is based on the premise that a memory device that outputs a calculation result obtained by performing a raster calculation process on transfer data to a transfer destination memory is provided. A memory array having a memory in a column; a row decoder for selecting row data including transfer data in the memory array; a sense amplifier for amplifying the row data selected by the row decoder; A column decoder for sequentially outputting the transfer data of the row data from the most significant bit by a predetermined number of bits starting from the most significant bit; and the data of the predetermined number of bits output from the column decoder being sequentially input and first-in first-out. Is stored in a data storage means for outputting the data and a memory for storing the calculation result by the raster calculation processing. Data holding means for sequentially holding and outputting the transfer destination data from the most significant bit by the predetermined number of bits at a time, and at least an output from the data storage means and an output from the data holding means are inputted and at least from the data storage means And a writing means for writing the result of the operation by the raster operation circuit to the destination memory of the memory array.

[0020]

According to the structure of the first aspect of the present invention, row data including transfer data is selected by the row decoder and amplified by the sense amplifier, and then stored in the data storage means from the most significant bit by a predetermined bit through the column decoder. Is done. From the data storage means, output data including a predetermined number of bits constituting the row data as the least significant bit and having a larger number of bits than the predetermined number of bits is sequentially output to the barrel shifter. The output data output to the barrel shifter is shifted by a predetermined number of bits and input to the raster operation circuit. On the other hand, the row data of the transfer destination stored in the row including the memory in which the calculation result by the raster calculation processing is to be stored is sequentially stored in the data holding means by a predetermined number of bits from the most significant bit and output to the raster calculation circuit. . The raster operation circuit performs a raster operation based at least on the output from the barrel shifter. The calculation result after the raster calculation processing is output to the writing means, and only the portion corresponding to the transfer data is written to the transfer destination of the memory array. As described above, in the memory device according to the first aspect of the present invention, it is not necessary to provide a means for holding the transfer source data outside the memory device, and it is necessary to perform the raster operation by the CPU outside the memory device. There is no CPU
B with raster operation processing without increasing the load on
itBLT can be performed.

According to the configuration of the second aspect of the present invention, the row data including the transfer data is selected by the row decoder and amplified by the sense amplifier, and then stored in the data storage means from the most significant bit via the column decoder by predetermined bits. Is done. From the data storage means, the transfer data is sequentially input to the raster operation circuit by a predetermined number of bits from the most significant bit. On the other hand, the data of the transfer destination stored in the row including the memory in which the calculation result by the raster calculation process is to be stored is stored in the data holding means by a predetermined number of bits from the most significant bit, and the data of the predetermined number of bits is sequentially stored. Output to the raster operation circuit. The raster operation circuit performs a raster operation based at least on the output from the data storage means. The operation result after the raster operation processing is output to the writing means, and is written to the transfer destination memory of the memory array. As described above, in the memory device according to the second aspect of the present invention, it is not necessary to provide a means for holding the transfer source data outside the memory device, and it is necessary to perform the raster operation by the CPU outside the memory device. BitBL with raster processing without increasing CPU load
T can be performed.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments and reference examples of the present invention will be described with reference to the drawings.

[0023] showing a configuration of a memory device according to a first exemplary embodiment of the present invention in FIG. Memory device of the present embodiment is intended to perform a scrolling transfer of the transfer data. Memory device of the present embodiment includes a memory array 1 having a memory that forms a large number of rows and columns, a row decoder 4 for selecting the rows of data including the transfer data in the memory array 1, row data selected by the row decoder , And a column decoder 3 that sequentially outputs the row data amplified by the sense amplifier 2 four bits at a time from the most significant bit. Furthermore, the memory device of the present embodiment includes a FIFO8 as a data storage means for outputting the sequentially input data of 4 bits 4 bits data output from the column decoder 3 by first-in-first-out, four-bit output from FIFO8 And a write mask logic 5 for writing only the transfer data portion of the data from the data selection gate 10 based on the mask data. Write means is constituted by the data selection gate 10 and the write mask logic 5.

[0024] a description will be given of the operation of the memory device of the present reference example. First, a row address Row and a column address Col are externally input to the row decoder 4 and the column decoder 3, respectively. Thereby, row data in the memory array 1 is selected by the row decoder 4 and amplified by the sense amplifier 2. The row data amplified by the sense amplifier 2 is sequentially read out to the internal data bus 7 by the column decoder 3 every 4 bits, and the 4-bit data read out to the internal data bus 7 is sequentially held in the FIFO 8. The 4-bit data held in the FIFO 8 is output to the data selection gate 10 on a first-in first-out basis. Next, either the source data or the output of the FIFO 8 is output to the write mask logic 5 by the data selection gate 10. In the write mask logic 5, it is determined whether or not the data in the memory array 1 is to be updated based on the output of the data selection gate 10. In the case of updating, the output from the write mask logic 5 is written to the memory array 1 based on the mask data. It is.

Next, it will be described with reference to FIG. 2, the operation of the scroll transfers in the memory device of the present embodiment. In the example shown in FIG. 2, as shown in FIG. 1A, the 12-bit transfer data stored in the predetermined memory area (aa) of the row data in the memory array 1 is
Is transferred to another 12-bit memory area (bb). In the present reference example for explaining the data width as 4 bits.

First, due to the page cycle of the memory, as shown in FIG. 2 (3), all of the row data of the transfer source in FIG. 2 (1), that is, (a1) (a2) (a3) (a4) The data is read out to the internal data bus 7 in FIG.
(C1), (c2), (c3), and (c4). Next, as shown in FIG. 2D, the first 4-bit data (c1) in the FIFO 8 of FIG. 1 is input to the data selection gate 10 of FIG. 1 as data (d1) by a write cycle of the memory. Are output to the write mask logic 5. At this time, the transfer destination (b1) in FIG.
Since the transfer data is stored in the lower three bits in the memory area where is stored, the mask data in the write cycle is set as shown in (d2).

Hereinafter, the same operation is performed in the cycles (5), (6) and (7) of FIG.
Individual 4-bit data (a) constituting the transfer data stored in the area (aa) of the transfer source memory (1)
2), (a3) and (a4) are transferred to the transfer destination memory area (bb) in FIG. 2 (2). Thus, FIG.
The transfer result shown in (8) is (h1) (h2) (h3) (h
4) is obtained. Scroll transfer is performed correctly as described above.

As described above, according to the first embodiment of the present invention,
If the row data including the transfer data is
Selected and amplified by the sense amplifier,
From the high-order bits through the column decoder at predetermined bits
It is stored in data storage means. Stored in data storage means
The row data is stored on a first-in first-out basis with a predetermined number of bits.
Are sequentially output to the writing means.
Data of a predetermined number of bits output from the data storage means.
Only the transfer data is written to the transfer destination of the memory array
I will. Thus, in the memory device according to the present reference example,
A means for holding the transfer source data is provided outside the memory device.
Data access between the memory device and the external
The delay time due to access can be reduced. Also, C
Use page mode without increasing PU load
Fast and easy scroll transfer
You.

[0029] showing a configuration of a memory device according to a second exemplary embodiment of the present invention in FIG. Memory device of the present embodiment is intended to perform BitBLT transfer data. Memory device of the present embodiment, in addition to the configuration of the first reference example shown in FIG. 1 described above,
Between the FIFO 8 and the data selection gate 10, there is provided a barrel shifter 9 for shifting the input data to lower by 2 bits. The other configuration is the same as that of FIG. 1, and the corresponding portions are denoted by the same reference numerals.

[0030] a description will be given of the operation of the memory device of the present reference example. First, a row address Row and a column address Col are externally input to the row decoder 4 and the column decoder 3, respectively. Thereby, row data in the memory array 1 is selected by the row decoder 4 and amplified by the sense amplifier 2. The row data amplified by the sense amplifier 2 is sequentially read out to the internal data bus 7 by the column decoder 3 on a 4-bit basis, and
Are sequentially stored in the FIFO 8. Next, each 4-bit data held in the FIFO 8 and the upper 3 bits of the 4-bit data are stored.
Are input to the barrel shifter 9. That is, FI
Seven consecutive bits on the FO 8 are input to the barrel shifter 9. When the uppermost 4 bits are output, arbitrary 3-bit data is added to the upper side and input to the barrel shifter 9. In the barrel shifter 9, the input 7-bit data is shifted downward by 2 bits, and the shifted lower 4 bits are output to the data selection gate 10.

Next, either the source data or the output of the barrel shifter 9 is output to the write mask logic 5 by the data selection gate 10. In the write mask logic 5, whether or not to update the data in the memory array 1 is determined by the output of the data selection gate 10,
When updating, the output from the write mask logic 5 is written to the memory array 1 based on the mask data.

[0032] Next, Bi in the memory device of the present reference example
The operation of tBLT will be described with reference to FIG.
In the example shown in FIG. 4, as shown in FIG. 1A, the 12-bit transfer data stored in the predetermined memory area (aa) of the row data in the memory array 1 The data is transferred to the 12-bit area (bb) at the other position shown.
Note that, also in this reference example, the data width is described as 4 bits.

First, due to the page cycle of the memory, as shown in FIG. 4 (3), all the row data of the transfer source in FIG. 1 (1), that is, (a1) (a2) (a3) (a4) The data is read out to the internal data bus 7 in FIG.
(C1), (c2), (c3), and (c4). Next, as shown in FIG. 4 (4), the FIFO of FIG.
An arbitrary 4-bit data is linked to the upper part of the most significant 4-bit data (c1) held in 8. Furthermore,
The lower 7 bits (d1) of the concatenated 8-bit data are input to the barrel shifter 9 of FIG. In the barrel shifter 9, the 7-bit data (d1) is
Bit shifted. Next, the lower 4-bit data (d2) of the shifted data is output from the barrel shifter 9. The 4-bit data (d2) output from the barrel shifter 9 is output to the write mask logic 5 via the data selection gate 10. At this time, the transfer data is stored only in the lower one bit in the memory area storing the transfer destination (b1) shown in FIG. 4B, so that the mask data in the write cycle is (d3). It is set as shown.

Next, as shown in FIG.
To the upper part of the 4-bit data (c2) held in the FIFO 8, 4-bit data (c1) higher than (c2) also held in the FIFO 8 is connected. Further, the lower 7 bits (e1) of the thus concatenated 8-bit data are input to the barrel shifter 9 of FIG. In the barrel shifter 9, the 7-bit data (e1) is shifted downward by 2 bits. Next, the lower 4-bit data (e2) of the shifted data is output from the barrel shifter 9. The 4-bit data (e2) output from the barrel shifter 9 is output to the write mask logic 5 via the data selection gate 10. At this time, FIG.
Since the transfer data is stored in all the bits of the memory area storing the transfer destination (b2) shown in (2), the mask data in the write cycle is set as shown in (e3).

Hereinafter, similar operations are performed in the cycles shown in (6) and (7) of FIG. 4, and the transfer data stored in the memory area (aa) of the transfer source shown in FIG. 4-bit data (a2), (a3)
And (a4) correspond to the transfer destination memory area (b) in FIG.
b). Thus, as shown in FIG .
Thus, the transfer result is obtained as (h1) (h2) (h3) (h4). BitBLT is correctly performed as described above.

As described above, according to the second embodiment of the present invention,
Lever, the line data containing the transmitted data by a row decoder
Selected and amplified by the sense amplifier,
From the high-order bits through the column decoder at predetermined bits
It is stored in data storage means. From the data storage means,
Each data of a predetermined number of bits constituting the row data is placed at the lowest
The number of bits is larger than the specified number of bits.
The threshold output data is sequentially output to the barrel shifter. Barre
The output data output to the shifter is
And the output is shifted to the writing means. Writing
The predetermined bit output from the data storage means.
Note that only the portion of the
Written to the destination of the rearray. Thus, this reference
In the memory device according to the example, the method of holding the data of the transfer source is
It is not necessary to provide the step outside the memory device, and
CPU performs barrel shift of data during tBLT.
Since there is no need to reduce the load on the CPU,
High speed because it can be accessed using storage mode
Processing can be realized.

FIG. 5 shows the configuration of the memory device according to the first embodiment of the present invention. The memory device of the present embodiment performs BitBLT after performing a raster operation process on transfer data. Arithmetic processing apparatus of the present embodiment, the memory array 1 shown in FIG. 3 described above, the row decoder 4, a sense amplifier 2 and the column decoder 3, FIFO 8 and the barrel shifter 9,
In addition to a write mask logic 5 as a writing means, a destination data latch 6 as a data holding means for storing row data of a transfer destination including a memory in which an operation result after the raster operation processing is stored, and an output of a barrel shifter 9 , A raster operation circuit 11 to which the output of the destination data latch 6 and the source data are input. The raster operation circuit 11 performs a raster operation process based on at least one of the output of the barrel shifter 9, the output of the destination data latch 6, and the source data. The output of the raster operation circuit 11, the output of the destination data latch 6, and the mask data are input to the write mask logic 5 of the memory device of the present embodiment.

The operation of the memory device of this embodiment will be described. First, a row address Row and a column address Col are externally input to the row decoder 4 and the column decoder 3, respectively. Thereby, row data in the memory array 1 is selected by the row decoder 4 and amplified by the sense amplifier 2. The row data amplified by the sense amplifier 2 is sequentially read out to the internal data bus 7 by the column decoder 3 on a 4-bit basis, and
Are sequentially stored in the FIFO 8. Next, each 4-bit data held in the FIFO 8 and the upper 3 bits of the 4-bit data are stored.
Are input to the barrel shifter 9. That is, FI
Seven consecutive bits on the FO 8 are input to the barrel shifter 9. When the uppermost 4 bits are output, arbitrary 3-bit data is added to the upper side and input to the barrel shifter 9. In the barrel shifter 9, the input 7-bit data is shifted downward by 2 bits, and the shifted lower 4 bits are input to the raster operation processing circuit 11.

On the other hand, the row data of the transfer destination stored in the row including the memory into which the calculation result after the raster calculation processing is written is stored in the destination data latch 6 via the internal data bus 7 by four bits from the most significant bit. Will be retained.
4 held in the destination data latch 6
The bit data is also input to the raster operation circuit 11. Next, a raster operation is performed by the raster operation circuit 11 based on the source data , the output of the barrel shifter 9 and the output of the destination data latch 6,
The operation result is output to the write mask logic 5.
In the write mask logic 5, it is determined whether or not the data in the memory array 1 is to be updated based on the operation result in the raster operation circuit 11, and in the case of updating, the operation result is written in the memory array 1 based on the mask data.

Next, the operation of BitBLT involving raster operation processing in the memory device of this embodiment will be described with reference to FIG. In the example shown in FIG. 6, as shown in FIG. 6A, the predetermined area (aa) of the row data on the memory array 1 is
After the 12-bit transfer data stored in the data is raster-processed, it is transferred to a 12-bit area (bb) at another position shown in FIG. Even explaining data width as 4 bits in the real施例.

First, due to the page cycle of the memory, as shown in FIG. 6 (3), all of the row data of the transfer source in FIG. 6 (1), that is, (a1) (a2) (a3) (a4) The data is read out to the internal data bus 7 in FIG.
(C1), (c2), (c3), and (c4). Next, as shown in FIG. 6 (4), the FIFO 8 of FIG.
An arbitrary 4-bit data is linked to the upper part of the most significant 4-bit data (c1) held in the. Further, the lower 7 bits (d1) of the 8-bit data concatenated in this way are input to the barrel shifter 9 of FIG. In the barrel shifter 9, the 7-bit data (d1) is shifted downward by 2 bits. Next, the lower 4-bit data (d2) of the shifted data is output from the barrel shifter 9. The 4-bit data (d2) output from the barrel shifter 9 is input to the raster operation circuit 11 in FIG.

On the other hand, the data (b1) of the destination data included in the row data stored in the transfer destination memory area of FIG. From the array 1 to the destination data latch 6 via the internal data bus 7 (d
3), and is also input to the raster operation circuit 11. Next, in the raster operation circuit 11, a raster operation is performed between the source data and the output (d2) of the barrel shifter 9 and the output (d3) of the destination data latch 6, and the operation result (d4) is written in the write mask logic. 5 is output. At this time, since only the lower 1 bit stores the operation result of the raster operation processing in the memory area where (b1) of the transfer destination in FIG. 6B is stored, the mask data in the write cycle is ( d5)
Are set as shown in FIG.

Next, as shown in FIG.
The 4-bit data (c1) located higher than (c2), which is also held in the FIFO 8, is connected to the upper part of the 4-bit data (c2) held in the FIFO 8. Further, the lower 7 bits (e1) of the thus concatenated 8-bit data are input to the barrel shifter 9 of FIG. 7-bit data (e1) in barrel shifter 9
Are shifted down by two bits. Next, the lower 4-bit data (e2) of the shifted data is output from the barrel shifter 9. The 4-bit data (e2) output from the barrel shifter 9 is output to the raster operation circuit 11 shown in FIG.
Is input to

On the other hand, the data (b2) of the row data stored in the transfer destination memory area in FIG.
Are stored in the destination data latch 6 via the internal data bus 7 as (e3), and are similarly input to the raster operation circuit 11. Next, in the raster operation circuit 11, the source data and the output of the barrel shifter 9 (e2)
A raster operation is performed between the data and the output (e3) of the destination data latch 6, and the operation result (e4) is output to the write mask logic 5. At this time, FIG.
Since the operation result of the raster operation processing is stored in all the memory areas where (b2) of the transfer destination of (2) is stored,
The mask data in the write cycle is set as shown in (e5).

The same operation is performed in the cycles shown in (6) and (7) of FIG. 6 to form the transfer data stored in the transfer source memory area (aa) of FIG. 6 (1). 4-bit data (a2), (a3)
And (a4) correspond to the transfer destination memory area (b) in FIG.
b). Thus, as shown in FIG .
Thus, the transfer result is obtained as (h1) (h2) (h3) (h4). After the raster operation processing is performed as described above, BitBLT is correctly performed.

[0046] showing a configuration of a memory device according to a third exemplary embodiment of the present invention in FIG. Memory device of the present embodiment is intended to perform BitBLT transfer data. Memory device of this reference example, except that the column decoders 12 having pixels aligned function in place of the column the decoder 3 is provided, the same as in the first reference example shown in FIG. 1 described above. That is, the column de <br/> coder 2 provided in the memory device of FIG. 1 described above is output from the most significant bit of the row data selected by the row decoders 4-bit data is selected by one of a predetermined number Although obtaining was only, the column decoder 12 in the present embodiment, among the rows of data selected by row decoders 4, function to select bit data from any bit position (hereinafter, referred to as "pixel alignment function")
have.

[0047] a description will be given of the operation of the memory device of the present reference example. First, the row address Row and the column address Col are externally supplied to the row decoder 4 and the column decoder 12.
Respectively. Thereby, row data in the memory array 1 is selected by the row decoder 4 and amplified by the sense amplifier 2. Of the row data amplified by the sense amplifier 2, four bits are sequentially read from the most significant bit of the transfer data to the internal data bus 7 by the column decoder 12 , and the 4-bit data read to the internal data bus 7 is The data is sequentially stored in the FIFO 8. F
The 4-bit data held in the IFO 8 is sequentially input to the data selection gate 10 on a first-in first-out basis.
Next, either the source data or the output of the FIFO 8 is output to the write mask logic 5 by the data selection gate 10. In the write mask logic 5, it is determined whether or not the data in the memory array 1 is to be updated based on the output of the data selection gate 10. In the case of updating, the output from the write mask logic 5 is written to the memory array 1 based on the mask data. It is.

Next, Bi using the memory device of the present reference example
The operation of tBLT will be described with reference to FIG.
In the example shown in FIG. 8, as shown in FIG. 1A, the 12-bit transfer data stored in the predetermined area (aa) of the row data on the memory array 1 is different from that shown in FIG. Is transferred to the 12-bit memory area (bb) at the position of. Note that, also in this reference example, the data width is described as 4 bits.

First, as shown in FIG. 8 (3), the transfer data of FIG. 8 (1), that is, the area (aa) in (a1) (a2) (a3) (a4) is caused by the page cycle of the memory. ) Is read out to the internal data bus 7 by the column decoder 12 having the pixel alignment function shown in FIG. 7 by four bits from the most significant bit, and is stored in the FIFO 8 shown in FIG. 7 by (c1) (c2) (c3). ) (C
4). Such a column decoder 12
The four-bit data (a1), (a2), (a3), and (a4) of the transfer source are converted to the four-bit data (c1), (c2), and (c) of the transfer source, respectively.
3), not the same as (c4).

Next, as shown in FIG. 8D, the uppermost four bits in the FIFO 8 of FIG.
The bit data (c1) is input as data (d1) to the data selection gate 10 in FIG. At this time, the write mask logic 5
All of the transfer data output from the memory cell is stored in the uppermost 4 bits of the transfer destination memory area (bb) in FIG. 8B, so that the mask data in the write cycle is set as shown in (d2). .

Hereinafter, the same operation is performed in the cycles shown in (5) and (6) of FIG. 8, and the transfer data (aa) stored in the transfer source area of FIG. 8 (1) is formed. The individual 4-bit data (a2), (a3) and (a4) are transferred to the destination area (bb) in FIG. 8B. In this way, the transfer result shown in FIG. 8 (7) is obtained as (h1) (h2) (h3) (h4). BitBLT is correctly performed as described above.

As described above, according to the third embodiment of the present invention.
If the row data including the transfer data is
Selected and amplified by the sense amplifier,
From the high-order bits through the column decoder at predetermined bits
It is stored in data storage means. Transfer from data storage means
The transmission data is written sequentially by the specified number of bits from the most significant bit.
Output to the embedding means. Writing means is data storage means
A predetermined number of bits of data output from
Write to the destination. Thus, the memory according to the present reference example
In the device, the means for holding the transfer source data is a memory device.
It is not necessary to provide outside the
Since there is no need to perform barrel shift of data
U's load is reduced, and
High-speed processing can be realized. Change
Since no barrel shifter is provided,
The circuit becomes simpler than the memory device of the reference example 2;
The processing speed can be further improved.

FIG. 9 shows a configuration of a memory device according to the second embodiment of the present invention. The memory device of the present embodiment performs BitBLT after performing a raster operation process on transfer data. The memory device of this embodiment is the same as that of the first embodiment shown in FIG. 5, but differs in the following points. That is, different from the point where the column decoders 12 having pixels aligned function in place of the column the decoder 3 is provided, in that the barrel shifter 9 is not provided. Thus, in this embodiment, as in the third reference example described above, the column decoder 12 of the line data selected by the row decoders 4 has a function of selecting bit data from any bit position ing.

The operation of the memory device of this embodiment will be described. First, the row address Row and the column address Col are externally supplied to the row decoder 4 and the column decoder 12.
Respectively. Thereby, row data in the memory array 1 is selected by the row decoder 4 and amplified by the sense amplifier 2. Of the row data amplified by the sense amplifier 2, four bits are sequentially read from the most significant bit of the transfer data to the internal data bus 7 by the column decoder 12 , and the 4-bit data read to the internal data bus 7 is The data is sequentially stored in the FIFO 8. F
The 4-bit data held in the IFO 8 is sequentially input to the raster operation processing circuit 11 on a first-in first-out basis.

On the other hand, the transfer destination data stored in the memory area (bb) in which the operation result after the raster operation processing is written is stored in the internal data bus 7 by four bits from the highest order by the column decoder 12 having the pixel alignment function. Is stored in the destination data latch 6 via The 4-bit data of the transfer destination held in the destination data latch 6 is similarly input to the raster operation circuit 11. Next, the raster operation circuit 11 performs a raster operation based on the source data , the output of the barrel shifter 9 and the output of the destination data latch 6, and outputs the operation result to the write mask logic 5. In the write mask logic 5, the memory array 1 is operated according to the operation result of the raster operation circuit 11.
It is determined whether or not to update the data in. If it is to be updated, the operation result is written to the memory array 1 based on the mask data.

Next, the operation of BitBLT involving raster operation processing in the memory device of this embodiment will be described with reference to FIG. In the example shown in FIG. 10, as shown in FIG. 1A, a predetermined area (a
After the 12-bit transfer data stored in a) is subjected to the raster operation processing, it is transferred to another 12-bit memory area (bb) shown in FIG. Even explaining data width as 4 bits in the real施例.

First, as shown in FIG. 10 (3), the transfer data of the transfer source of FIG. 10 (1), ie, (a 1) (a 2) (a 3) (a 4) by the page cycle of the memory, only parts that are stored in the region (aa) is read to the internal data bus 7 by a column decoder 12 which have pixel alignment function of 4 bits each Figure 9, the figure F
The data is stored as (c1) (c2) (c3) (c4) in the IFO8. By such a pixel alignment function of the column decoder 12, the transfer source 4-bit data (a
1), (a2), (a3), and (a4) are 4-bit data (c1), (c2), (c3), and (c4) after transfer.
Is not the same as Next, as shown in FIG. 10 (4), a FIFO write of FIG.
The data (c1) of the most significant 4 bits is data (d1)
Is input to the raster operation circuit 11 of FIG.

On the other hand, among the destination data stored in the transfer destination memory area (bb) of FIG. 10B where the calculation result after the raster calculation processing is stored, the data of 4 bits from the most significant bit are: The data is stored as (d2) in the destination data latch 6 from the memory array 1 via the internal data bus 7, and
1 is input. Next, in the raster operation circuit 11,
A raster operation is performed between the source data and the output (d1) of the FIFO 8 and the output (d2) of the destination data latch 6, and the operation result (d 3 ) is output to the write mask logic 5. At this time, since all the operation results of the raster operation processing are stored in the uppermost 4 bits of the transfer destination memory area (bb) in FIG. 10B, the mask data in the write cycle is as shown in (d4). Is set.

Hereinafter, similar operations are performed in the cycles shown in FIGS. 10 (5) and (6).
Each of the 4-bit data (a2), (a3), and (a4) that constitute the transfer data (aa) stored in the transfer source area of the transfer destination area (bb) of FIG. Is forwarded to In this way, the transfer results shown in FIG. 10 (7) are obtained as (h1) (h2) (h3) (h4). BitBLT is correctly performed as described above.

[0060]

The memory device according to the first aspect of the present invention includes, as the least significant bit, data of a predetermined number of bits constituting row data including transfer data, and stores data having a bit number larger than the predetermined number of bits. A data storage means for outputting, a barrel shifter for shifting output data from the data storage means by a predetermined number of bits and outputting the data, and a row including a memory in which a calculation result of the raster calculation processing is to be stored. A data holding means for storing row data of a transfer destination by a predetermined number of bits starting from the most significant bit and outputting the data to a raster operation circuit.
, The load on the CPU is reduced, and access can be made using the page mode, so that high-speed processing can be realized.

According to a second aspect of the present invention, there is provided a memory device in which a column decoder for storing predetermined bits from a most significant bit of transfer data in a data storage means and a memory for storing an operation result of raster operation processing. Data holding means for storing the transfer destination data in a predetermined number of bits from the most significant bit and outputting the data to the raster operation circuit, and transfer of the predetermined number of bits of the transfer data output from the data storage means and the transfer output from the data holding means A raster operation circuit for performing a raster operation process by using data of a predetermined number of bits of the preceding data, so that a Bit operation involving the raster operation process is performed.
It is not necessary to perform barrel shift of data at the time of BLT, the load on the CPU is reduced, and access can be made using the page mode, so that high-speed processing can be realized. Furthermore, since no barrel shifter is provided,
As compared with the memory device of the first aspect , the circuit is simplified, and the processing speed can be further improved.

As described above, the memory device of the present invention has a scroll transfer, a BitBL
BitBLT involving T and raster operation processing can be performed at high speed, and the pattern fill operation can be performed at high speed and easily.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a memory device according to a first reference example of the present invention.

FIG. 2 is a diagram showing an operation of scroll transfer according to a first reference example of the present invention.

FIG. 3 is a configuration diagram of a memory device according to a second reference example of the present invention.

FIG. 4 is a diagram illustrating an operation of BitBLT according to a second reference example of the present invention.

FIG. 5 is a configuration diagram of a memory device according to a first embodiment of the present invention.

FIG. 6 is a diagram illustrating the operation of BitBLT involving raster transfer in the first embodiment of the present invention.

FIG. 7 is a configuration diagram of a memory device according to a third reference example of the present invention.

FIG. 8 is a diagram illustrating an operation of BitBLT according to a third reference example of the present invention.

FIG. 9 is a configuration diagram of a memory device according to a second embodiment of the present invention.

FIG. 10 is a diagram illustrating an operation of BitBLT involving raster transfer according to the second embodiment of the present invention.

FIG. 11 is a configuration diagram of a conventional memory device.

FIG. 12 is a diagram showing a scroll transfer operation in a conventional memory device.

FIG. 13 is a diagram showing row data including transfer data in a BitBLT operation of a conventional memory device.

FIG. 14 is a diagram showing row data including a transfer destination memory in a BitBLT operation of a conventional memory device.

FIG. 15 is a diagram showing the operation of BitBLT in a conventional memory device.

FIG. 16 is a diagram showing the operation of BitBLT in a conventional memory device.

FIG. 17 is a diagram illustrating the operation of BitBLT in a conventional memory device.

FIG. 18 is a diagram illustrating the operation of BitBLT in a conventional memory device.

FIG. 19 is a diagram showing row data of a transfer destination after BitBLT of a conventional memory device.

FIG. 20B illustrates a conventional memory device with raster operation processing.
FIG. 10 is a diagram showing row data including transfer data in the operation of itBLT.

FIG. 21B illustrates a conventional memory device with raster operation processing.
FIG. 14 is a diagram illustrating row data including a transfer destination memory in the operation of itBLT.

FIG. 22 is a diagram illustrating an operation of BitBLT involving raster operation processing in a conventional memory device.

FIG. 23 is a diagram showing the operation of BitBLT involving raster operation processing in a conventional memory device.

FIG. 24 is a diagram showing the operation of BitBLT involving raster operation processing in a conventional memory device.

FIG. 25 is a diagram illustrating an operation of BitBLT involving raster operation processing in a conventional memory device.

FIG. 26 is a diagram B showing raster operation processing of a conventional memory device.
It is a figure which shows the row data of the transfer destination after itBLT.

[Explanation of symbols]

Reference Signs List 1 memory array 2 sense amplifier 3 column decoder 4 row decoder 5 write mask logic (writing means) 6 destination data latch (data holding means) 7 internal data bus 8 FIFO ( data storage means) 9 barrel shifter 10 data selection gate 11 raster operation Circuit 12 column decoder

Continued on the front page (72) Inventor Keizo Sumida 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-1-163882 (JP, A) (58) .Cl. ⁷ , DB name) G11C 11/40-11/409 G06F 15/66

Claims (2)

(57) [Claims] 1. A memory device for outputting an operation result obtained by performing a raster operation process on transfer data to a transfer destination memory, comprising: a memory array having a plurality of rows and columns of memories; A row decoder that selects the row data including the transfer data therein; a sense amplifier that amplifies the row data selected by the row decoder; and a predetermined number of bits starting from the most significant bit, the row data being amplified by the sense amplifier. A column decoder for sequentially outputting, the output having the predetermined number of bits output from the column decoder being sequentially input, and having a bit number larger than the predetermined number of bits including each of the predetermined number of bits of data as the least significant bit A data storage means for sequentially outputting data; and a data storage means for sequentially outputting data from the data storage means by a predetermined number of bits. A barrel shifter that shifts and outputs the data, and a data hold that sequentially stores and outputs the row data of the transfer destination stored in the row including the memory in which the calculation result by the raster calculation processing is to be stored in the predetermined number of bits from the most significant bit. Means, a raster operation circuit to which at least an output from the barrel shifter and an output from the data holding means are input and perform a raster operation based on at least an output from the barrel shifter; Writing means for writing only a portion corresponding to transfer data into a transfer destination memory of the memory array. 2. A memory device for outputting an operation result obtained by subjecting transfer data to a raster operation process to a transfer destination memory, comprising: a memory array having a large number of rows and columns of memories; wherein a row decoder for selecting rows of data including the transfer data, the sense amplifier and the top-level of the transfer data of the rows data amplified by the sense amplifier for amplifying the row data selected by the row decoder in A column decoder for sequentially outputting a predetermined number of bits at a time from a bit; data storage means for sequentially inputting the predetermined number of bits of data output from the column decoder and outputting the predetermined number of bits of data on a first-in first-out basis; The transfer destination data stored in the memory where the operation result should be stored, A data holding means for sequentially holding and outputting a predetermined number of bits each, and at least an output from the data storage means and an output from the data holding means are inputted and a raster operation is performed based on at least an output from the data storage means A memory device, comprising: a raster operation circuit; and a writing unit that writes an operation result of the raster operation circuit to a transfer destination memory of the memory array.