JPH1027130A - Picture processor and its processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly obtain face sequential type data from dot sequential type data by simple constitution. SOLUTION: Sixteen dot sequential type data in which pixels have continuous positional relation are stored in the same addresses of respective DRAMs 800 to 815 constituting a fame memory. Four dot sequential type data having continuous positional relation of pixels are read out by one access specified by a column address strobe(CAS) signal. Then the four dot sequential data are respectively separated into data indicating respective fundamental colors and data indicating respective elements are arrayed in each fundamental color in the order of pixels to obtain the face sequential type data of each fundamental color.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus suitable for outputting, for example, plane-sequential drawing data to an output device of a full-color printing apparatus. The present invention relates to an image processing apparatus that stores the image data once, converts the image data into a frame sequential format, and outputs the image data.

[0002]

2. Description of the Related Art Generally, a color image is composed of a plurality of pixels. The pixel further includes multi-value data indicating each basic color of the pixel. For example, one pixel is Y (yellow), M (magenta), C
(Cyan) and K (Black)
In addition, when one basic color is represented by 8 bits, data representing one pixel is represented by 32 bits because four 8-bit data representing the basic color are required. Therefore, when a color image composed of a plurality of pixels is stored as data, multivalued data indicating the basic color exists for each pixel constituting the color image for the basic color.

As a method of storing such a color image as data, there are two typical methods, a dot-sequential type and a plane-sequential type. The dot-sequential type is a method in which color data for one pixel is packed and stored as one unit, and the plane-sequential type forms a color plane on a memory in a basic color unit and stores each drawing data. This is a method of storing basic colors as a unit. The general memory configurations of the dot sequential type and the plane sequential type are shown in FIG.
(A) and (b). Here, the drawing pixel is P
.., 0, P1, P2,..., In the dot sequential type, data P0 (Y), P0 (M), P0 (C), P0 indicating the basic colors Y, M, C, K for the pixel P0, respectively.
(K), data P1 (Y), P1 for pixel P1
Data representing the basic colors of Y, M, C, and K are sequentially stored for one drawing point, such as (M), P1 (C), and P1 (K). On the other hand, in the plane sequential type, a plane is provided for each basic color, and the data P0 for the Y plane is provided.
(Y), P1 (Y), P2 (Y)..., Data P0 (M), P1 (M), P2 (M).
Data P0 (C), P1 (C), P for C plane
2 (C)..., Data P0 (K) for the K plane,
Y, M, P1 (K), P2 (K) ...
The data of the basic colors is sequentially stored in the planes representing the basic colors C and K.

Here, when drawing (writing, storing) drawing data in a memory, it is considered which of a dot sequential type and a plane sequential type is more efficient. As an example, consider a case where a straight line composed of four pixels is drawn as shown in FIG. Note that drawing data is generally processed in units of pixels by a processor such as a CPU, and access is performed via a general-purpose data bus having a 32-bit width regardless of whether it is a dot sequential type or a plane sequential type. Also, 1 in the memory
Assume that a cycle such as that shown in FIG. First, in order to store the drawing data in the memory by the dot-sequential type, as shown in FIG. 18A, writing is performed in correspondence with four pixels forming a straight line, so that four cycles are required. On the other hand, in order to store the drawing data in the memory by the frame sequential type, it is necessary to use FIG.
As shown in (b), the number of cycles is four times as large as that of the dot sequential type because of writing for four pixels for each of the four planes. That is, assuming that one cycle is A [ns], 4 A in the dot sequential type
[Ns] is 16 A [ns] in the field sequential type. Therefore, in order to store the drawing data processed in units of pixels on the memory, it is efficient to store the data in a dot-sequential manner, and inefficient to store the data in a plane-sequential manner.

Next, a case where the drawing data stored in the memory is output will be considered. There are various cases in which drawing data is output. Here, a case in which the drawing data is output to a color printing apparatus will be considered. In recent color printing devices,
Almost all types that process drawing data in a frame-sequential type. This is because, since the formation of a color image is performed in units of basic colors, the drawing data must necessarily be treated in a frame sequential manner. Recently, the speed of color printing apparatuses has been increasing, and it has become necessary to perform continuous processing (tandem processing) for each color in the processing conventionally performed for each color. In order to follow such processing, it is important how fast the storage device can be accessed.

[0006] Here, if the drawing data is stored in the memory in a frame sequential type, four pixels can be transferred as one unit, but in the dot sequential type, only one pixel of color data is accessed by one access. Since it cannot be transferred, it cannot be processed at high speed. For this reason, considering data transfer to a color printing apparatus, it is desirable to store drawing data in a memory in a frame sequential manner. However, storing drawing data in a memory in a frame sequential manner is inefficient and causes a reduction in processing speed, as described above. Therefore, there has been a problem that performing a series of processing of storage and reading in a frame-sequential manner is not suitable for high-speed access to a memory as a storage device.

[0007] To solve this problem, the following techniques have conventionally existed. That is, first, a technology that enables the dot-sequential / plane-sequential writing and the dot-sequential-plane / plane-sequential reading mutually, and second, a technology that converts the dot-sequential type to the frame-sequential type. By using these technologies, drawing data is written to the memory in a point-sequential manner, and when it is output, it is read out in a plane-sequential manner to reduce the time required for a series of processes of storage and reading. Was thought. this house,
The first technique is further divided into a technique using address translation and a technique for separating a data bus. The former technique using address conversion is disclosed in, for example,
271184, JP-A-1-321573, JP-A-2-321
201641, JP-A-3-62272, etc., which are accessed in a dot-sequential type or a frame-sequential type using address conversion means in an independent address format. In the address, information such as which plane is selected and accessed (write or read) and which pixel (pixel) is selected and accessed are added. The latter technique for separating the data bus is disclosed in, for example, JP-A-3-55672 and JP-A-4-25.
No. 3094, which includes an address bus and a data bus for dot-sequential access,
Further, an address bus and a data bus are provided for field sequential access, and when accessing, these address buses and data buses are appropriately selected. Further, as a technique for converting the second dot-sequential type to the plane-sequential type, there are, for example, those described in JP-A-5-205038 and JP-A-7-141144. The obtained data is read out in pixel units, and the data is input to a data aligner composed of a shift register or hardware to form field sequential data.

[0008]

However, the first technique which enables the dot-sequential / plane-sequential writing and the dot-sequential plane / plane-sequential reading mutually, and the dot-sequential type is a field-sequential type The second technique for converting to the following has the following problem. First,
The technique using address translation in the first technique has a drawback that substantially more address buses are required because data for selecting a plane or a pixel is added. Further, the access also requires address conversion means which are not originally required. Further, the technique of separating the data bus in the first technique requires a means for selecting the address bus and the data bus, and thus has a disadvantage that the circuit scale is inevitably increased. Furthermore, when drawing data is read out and output in a frame sequential manner, there is a drawback that only one color of drawing data can be read at a time. On the other hand, in the second technique of converting the dot-sequential type to the field-sequential type, it takes several cycles to form the field-sequential type data. Since it is necessary, there is a disadvantage that the circuit scale becomes complicated and enlarged.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is an object of the present invention to write drawing data in a dot-sequential type while writing data in a line-sequential type. In addition to contributing to the speeding up of color printing devices, the configuration is simplified and the circuit scale is simplified.
An object of the present invention is to provide an image processing apparatus capable of reducing the size.

[0010]

In order to solve the above-mentioned problems, in the first invention of the present application, p and q are each an integer of 2 or more, and for one pixel, a color element of the pixel is indicated. Multi-valued data is represented by p color elements,
In an image processing apparatus for processing drawing data arranged for each color element, a storage means for storing q drawing data in which pixels have a continuous positional relationship in a state readable in one cycle; Data from the storage means
Reading means for reading in a cycle, and separating each of the read q pieces of drawing data into multi-valued data indicating a color element, and then multiplying the multi-valued data indicating the color element for one color element in pixel order. And a separation arrangement means for arrangement. Further, in the second invention of the present application, r, s, and t are each an integer of 2 or more (where s ≧ t), and for one pixel, multi-value data indicating a color element of the pixel is represented by a color. R of the number of elements
In an image processing apparatus for processing drawing data arranged for each of the color elements, a storage unit for storing the drawing data, and s pixels in a continuous positional relationship,
It is characterized by comprising selecting means for selecting t pixels and writing means for writing drawing data corresponding to the selected t pixels to the storage means in one cycle.
Further, in the third invention of the present application, w, x, y and z are each an integer of 2 or more (provided that x ≧ y, x ≧ z)
An image processing apparatus for processing, for one pixel, multi-value data indicating the color element of the pixel, w number of color elements, and drawing data arranged for each color element, for storing the drawing data. The storage means, and y of the x pixels in a continuous positional relationship at the time of writing
Write selection means for selecting the number of pixels, writing means for writing the drawing data corresponding to the selected y pixels in one cycle to the storage means, and a pixel among the x pieces of drawing data at the time of reading. Readout selecting means for selecting z pieces of data having a continuous positional relationship, readout means for reading out the selected z pieces of drawing data from the storage means in one cycle,
After separating each of the read z pieces of drawing data into multi-value data indicating a color element, for each color element, separating arrangement means for arranging the multi-value data indicating the color element in pixel order is provided. It is characterized by having.
In addition, in the fourth invention of the present application, p and q are each an integer of 2 or more, and for one pixel, multi-value data indicating a color element of the pixel is represented by p of the number of color elements.
In the image processing method for drawing data arranged for each color element, a step of storing q drawing data in which pixels have a continuous positional relationship in a state readable in one cycle; The process of reading the drawing data in one cycle, and separating each of the read q pieces of drawing data into multi-valued data indicating a color element. Then, for one color element, the multi-valued data indicating the color element is converted to a pixel. And arranging in order.

(Operation) According to the first aspect of the present invention, q pieces of drawing data in which pixels have a continuous positional relationship are stored in advance so as to be readable in one cycle, and are read out in one cycle. Are in a continuous positional relationship q
Get drawing data. Here, one cycle of reading can be performed, for example, by storing q pieces of drawing data at the same address and designating the address at the time of reading.
These q pieces of drawing data are, for each pixel, multi-valued data indicating the color element of the pixel arranged in p number of color elements for each color element, that is, so-called dot-sequential type drawing data. is there. After separating these drawing data into other value data indicating color elements by separation arrangement means, for one color element, multi-value data indicating the color element is arranged in pixel order.
It is possible to obtain so-called plane-sequential drawing data. When these arrangements are performed for each color element, plane-sequential drawing data can be obtained for all color elements by one cycle of reading. Further, since the separating and arranging means can be substantially constituted only by rearranging the bus lines for transferring the read drawing data, the constitution can be simplified. Next, according to the second aspect of the present invention, t pixels are selected from s pixels in a continuous positional relationship, and the corresponding drawing data is written in one cycle. If they are the same, writing of the t drawing data can be completed in one cycle without repeating t cycles. Therefore, it greatly contributes to shortening the time required for writing the so-called dot-sequential drawing data.
Further, according to the third aspect of the present invention, the first and second aspects of the present invention are provided.
By combining the inventions described above, it is possible to reduce the time required for both writing and reading processing for drawing data. According to the fourth aspect of the present invention, similarly to the first aspect of the present invention, it is possible to easily obtain drawing data of a dot sequential type to a plane sequential type.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

<1: Overall Configuration> FIG. 1 is a block diagram illustrating the overall configuration of an image processing apparatus according to the present embodiment. In this figure, reference numeral 60 denotes an image information generation unit which generates a reading range of a frame memory, drawing data PD drawn in a drawing effective area, an address ADR for storing the drawing data, pixel selection data described later, and the like. I do.

Reference numeral 80 denotes a frame memory as storage means. The frame memory 80 is composed of a plurality of DRAMs, can use high-speed page mode access, and can store 32-bit data at one address. Reference numeral 70 denotes a control device, which includes a writing unit 71 and a reading unit 72. The former writing unit 7
Numeral 1 is for writing drawing data in the frame memory 80 in a dot-sequential manner, and the latter reading section 72 is for reading drawing data from the frame memory 80. The detailed configuration of the writing unit 71 and the reading unit 72 will be described later. Reference numeral 90 denotes a buffer, which comprises four FIFOs (First In First Out: first-in first-out buffers) corresponding to the respective basic colors, as described later, and buffers frame-sequential data for each basic color.

<1-1: Data Format> Here,
An example of a format of drawing data in the image processing apparatus will be described with reference to FIG. The image processing apparatus according to the present embodiment has four basic colors of Y, M, C, and K.
Colors are used, and data indicating the gradation of each of these basic colors is represented by 8 bits. Therefore, the drawing data of one pixel is 32 bits. The image processing apparatus treats such drawing data as indicating one pixel having four basic color data as shown in FIG. 2A for the dot sequential type, and FIG. ),
It is assumed that the data has one color of the basic color data and indicates four pixels. Both of the data are 32 bits.

The drawing data having such a format is written into the frame memory 80 in a dot-sequential type as described later. Therefore, this storage state will be described with reference to FIG. 3. As shown in FIG. 3, one address of one DRAM constituting the frame memory 80 has one address.
32 bits of drawing data for pixels are stored in a dot sequential manner.

<1-2: Outline of Memory Configuration> Next, a schematic configuration of the frame memory 80 in the image processing apparatus will be described. First, a process from writing to reading of drawing data will be described, and a circuit configuration for realizing this process will be described later.

<1-2-1: Flow of Drawing Data> FIG.
FIG. 4 is a block diagram for explaining the flow of drawing data in the frame memory 80. In this figure, 80
0 to 815 are DRAMs constituting the frame memory 80
Thus, as described above, data having a 32-bit width can be stored. In this embodiment, the DRAM is used to mean a memory module composed of a general dynamic RAM.

As shown in FIG.
Reference numeral 15 comprises four memory blocks MB0 to MB3, and each memory block has four surfaces. In such a configuration, drawing data in which pixels have a continuous positional relationship are sequentially stored in a memory block. That is, as shown in FIG. 5, in an effective area EA (m horizontal pixels × n vertical pixels) to be output to the color printing apparatus, a pixel drawn at the start point of the area is set to P0, and pixels to be drawn thereafter are set to P1 in order. , P
2,..., P (mn), pixels P0 to P3
Is the first of the memory blocks MB0 to MB3.
The drawing data of the pixels P4 to P7 are stored on the second surface of the memory blocks MB0 to MB3.
Is the third data of the memory blocks MB0 to MB3.
On the plane, the drawing data of the pixels P12 to P15 are stored on the fourth plane of the memory blocks MB0 to MB3, respectively. In other words, pixels P0-P
Fifteen drawing data are stored in DRAMs 800 to 815, respectively.
Is stored. These drawing data are stored in a dot-sequential type.

The drawing data stored in the DRAMs 800 to 815 is read one by one from each memory block. Then, the drawing data PD0 read from the memory blocks MB0 to MB3
To PD3 are supplied to the bus converter 820. The bus conversion unit 820, as shown in FIG.
After D3 is separated for each of the components of the basic colors Y, M, C, and K, the pixels are rearranged in the order of pixels for each of the components of the basic colors Y, M, C, and K. As a result, drawing data LDY, LDM, LDC, and LDK of the frame sequential type are obtained. Note that, as described later, the drawing data PD0 to P
D3 is simultaneously read from the memory blocks MB0 to MB3 by one access. Therefore, the bus converter 82
0, plane-sequential type drawing data LDY, LDM,
LDC and LDK can be obtained simultaneously. Further, the bus conversion unit 820 is substantially only a rearrangement of data buses.

<1-2-2: Circuit Configuration of Frame Memory> A specific circuit configuration for realizing such a process from writing to reading of drawing data will be described with reference to FIG. As shown in FIG.
15 has an address ADR, drawing data PD, R
AS (row address strobe) signal and WE
(Write enable) signals are commonly supplied. Each of the DRAMs 800 to 815 is supplied with a corresponding CAS (column address strobe signal) for each DRAM. Therefore, in this image processing apparatus, since there are 16 DRAMs,
There are also 16 S signals corresponding to each of these DRAMs. Regarding these 16 CAS signals, the CAS signal corresponding to DRAM 800 is represented by LSB, D for convenience of explanation.
The CAS signal corresponding to the RAM 815 is set to the MSB 16
It is described by bit data. The address of the frame memory 80 is the RAS (row) address and the CAS address.
(Column) address.

According to the frame memory 80 having such a configuration, the same address is designated by the RAS address and the CAS address, the WE signal and the RAS signal are both activated, and the 16 CAS signals are set to "000".
"0" for each CAS corresponding to DRAMs 800 to 815
By making the signal low active, the same drawing data can be written to each of the DRAMs 800 to 815 by one access. At the time of reading, the same address is designated by the RAS address and the CAS address, the WE signal is inactive, the RAS signal is active, and the DRAs having the same plane relationship in the memory blocks MB0 to MB3.
By activating the CAS signal of M, the drawing data PD0 to PD3 of four consecutive pixels can be read by one access.

In the frame memory 80, FIG.
Are written in the relationship shown in FIG. 7 and stored as shown in FIG. That is,
FIG. 7 is a diagram showing, for each of the DRAMs 800 to 815, what kind of pixel image data is stored in a set of addresses determined by the RAS address and the CAS address. As shown in this figure, at one address, pixels have a continuous positional relationship.
Pieces of drawing data are stored in the DRAMs 800 to 815, respectively.

<1-3: Pixel Selection Data> As described above, in this image processing apparatus, at the time of writing, a maximum of one
Six DRAMs can be accessed. However, there is naturally a DRAM that does not need to be accessed in one access. Also,
At the time of reading, the drawing data PD of four consecutive pixels
In order to obtain 0 to PD3, it is necessary to select a DRAM to be accessed. Therefore, in this image processing apparatus,
The DRAM to be accessed is selected based on the pixel selection data. FIG. 8 shows the configuration of such pixel selection data. As shown in this figure, the pixel selection data is 16-bit data whose LSB to MSB correspond to the DRAMs 800 to 815, and the bit corresponding to the DRAM to be accessed is set to "1".

At the time of writing, the pixel information is written by the image information generation unit 60 into the address ADR or the address ADR.
It is generated together with the drawing data PD and supplied to the writing unit 71. In this case, the writing unit 71 detects each bit of the pixel selection data, and activates only the CAS signal of the DRAM corresponding to the bit set to “1”. On the other hand, the pixel selection data is
As will be described later, it is generated by the timing controller of the reading section 72, and thereby generates the CAS signal. With such pixel selection data, only the DRAM that needs to be accessed at a certain address can be selected.

<1-4: Detailed Configuration of Writing Unit> Next, FIG.
Will be described in detail. FIG.
Is a block diagram showing a configuration of the writing unit 71. In the figure, reference numeral 711 denotes a RAS address latch circuit, which is an address ADR supplied from the image information generation unit 60.
RAS address is latched. Similarly, reference numeral 712 denotes a CAS address latch circuit, which latches a CAS address of the address ADR. A data latch circuit 713 latches the drawing data PD supplied from the image information generation unit 60. A pixel selection latch circuit 714 latches pixel selection data (see FIG. 8) similarly supplied from the image information generation unit 60.

715 is a timing controller,
The transmission timing of the latched RAS address and CAS address is controlled via gates 716 and 717, respectively, and is used as the write address of the frame memory 80. Further, the timing controller 715 determines the transmission timing of the drawing data PD by the data latch circuit 713.
, And the transmission timing of the CAS signal is controlled via a NAND gate circuit 718. In addition, the timing controller 715 controls the levels of the RAS signal and the WE signal in accordance with the write address transmission timing. Since the CAS signal is active low in this embodiment, the pixel selection data is inverted by the NAND gate circuit 718,
The transmission is controlled.

<1-5: Detailed Configuration of Reading Unit> Next, FIG.
The detailed configuration of the reading unit 72 in the above will be described. FIG.
0 is a block diagram showing the configuration of the reading unit 72.
In this figure, reference numeral 721 denotes a read area setting unit which sets a read area based on information indicating a read range supplied from the image information generation unit 60. An address generation unit 722 generates a read address of the frame memory 80 for each of the RAS address and the CAS address based on the set read area. Note that the address generation unit 722 suspends address generation when the level of a PAF signal (described later) supplied from the buffer 55 goes low, and resumes address generation when it goes high. Reference numeral 723 denotes a RAS address latch circuit that latches the generated RAS address. Similarly,
A CAS address latch circuit 724 latches the generated CAS address.

725 is a timing controller,
The transmission timing of the latched RAS address and CAS address is controlled via gates 726 and 727, respectively, and is used as the read address of frame memory 80. In addition, the timing controller 725 controls the levels of the RAS signal and the WE signal in accordance with the transmission timing of the read address.

<1-6: Detailed Configuration of Buffer> Next, the detailed configuration of the buffer 90 in FIG. 1 will be described.
FIG. 11 is a block diagram showing the configuration of the buffer 90. In this figure, reference numerals 901 to 904 denote FIFOs, which correspond to the basic colors Y, M, C, and K, respectively.
In this embodiment, since 32-bit field sequential data is input for one basic color, two general FIFOs having a 16-bit width are used in parallel. Then, the frame sequential drawing data L from the frame memory 80
Each of DY, LDM, LDC, and LDK receives a FIFO 901-
While being stored in 904, each basic color is output to the output device in accordance with an RE signal from an output device (not shown) such as a color printing device that requires the frame sequential drawing data. That is, the frame sequential drawing data L
Each of DY, LDM, LDC, and LDK is stored at the timing by the reading unit 72, and is read and output at the timing required by the output device.
It should be noted that the buffer 90 is an optional component if only the configuration for obtaining the frame-sequential type data from the dot-sequential type is referred to.

Here, each of the FIFOs 901 to 904 outputs flags FF1 to FF4 which fall to a low level when the amount of data stored in the FIFO becomes full. And by the AND circuit 905,
The logical product of these full flags FF1 to FF4 is obtained, and this is used as a PAF (Almost Full Flag) to the reading unit 72.
Signal. Such a PAF signal is
If there is a vacancy in O, it goes high, allowing the address to be advanced by the readout unit.
When the data storage amount becomes full, the level becomes low, and the address advance by the reading unit 72 is prohibited.

<2: Operation> Next, the operation of the image processing apparatus having the above configuration will be described. First, an operation of writing (drawing) the drawing data generated by the image information generating unit 60 into the frame memory 80 in a dot sequential manner will be described.

<2-1: Point Sequential Write Operation> Various data for drawing in the frame memory 80 are generated by the image information generating unit 60. Specifically, after the address ADR is generated separately for the RAS address and the CAS address, the dot-sequential drawing data PD and the pixel selection data to be written to the address are generated.
These data are input to the corresponding latch circuit in the writing unit 71 of FIG. 9 and are latched. At this time, the timing controller 715 uses a general DR
The output timing of each signal is controlled in accordance with the AM write timing (for example, see FIG. 17). That is, after outputting the RAS address at the RAS address timing, the timing controller 715 activates the RAS signal and outputs the RAS signal at the CAS address timing.
After outputting the AS address, the CAS signal is activated, and the drawing data PD is output at a predetermined timing to create a writing timing. At this time, the CAS signal is NANDed with the pixel selection data.
Only the CAS signal corresponding to the RAM becomes low active. Therefore, the drawing data PD is written to the address ADR determined by the RAS address and the CAS address only for the DRAM selected by the pixel selection data.

A more specific write operation will be described with reference to FIG. Note that the example of this figure shows the case shown in the left half of this figure. That is, "FFF
The drawing data PD indicated by “FFFFF” is transferred to the address ADR defined by the RAS address “000” and the CAS address “001”, and the pixel selection data is set to “F0F”.
This is a case where data is written to the DRAM indicated by "0". Note that these pieces of information are generated by the image information generation unit 60 and supplied to the writing unit 71.

In this case, the timing controller 715 of the writing section 71 controls each gate and latch circuit as follows. That is, the timing controller 715
First, after sending the RAS address "000",
The RAS signal is set to low active, and then the drawing data PD “FFFFFF” is added together with the CAS address “001”.
Third, the CAS signal is changed to "0F0F", which is obtained by inverting the pixel selection data from "FFFF" in an inactive state (because of low active). As a result, the drawing data PD of “FFFFFFFF” becomes the D data corresponding to the pixel selection data “F0F0”.
The data is written to the RAMs 804 to 807 and 812 to 817 by one access. The address determined by the RAS address “000” and the CAS address “001” is a location for storing the drawing data of the pixels P16 to P31, as can be understood from FIG. Therefore, in the example shown in FIG. 12, the drawing data PD includes the pixels P20 to P23 and the pixel P28.
DRAMs 804 to 80 as the drawing data of
7, 812 to 817 by one access.

Here, when the drawing data of 16 pixels to be written at the same address are all different, the image information generating section 60 changes the pixel selection data so as to designate the DRAMs 800 to 815 one by one in order. ,
Writing to the frame memory 80 is performed by 16 accesses. Conversely, when the drawing data of 16 pixels to be written at the same address are all the same, the image information generation unit 60 sets the pixel selection data so as to designate all of the DRAMs 800 to 815. That is, “FFFF” is set. Thus, the drawing data of 16 pixels is written into the frame memory 80 by one access, and the time required for writing can be reduced.

Since such writing is performed in the order of the drawing data generated by the image information generating unit 60, the addresses to be accessed do not need to be continuous,
Writing can be performed to a random address. When the writing of the image effective area for one surface is performed on the frame memory 80, the writing operation ends. In the case of writing, the DRA is used until the RAS address changes or until a memory refresh is started.
M high-speed page mode is used to the maximum extent, and a continuous write operation is performed.

<2-2: Surface Sequential Type Read Operation> Next, an operation of reading the drawing data written as described above and converting it into a dot sequential type will be described. When reading the drawing data written in the frame memory 80, the image information generation unit 60 first sets the reading range of the drawing data in the reading area setting unit 721 (see FIG. 10) in the reading unit 72. This read range is defined as
Indicates an area to be output from the frame memory 80 written by the above. Therefore, when drawing data is read from the frame memory 80, the same address as when writing in the dot sequential type is used.

When the read range is set in the read area setting section 721, the address generation section 722 generates a RAS address and a CAS address in units of four pixels from the first pixel in the drawing effective area. The generated addresses are stored in the RAS address latch circuits 72, respectively.
3 and are input to the CAS address latch circuit 724 and latched. At this time, the timing controller 725 controls the output timing of each signal according to the general DRAM high-speed page mode read timing. That is, the timing controller 725
After outputting the RAS address at the S address timing,
After the RAS signal is activated and the CAS address is output at the CAS address timing, the CAS signal is activated to create a read timing. At this time, the frame memory 80 stores the drawing data for 16 pixels consecutive at one set of addresses. Therefore, the reading for the same address is divided into four times by four pixels by changing the CAS signal. It is done. That is, the read for the same address is performed by the DRAM 800 in the first access.
803 to 803 in the next access
DRA for 804 to 807 in the third access
For M808 to 811 and for the fourth access, for DRAMs 812 to 815, respectively. Therefore, in one access, four dot-sequential drawing data in which pixels have a continuous positional relationship are read. In the case of reading, RA
Until the S address changes, until a memory refresh occurs, or a FIFO that stores read data
Until is full, a continuous read operation is performed using the high-speed page mode of the DRAM.

When four dot-sequential type drawing data having a positional relationship of continuous pixels are read in one access, each of these drawing data is read by the bus conversion unit 820 (see FIG. 4). After being separated into data for each basic color, data of the same basic color is arranged for each basic color in pixel order. As a result of this separation / rearrangement, plane-sequential data of four colors is obtained for each basic color in one access. Such an operation is switched while changing the address from the pixel at the start point to the pixel at the end point of the designated area, and the operation ends when all of the designated area is read.

A more specific reading operation will be described with reference to FIG. Note that, in the example of this drawing, a case is shown in which drawing data is sequentially read from an address determined by an RAS address of “000” and a CAS address of “000”. In this case, the reading range is generated by the image information generating unit 60 and supplied to the reading unit 72, and the starting point of the reading range is the pixel P0 in FIG.

In this case, first, the address generator 722
Are the RAS address “000” and the CAS address “00”
0 ", and the timing controller 725 controls each latch circuit as follows. That is, after sending the RAS address “000”, the timing controller 725 sets the RAS signal to low active,
As the AS address “000”, the CAS signal is changed to “FFF”.
0 ". The CAS signal is set to “FFFF0” in order to access the DRAMs 800 to 803 at the first time. Thereby, the DRAMs 800 to 8
03, dot-sequential drawing data PD0 to PD
3 are read out, are immediately converted by the bus conversion unit 820, and are output to the frame sequential data PDY, PDM, PDC,
PDK is obtained.

Next, the timing controller 725
After the CAS signal is set to “FFFF” and the selection of the DRAM is once canceled, the DRAMs 804 to 8
In order to access 07, the CAS signal is set to “FF0F”. As a result, the dot-sequential drawing data are read out by the DRAMs 804 to 807, respectively, and are immediately converted to obtain the frame-sequential data. Similarly, the timing controller 725 accesses the DRAMs 808 to 811 by setting the CAS signal to “F0FF” at the third time, and sets the DRAM 8 at “0FFF” at the fourth time.
By accessing 12 to 815, plane-sequential data is immediately obtained in each access.

As described above, when the drawing data of the continuous 16 pixels is read from the DRAMs 800 to 815, the address generation unit 722 increments the CAS address by “1”, and similarly, the address of the continuous 16 pixels is increased. The drawing data of the pixel is read. The same operation is repeated thereafter until the drawing data of the pixel located at the end point of the reading range is read.

As described above, according to the image processing apparatus of the present embodiment, at the time of writing, of the 16 drawing data in which the pixels are in a continuous positional relationship, the drawing data is arbitrarily selected and selected by the pixel selection data. Since the object is written to the frame memory 80 by one access, the same drawing data can be written by one access. Therefore, it greatly contributes to shortening the time required for writing so-called dot-sequential type drawing data.
Further, according to the image processing apparatus of the present embodiment, at the time of reading, four pieces of drawing data in which pixels have a continuous positional relationship are read out by one access, and these four pieces of drawing data are respectively After separation into other value data indicating colors, data indicating basic colors are arranged in pixel order for each basic color to obtain plane-sequential drawing data. As a result, plane-sequential data of each basic color is obtained by one access, so that it can greatly contribute to high-speed processing including writing.

<3: Application> The present invention is not limited to the above-described embodiment, but can be applied as follows. In the embodiment described above, the buffer 90 is constituted by FIFOs 901 to 904 corresponding to the respective basic colors,
It is assumed that an output device such as a color printing device located at the subsequent stage of the FIFO processes all the four-color sequential data. However, if the output device is, for example, two out of four color data,
Assuming that only color is processed, the other two
Since the color data continues to be stored in the corresponding FIFO,
The amount of storage in the FIFO becomes full. In such a case, the operation of reading from the frame memory 80 is interrupted, which may cause a problem that required basic color data is not supplied. Therefore, in this application form, a reading color setting section 731 is provided inside the reading section 72 as shown in FIG. This read color setting section 731
Is to input a read color requested by the image information generation unit 60 or the output device and output a reset signal so as not to buffer the FIFOs of the basic colors other than the read color. As a result, in the buffer 90, only the data of the basic color requested by the output device is stored in the FIFO, and the data of the basic color not requested by the output device is not stored in the FIFO, so that the reading operation is adversely affected. Is prevented.

<4: Others> The above-described embodiment,
In the applied embodiment, the control device 70 has a configuration including the writing unit 71 and the reading unit 72. However, as can be seen from FIGS. 9 and 10, the configurations of the writing unit 71 and the reading unit 72 are similar to each other. Therefore, it is desirable to integrate these components. With the single control device 70, the bus line can be omitted and the D
Since the refresh operation of the RAM is shared between the write control and the read control, the control can be simplified.

In the above-described embodiment or application, p = 4 and the color elements are Y, M, and
Although the case of four colors C and K has been described as an example, the present invention does not limit the color elements. For example, RGB of a color space, L ^* a ^* b ^{*, and the} like can be used. In this case, p = 3, and q pieces of drawing data in which pixels have a continuous positional relationship are read out for each access, so that q pixels of plane-sequential data of each color element can be obtained. . In the above-described embodiment or application, q
= 4, the drawing width of four consecutive pixels is read and transferred by one access, and the transfer is performed. Therefore, the bus width for transferring the drawing data read from the frame memory 80 is the point-sequential type data. (32 bits). However, the value of q in the present application is not limited to this, and any value may be used as long as it is an integer of 2 or more. For example, if q is set to “3”, three pixels for one plane-sequential type data are obtained. in this way,
In the present application, p and q are independent of each other, and may be any integers as long as each is an integer of 2 or more. In addition,
In the present application, r and w are related to p, and z is related to q.

[0049]

As described above, according to the present invention, writing data is performed in a dot-sequential manner while writing data is performed in a frame-sequential manner, contributing to speeding up of a color printing apparatus and the like. In addition, the configuration can be simplified, and the circuit scale can be simplified and reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus according to an embodiment of the present invention.

FIG. 2A is a diagram illustrating a configuration of dot-sequential data, and FIG. 2B is a diagram illustrating a configuration of plane-sequential data.

FIG. 3 is a diagram showing a storage state of drawing data in a frame memory of the image processing apparatus.

FIG. 4 is a diagram showing a flow of drawing data in a frame memory of the image processing apparatus.

FIG. 5 is a diagram for explaining a positional relationship of pixels related to drawing data processed in the image processing apparatus.

FIG. 6 is a block diagram illustrating a configuration of a frame memory in the image processing apparatus.

FIG. 7 is a diagram showing what kind of pixel image data is stored in one set of addresses for each DRAM.

FIG. 8 is a diagram showing a configuration of pixel selection data in the image processing apparatus.

FIG. 9 is a block diagram illustrating a configuration of a writing unit in the image processing apparatus.

FIG. 10 is a block diagram illustrating a configuration of a reading unit in the image processing apparatus.

FIG. 11 is a block diagram illustrating a configuration of a buffer in the image processing apparatus.

FIG. 12 is a timing chart showing a writing operation in the image processing apparatus.

FIG. 13 is a timing chart showing a read operation in the image processing apparatus.

FIG. 14 is a block diagram illustrating a configuration of a reading unit according to an application of the present invention.

FIG. 15A is a diagram showing a conventional dot-sequential memory configuration, and FIG. 15A is a diagram showing a conventional frame-sequential memory configuration.

FIG. 16 is a diagram illustrating an operation of drawing a straight line.

FIG. 17 is a diagram showing a cycle required for one access.

18A is a diagram illustrating writing of dot sequential data in the related art, and FIG. 18B is a diagram illustrating writing of frame sequential data in the related art.

[Explanation of symbols]

60 image information generating section (writing selecting means, reading selecting means), 71 writing section (writing means), 72 reading section (reading means), 80 frame memory (storage means),
90: buffer (buffer storage means), 800 to 815
... DRAM, 820 ... Bus conversion unit (separation arrangement means)

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical indication location G06T 1/00 G06F 15/64 450C H04N 1/21 15/66 310 1/60 H04N 1/40 D 1/46 1/46 Z

Claims (12)

[Claims] 1. p and q are each an integer of 2 or more, and for one pixel, multi-valued data indicating the color element of the pixel is processed by drawing data in which p number of color elements are arranged for each color element (A) storage means for storing (A) q pieces of drawing data in which pixels have a continuous positional relationship in a readable state in one cycle; and (B) storing the q pieces of drawing data. Means for reading in one cycle from the means, and (C) separating each of the q pieces of drawing data read out into multi-valued data indicating a color element, and indicating the color element for one color element. An image processing apparatus comprising: a separating arrangement unit for arranging multi-value data in pixel order. 2. The storage means stores q pieces of drawing data in which pixels have a continuous positional relationship at the same address, while the reading means designates the same address by designating the same address.
2. The image processing apparatus according to claim 1, wherein the drawing data is read. 3. An image processing apparatus according to claim 1, wherein said separation arrangement means is obtained by rearranging bus lines for transferring drawing data read from said storage means. 4. An image processing apparatus according to claim 1, wherein said separation arrangement means performs arrangement in pixel order for each color element. 5. The data arranged in pixel order by the separation arrangement means is stored for each color element.
5. The image processing apparatus according to claim 4, further comprising buffer storage means for supplying the stored data according to a request for each color element. 6. The image processing apparatus according to claim 1, wherein the reading means interrupts reading of the drawing data when the data storage amount corresponding to any one of the color elements becomes full in the buffer storage means. 6. The image processing apparatus according to 5. 7. A device for designating a required color element, wherein said reading means is provided when the data storage amount corresponding to the color element designated by said designation means becomes full in said buffer storage means. 6. The image processing apparatus according to claim 5, wherein the reading of the drawing data is interrupted. 8. Each of r, s, and t is an integer of 2 or more (where s ≧ t), and for one pixel, multi-valued data indicating a color element of the pixel is represented by r color elements, In an image processing apparatus that processes drawing data arranged for each element, (A) storage means for storing the drawing data, and (B) selecting t out of s pixels in a continuous positional relationship An image processing apparatus comprising: a selection unit that performs writing of drawing data corresponding to the selected t pixels into the storage unit in one cycle. 9. The storage means stores s pieces of drawing data in which pixels have a continuous positional relationship at the same address, while the writing means specifies the same address to thereby store the s pieces of the s pieces of data. 9. The image processing apparatus according to claim 8, wherein drawing data corresponding to t pixels among the pixels is written. 10. W, x, y, and z are each an integer of 2 or more (where x ≧ y, x ≧ z), and for one pixel, multi-value data indicating a color element of the pixel is represented by a color element. In an image processing apparatus that processes drawing data arranged for each color element, the number w is (A) a storage unit for storing the drawing data, and (B) a continuous positional relationship during writing. Of the x pixels,
writing selection means for selecting y pixels, (C) writing means for writing drawing data corresponding to the selected y pixels to the storage means in one cycle, and (D) x
Reading selection means for selecting z pieces of pixels having a continuous positional relationship among the pieces of drawing data, and (E) selecting the selected z
Reading means for reading out one piece of drawing data from the storage means in one cycle; and (F) separating each of the read out z pieces of drawing data into multivalued data indicating a color element,
An image processing apparatus comprising: a separation arrangement unit that arranges multi-value data indicating one color element in pixel order in one color element. 11. The storage means stores drawing data corresponding to x pixels having a continuous positional relationship at the same address, and the writing means designates the same address by specifying the same address. The image processing apparatus according to claim 10, wherein drawing data corresponding to y pixels is written, and the reading unit reads the selected z drawing data by designating the same address. 12. An image of drawing data in which, for each pixel, p and q are integers of 2 or more, and for each pixel, p-valued multi-value data indicating the color element of the pixel is arranged for each of the p number of color elements. In the processing method, (A) a step of storing q pieces of drawing data in which pixels have a continuous positional relationship in a readable state in one cycle; and (B) a step of storing the stored q
(C) separating each of the read q pieces of drawing data into multi-valued data indicating a color element, and
Arranging the multi-value data indicating the color element in pixel order.