JPH06223560A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide a video RAM capable of individually clearing a old mask register and a stop register, capable of rewriting a part of a memory cell array at a high speed and further capable of preventing the unnecessary transfer of data. CONSTITUTION:This device is provided with a reset signal generation circuit 50 for individually giving a reset signal RST 1 and an RST 2 to an old mask register 17 and a stop register 23. It is also provided with mask means FWM 0 to FWM (n) of a transmission gate, etc., to be optionally controlled in a flash write bus 20. It is further provided with mask means DTM 0 to DTM (n) of a transmission gate, etc., to be optionally controlled in a data transfer bus and devided data transfer buses SDTB (0) to SDTB (m) to be made continuous being devided every constant pieces. Further, data is transferred to a serial register 7 for every boundary.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a random accessible RAM.
The present invention relates to a multiport memory including a (random access memory) port and a serially accessible SAM (serial access memory) port.

[0002]

2. Description of the Related Art With the recent development of image processing technology, for example, color display on a CRT of a personal computer, three-dimensional display in a CAD system, image enlargement and reduction, screen multi-windowing, and resolution improvement. Therefore, various technological developments are progressing rapidly. Further, computer graphics for displaying numerical calculation results by a super computer are also receiving attention.

Under such circumstances, various video RAMs for storing digital image signals have been developed. The video RAM is a multi-port memory having a random access port and a serial access port, and the multi-port memory used as a frame buffer memory for storing digital image signals in this way is particularly called a video RAM.

A general RAM cannot simultaneously write and read data. Therefore, when the general RAM is used as the video RAM, the CPU (Central Processing Unit) is required to operate the video RA during the image display period.
Since M cannot be accessed, the CPU's access to the video RAM is performed only during the horizontal blanking period. This lowers the data processing speed of the system, so the output of the image signal to the display device and the CPU
A multi-port memory that can be simultaneously and asynchronously accessed is widely used as an image processing memory.

As described above, the video RAM is known as an optimized random access memory for storing image data, and random access and serial access are possible.

FIG. 25 is a block diagram schematically showing the structure of an image processing system using a video RAM. As shown in the same figure, this processing system has a video RAM 1
And a CPU 2, a CRT controller 3, and a CRT 4. Furthermore, the video RAM 1 includes a memory cell array 5, a data transfer bus 6, and a serial register 7. The memory cell array 5 is composed of a DRAM (dynamic random access memory) in which a plurality of memory cells are arranged in a matrix of rows and columns, and is for storing image data. The data transfer bus 6 is for reading out image data stored in the memory cells forming one row of the memory cell array 5 and transferring it to the serial register 7. The serial register 7 includes the same number of register elements as the memory cells forming one row of the memory cell array 5, and the image data stored in these register elements are serially transferred to the outside in response to a serial clock SC supplied from the outside. It is for output.

According to such an image processing system, the memory cell array 5 is connected to the CP via the random access port.
It is randomly accessed by U2 and the image data is written and read. On the other hand, the image data stored in the memory cells forming one row of the memory cell array 5 is read out at once to the serial register 7 via the data transfer bus 6. Then, the image data read to the serial register 7 is output to the outside through the serial access port in response to the serial clock SC. The output serial data is given to the CRT controller 3, and a predetermined image is displayed on the CRT 4 according to the controller 3.

As described above, the video RAM is generally provided with two input / output units, that is, a random access port and a serial access port, and image data is output at high speed through the serial access port, so that the image quality is clear. It is possible to obtain a clear image.

Nowadays, with the increase in the processing amount of image data, a large number of video RAMs provided with a plurality of memory cell arrays are provided. Further, the video RAM is provided with various optional functions according to the user's request.

FIG. 26 is a block diagram showing an example of a conventional video RAM in more detail. As shown in the figure, this video RAM includes a memory cell array 5, data transfer buses 6a and 6b, and serial registers 7a and 7b.
b, and further includes an address buffer 8, a row address recorder 9, a column address recorder 10, a data input / output buffer 11, an I / O bus 12, and a sense amplifier 1.
3, a serial selector 14, a serial data input / output buffer 15, and a timing generator 16.

The address buffer 8 has an address terminal A0.
The address signals received from Aj to Aj are applied to the row address recorder 9, the column address recorder 10 and the like. Row address recorder 9 responds to the row address signal received from address buffer 8 with memory cell array 5
For activating a word line provided in the direction along the row and selecting the desired one row. The column address recorder 10 is responsive to a column address signal received from the address buffer 8 to activate a bit line pair provided in a direction along a column of the memory cell array 5 and select a desired one column. is there. Data input / output buffer 11
Receives data signals received from the data input / output terminals WIO0 to WIOi via the I / O bus 12 from the memory cell array 5
To the data input / output terminals WIO0 to WIOi via the I / O bus 12 and the like. The sense amplifier 13 is for amplifying the data signal read from the memory cell selected by the row address recorder 9 and the column address recorder 10. The serial selector 14 selects one register element forming the serial registers 7a and 7b, and
Data is output from a and 7b to the outside through the serial data input / output buffer 15. Serial data input / output buffer 15 applies the data received from serial registers 7a and 7b to serial data input / output terminals SIO0-SIOi, and conversely receives the data received from serial data input / output terminals SIO0-SIOi. It is for giving to 7b. The timing generator 16 includes a row address strobe signal * RAS, a column address strobe signal * CAS, a data transfer / output enable signal * DT / * OE, a write per bit / write enable signal * WP / * WE, which are external control signals. Function selection signal DSF1
And a DSF2, a serial clock SC, a serial enable signal * SE, etc. to generate an internal control signal to be given to each part of the video RAM. Here, the mark * before the signal indicates that it is a signal of negative logic (it becomes active when it becomes "L" level).

The data transfer buses 6a and 6b are also provided.
Is for mutually transferring data between the memory cell array 5 and the serial registers 7a and 7b, and between the memory cells of the first half of the memory cells forming one desired row of the memory cell array 5. It is composed of an upper data transfer bus 6a for data transfer and a lower data transfer bus 6b for data transfer between the memory cells of the subsequent half. Further, the serial registers 7a and 7b serially output the data stored in the register elements to the outside via the serial data input / output buffer 15, or conversely, from the outside via the serial data input / output buffer 15. The given data is stored and data transfer buses 6a and 6 are provided.
It is for writing those data at a time to the memory cells that form a desired row of the memory cell array S via b, and is associated with the upper data transfer bus 6a and the lower data transfer bus 6b. Side serial register 7a
And a lower serial register 7b.

Although not apparent in FIG. 26, a plurality (i-1) of memory cell arrays 5, data input / output buffers 11, serial data input / output buffers 15 and the like are provided, for example, in units of 4 bits or 8 bits. It is configured such that data is input and output by the.

Next, the old mask register function in this video RAM will be described.

The old mask register function has a function of writing a plurality of memory cell arrays 5 in the case of writing data into the memory cell array 5 through a random access port.
Since data is written only in a part of the memory cell array 5, a part of the input from the data input / output terminals WIO0 to WIOi is masked. The mask data regarding which input is masked is stored in the old mask register 17. That is, the old mask register function means performing write per bit according to the mask data stored in the old mask register 17. The mask data can be fetched from the data input / output terminals WIO0 to WIOi at appropriate times, and desired mask data can be set.

Next, the flash write function in this video RAM will be described. The flash write function is to write the same data to all the memory cells forming one desired row of the memory cell array 5 at the same time.
It is used when clearing the screen on T in a short time.

FIG. 27 is a block diagram showing the details of the serial register 7, the sense amplifier 13 and the like. As shown in the figure, the sense amplifier 13 is connected to a memory cell (not shown) via a bit line pair 18a and 18b, and the transfer gate 1
9 and a common flash light bus 20 to the color register 21. Data input from the outside via the data input / output buffer 11 is stored in the color register 21, and when the control signal FW is applied to the gate of the transfer gate 19, the data stored in the color register 21 becomes , Are simultaneously written in all the memory cells forming one desired row of the memory cell array 5 via the sense amplifier 13.

Next, the data transfer function will be described.
As shown in FIG. 27, each memory cell forming the memory cell array 5 is connected to the serial register 7 via the sense amplifier 13, the data transfer bus 6 and the transfer gate 22. Therefore, a desired one row of the memory cell array 5 is selected by the row address recorder 9,
When the control signal DT is applied to the gate of the transfer gate 22, the data stored in the memory cells forming the selected one row is transferred to the serial register 7. This is called read data transfer.

On the other hand, after the control signal DT is applied to the gate of the transfer gate 22 and the data stored in the serial register 7 is applied to the sense amplifier 13,
When a desired one row of the memory cell array 5 is selected by the row address recorder 9, the data stored in the serial register 7 is transferred to the memory cells forming the selected one row. This is called write data transfer.

In this way, the data transfer function is to perform data transfer between a desired row of the memory cell array 5 and the serial register 7 via the data transfer bus 6.

FIG. 28 is a block diagram showing the overall structure of the portion shown in FIG. As shown in the figure, the transfer gates 22a and 22b provided in the data transfer buses 6a and 6b are configured to be independently controllable on the upper side and the lower side.

Here, a desired one row of the memory cell array 5 is selected by the row address recorder 9, and the data stored in the memory cells forming the one row is sense amplifier 1.
When the control signals DTU and DTL are applied to the gates of the transfer gates 22a and 22b at the same time after being applied to 3, all the data of the selected one row are transferred to the serial registers 7a and 7b. This is called normal read data transfer.

On the other hand, control signals DTU and DTL are simultaneously applied to transfer gates 22a and 22b, and data in serial registers 7a and 7b are applied to sense amplifier 13. After that, a desired one row of memory cell array 5 is transferred to a row address recorder. When selected by 9, all the data in the serial registers 7a and 7b are simultaneously transferred to one row of the selected memory cell array 5. This is called normal write data transfer.

If only the lower control signal DTL is given to the gate of the transfer gate 22b,
Data transfer is mutually performed between the first half of one row of the memory cell array 5 and the lower serial register 7b. On the other hand, the control signal DTU on the upper side is transferred to the transfer gate 2
When supplied to the gate of 2a, the memory cell array 5
Data is mutually transferred between the latter half of one row and the upper serial register 7a.

When data is transferred independently on the upper side and the lower side in this way, one serial register 7
Data can be transferred between the other serial register 7a or 7b and the memory cell array 5 even while data is being output from a or 7b to the outside. This is called split read data transfer or split write data transfer.

FIG. 29 is a timing chart showing a data transfer cycle for determining these transfer modes. First, if the control signal * DT / * OE is "L" at the fall of the external control signal * RAS, the transfer mode is set. At this time, if the external control signals * WB / * WE are “H”, the read data transfer mode is set. If the external control signals * WB / * WE are “L”, the write data transfer mode is set. At this time, the external control signal D
If SF1 is "L", the normal data transfer mode is set, and if external control signal DSF1 is "H", the split data transfer mode is set.

Next, the stop register function will be described. The stop register function is as shown in FIG.
The serial registers 7a and 7b are appropriately divided, and only necessary data out of the data stored in the serial registers 7a and 7b is output to the outside. As a result, the serial registers 7a and 7b can be efficiently accessed when split data transfer is performed, but details will be described later.

FIG. 31 is a time chart showing a load / stop register cycle for determining the number of divisions of the serial register by the stop register function. As shown in the figure, when the control signal * RAS falls, the control signal * CAS is “L” and the control signal * WB is
If / * WE is "L" and the control signal DSF1 is "H", the address signal for determining the division number of the serial registers 7a and 7b is sent from the address terminals A0 to Aj via the address buffer 8 to the stop register 23. Stored in.

For example, the address signals Aj-1 to Aj-
When "0, 1, 1, 1" is input as 4, the serial registers 7a and 7b are divided into 1/4.
FIG. 32 shows the serial registers 7a and 7a in this case.
It is the figure which represented typically how b was accessed.
As shown in the figure, the serial registers 7a and 7b are divided into quarters. These serial registers 7
A unit of data continuously output by a and 7b is called a boundary, and is called a first boundary 24a, a second boundary 24b, a third boundary 24c, and a fourth boundary 24d in order from the lower side of the serial register.
As the serial clock SC is sequentially input, access is sequentially made from the start address TAP1 of the lower serial register 7b determined by the address pointer 25. During this time, split data transfer is performed in the upper serial register 7a, the data of the latter half of the selected one row of the memory cell array 5 is transferred to the upper serial register 7a, and the next start address TA
P2 is set to the address pointer 25. After that, when the final address of the first boundary 24a is accessed, the access is successively made from the start address TAP2 of the upper serial register 7a. Similarly, when the final address of the third boundary 24c is accessed, it is sequentially accessed from the start address TAP3 of the lower serial register 7b.

[0030]

However, the conventional video RAM has the following problems.

First, when it is desired to reset only the stop register 23, the old mask register 17 must be used.
Is also reset. This is because, as shown in FIG. 33, a single reset signal RST is given to both the old mask register 17 and the stop register 23 from the CBR reset signal generation circuit 26 provided inside the timing generator 16. Is. FIG. 34 is a circuit diagram showing an example of the reset signal generating circuit 26 in detail. As shown in the figure, the internal control signal CBR is input to one of the NAND gates 30 via the two inverters 28 and 29, and the other internal control signal DSF1 'is input to the inverter 3 as well.
It is input via 1. Reset signal RST
From this NAND gate 30 to one inverter 32
Is output via. Where the internal control signal CBR
As shown in the time chart of FIG. 35, in the cycle (* CASapefore * RAS cycle) in which the external control signal * RAS falls after the external control signal * CAS falls, the external control signal * RAS is If the control signal * CAS is "L", it becomes "H". On the other hand, the internal control signal DSF1 'is determined by the state of the external control signal DSF1 when the external control signal * RAS falls, and the external control signal DF1 when the external control signal * RAS falls.
If SF1 is "H", it becomes "H" and external control signal *
If the external control signal DSF1 is "L" at the fall of RAS, it becomes "L". Therefore, as shown in FIG.
When the control signal CBR is "H" and the control signal DSF1 'is "L", the reset signal RST becomes "H",
Old mask register 17 and stop register 2
The reset signal RST is applied to both of the registers 3 and 3, and the data stored in these registers 17 and 23 are cleared. On the other hand, as shown in FIG. 36, when the control signal CBR is "H" and the control signal DSF1 'is "H",
Since the reset signal RST becomes “L”, the reset signal RST is not given to both the old mask register 7 and the stop register 23. Therefore, the data stored in these registers 17 and 23 is not cleared and the previous state is maintained.

Secondly, according to the conventional flash write function, all the data for one selected line can be rewritten even if it is desired to partially retain the previous data. As a case where the previous data is partially left, for example, there is a case where only a part of the screen on the CRT is desired to be cleared. Therefore, in order to perform such an operation, it is necessary to individually rewrite data from the random access port, which causes a decrease in image processing speed.

Thirdly, in the conventional split data transfer function and stop register function, there is data read from the memory cell array 5 to the serial register 7 although it is not finally output from the serial register 7. It is to be. Data that is not finally output from the serial register 7 is, for example, as shown in FIG.
As shown in 2, first, the lower serial register 7b
The data in the second boundary 24b corresponds to the data transferred to. In addition, this second boundary 24b
The data inside is accessed and output after the last address of the third boundary 24c is accessed. The data output at this time is the third boundary 2
4c is newly transferred from the memory cell array 5 by split data transfer while 4c is being accessed. In this way, it is useless to transfer the data that is not finally output, and it also consumes unnecessary power.

An object of the present invention is to provide a semiconductor memory device such as a video RAM capable of independently clearing the data stored in the old mask register and the stop register.

Another object of the present invention is to provide a semiconductor memory device such as a video RAM capable of rewriting at high speed only a part of data in a selected row of a memory cell array.

Still another object of the present invention is to provide a semiconductor memory device such as a video RAM in which useless data that is not finally output from the serial register is prevented from being transferred from the memory cell array as much as possible. is there.

[0037]

A semiconductor memory device according to a first aspect of the present invention includes a plurality of memory cell arrays each having a plurality of memory cells arranged in a matrix of rows and columns, and A serial register means having the same number of register elements as the memory cells forming one row of the memory cell array, for serially outputting the data stored in these register elements to the outside, and a memory forming one row of the memory cell array. Transfer means for transferring the data stored in the cells to the register elements constituting the serial register means, input means for simultaneously inputting data from the outside to the plurality of memory cell arrays, and the plurality of memory cell arrays by the input means. One of the memory cell arrays to set whether or not to input data Field mask register means, stop register means for setting a boundary which is a unit of data continuously output by the serial register means, and reset for independently resetting the old mask register means and the stop register means. And means.

A semiconductor memory device according to a second aspect of the present invention is a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns,
Partial flash write means for simultaneously writing data to some of the memory cells forming one desired row of the memory cell array, and data for holding data for the partial flash write means to write to the memory cells Holding means.

In the semiconductor memory device, the partial flash write means is a flash write bus electrically connected to the data holding means and each memory cell forming one row of the memory cell array, and the flash write bus. A switching element interposed between the flash light bus and the flash light bus at the same time; and a masking device connected in series with the switching element and masking a part of the flash light bus.

In the semiconductor memory device, the partial flash write means includes a flash write bus electrically connecting the data holding means and each memory cell forming one row of the memory cell array, and the flash write. And a switching element interposed in each of the buses and capable of arbitrarily opening and closing the flashlight buses.

A semiconductor memory device according to a fifth aspect of the present invention includes a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns,
The memory cell array includes the same number of register elements as the memory cells forming one row, serial register means for serially outputting the data stored in these register elements to the outside, and one desired row of the memory cell array. Partial transfer means for transferring the data stored in a part of the memory cells to the register elements constituting the serial register means.

A semiconductor memory device according to a sixth aspect of the present invention is a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns,
The serial register means has the same number of register elements as the memory cells forming one row of the memory cell array, and serially outputs the data stored in these register elements to the outside, and the data continuously output by the serial register means. Stop register means for setting a boundary, which is a unit of, and data stored in memory cells forming a desired one row of the memory cell array, are divided into a certain number of register elements forming the serial register means. And a division transfer means for transferring the data.

In the semiconductor memory device, a fixed number, which is a unit of data transferred by the division transfer unit, and a boundary, which is a unit of data continuously output by the serial register unit, are matched. .

Further, in the semiconductor memory device, the division transfer means is configured to repeatedly transfer a fixed number of data in the same column of the memory cell array,
The serial register means is configured to repeatedly output the data in the same boundary.

[0045]

According to the semiconductor memory device of the first aspect of the present invention, the old mask register means or the stop register means is independently reset by the reset means. Therefore, it is possible to reset only the stop register means without resetting the old mask register means, for example.

According to the semiconductor memory device of the second aspect of the present invention, the data held in the data holding means constitutes the desired one row of the memory cell array by the partial flash write means. It is simultaneously written to some of the memory cells. Therefore, only a part of the data stored in the memory cell can be rewritten in a short time.

According to the semiconductor memory device of the fifth aspect of the present invention, only the data stored in some of the memory cells forming one desired row of the memory cell array is partially transferred. Is transferred to the register element constituting the serial register means. Therefore, it is possible to transfer only the data that needs to be transferred and not transfer the data that does not need to be transferred.

According to the sixth aspect of the semiconductor memory device of the present invention, the data stored in the memory cells forming one desired row of the memory cell array is divided by the division transfer means into a predetermined number. And is transferred to the register element that constitutes the serial register means. Therefore, it is possible to prevent the data that will not be finally output to the outside by the serial register means from being transferred to the register elements constituting the serial register means as much as possible.

According to the semiconductor memory device of the seventh aspect of the present invention, a desired memory cell array of the memory cell array can be formed.
The data stored in the memory cells forming the row is transferred to the register elements forming the serial register means by dividing it into a fixed number so as to correspond to the boundary. Therefore, the data that is not finally output to the outside by the serial register means is not transferred to the register element that constitutes the serial register means, and only the data that is output to the outside by the serial register means is transferred to the serial register means. Can be transferred to the register element constituting the.

Further, according to the semiconductor memory device of the eighth aspect of the present invention, among the data stored in the memory cells forming one desired row of the memory cell array by the division transfer means, the data is stored in the same column. While only a certain number of data are repeatedly transferred, the data in the same boundary is repeatedly output by the serial register means. Therefore, one boundary and the portion of the memory cell array corresponding to this boundary can be handled as if they were one video RAM.

[0051]

【Example】

[Embodiment 1] FIG. 1 is a block diagram showing the overall structure of a video RAM according to a first embodiment of the present invention. As shown in the figure, this video RAM has a memory cell array 5 having a plurality of memory cells arranged in a matrix of rows and columns, and the same number of memory cells as one row of the memory cell array 5. Register element (not shown)
The serial registers 7a and 7b for outputting the data stored in these register elements to the outside through the serial data input / output buffer 15, and the data stored in the memory cells forming one row of the memory cell array 5.
Data transfer buses 6a and 6b for transferring to the register elements forming serial registers 7a and 7b are included.
Although not clear in the drawing, the memory cell array 5
Etc. are provided in plural (i-1).

The video RAM further includes an old mask register 17 for setting which memory cell array 5 of the plurality of memory cell arrays 5 is externally input with data, and serial registers 7a and 7b. A stop register 23 for setting a boundary, which is a unit of data to be output, and a CBR reset signal generation circuit 50 for independently resetting the old mask register 17 and the stop register 23 are included. The reset signal generating circuit 50
Are provided inside the timing generator 16.

In addition to this, the video RAM includes an address buffer 8, a row address recorder 9, a column address recorder 10, a data input / output buffer 11, an I / O bus 12, a sense amplifier 13, a serial selector 14, and an address pointer 25. Including. Note that the same parts as those in FIG. 26 showing the conventional video RAM indicate the same or corresponding parts as in the conventional one.

FIG. 2 is a block diagram showing the reset signal generating circuit 50, the old mask register 17 and the stop register 23 of the video RAM shown in FIG. As shown in the figure, the reset signal generation circuit 50
Is configured to receive internal control signals CBR, TSF1 'and TSF2' generated by timing generator 16 and independently provide reset signals RST1 and RST2 to old mask register 17 and stop register 23, respectively. . This reset signal generation circuit 50 is the reset means, which is the greatest feature of this embodiment.

FIG. 3 is a circuit diagram showing the reset signal generating circuit 50 more specifically. As shown in the figure, the control signal CBR is input to one of the NAND gates 51 and also to one of the other NAND gates 52. The control signal DSF1 'is input to the other of the former NAND gates 51 via the inverter 53. The control signal DSF2 'is transmitted through the inverter 54 to the latter NA.
It is input to the other side of the ND gate 52. On the other hand, reset signals RST1 and RST2 from these NAND gates 51 and 52 are passed through inverters 55 and 56.
Is being output.

Here, the operation of the old mask register by the video RAM will be described.

FIG. 4 is a time chart showing a load old mask register cycle for loading the mask data into the old mask register 17. As shown in the figure, when the external control signal * RAS falls, the external control signal * CAS is "H" and the external control signal DS is
If F1 is "H", the old mask mode is set. Thereafter, when the external control signal DSF1 is "L" at the fall of the external control signal * CAS, mask data is stored in the old mask register 17 from the data input / output terminals WIO0 to WIOi via the data input / output buffer 11. It If the write per bit cycle as shown in the time chart of FIG. 5 is executed in this state, the write per bit is executed according to the mask data. That is, when the external control signal * RAS / * WE is "L" at the fall of the external control signal * RAS, the write per bit mode is set. At the same time, when the external control signal * RAS falls, the row address is stored in the row address recorder 9 from the address terminals A0 to Aj via the address buffer 8. Then, when the external control signal * CAS falls, the column address is stored in the column address recorder 10 from the address terminals A0 to Aj via the address buffer 8. Data is transferred from the data input / output terminals WIO0 to WIOi to the data input / output buffer 11, the I / O bus 12, and the sense amplifier 13 while the external control signal * WB / WE is "L".
Is written in one memory cell selected by the row address recorder 9 and the column address recorder 10 via.
At this time, a plurality (i-1) of memory cell arrays 5 are provided, but a part of the data input / output buffer 1 is used in accordance with the mask data stored in the old mask register 17.
Since 1 is in a non-conducting state, no data is written in the memory cells that form part of the memory cell array 5.

Next, the stop register operation by this video RAM will be described. FIG. 6 is a time chart showing a load / stop register cycle for loading boundary-related data into the stop register. As shown in the figure, when the external control signal * RAS falls, the external control signal * CAS is "L", the external control signal * WB / * WE is "L", and the external control signal DSF is
If 1 is "H", the stop register mode is entered.

Next, the input serial clock SC
In response to this, the address pointer 25 gives the serial selector 14 the addresses of the serial registers 7a and 7b to be read. According to this given address
The serial selector 14 selects the register element forming the serial registers 7a and 7b from which data should be read. Then, the data stored in the selected register element is output to the serial data input / output terminals SIO0 to SIOi via the serial data input / output buffer 15.

After that, when the address of the register element selected by the serial selector 14 reaches the final address in the boundary, a new start address is given from the address pointer 25 to the serial selector 14. Since the other details are the same as the conventional ones, the description thereof will be omitted.

According to such a video RAM, the reset signals RST1 and RST2 are independently provided to the old mask register 17 and the stop register 23, respectively.
Therefore, for example, when it is desired to clear only the data about the boundary stored in the stop register 23 and continue to use the mask data stored in the old mask register 17, the stop register 23 only needs to be used. Reset signal RST2
Should be given.

The reset operation will now be described in more detail with reference to FIGS. 3, 7 and 8. In FIG. 3, the internal control signal CBR is the timing generator 16
The signal generated by the external control signal * RAS falls after the external control signal * CAS falls (* CASbefore *), as shown in the time chart of FIG.
In the RAS cycle), it is a signal that becomes "H" when the external control signal * RAS falls. Internal control signal DSF
1'is also a signal generated by the timing generator 16 and its logic state is determined by the logic state of the external control signal DSF1 at the fall of the external control signal * RAS. In other words, when the external control signal DSF1 is "H" at the fall of the external control signal * RAS, the internal control signal DSF1 'becomes "H", while the external control signal * as shown in the time chart of FIG. At the fall of RAS,
If the external control signal DSF1 is "L", the internal control signal D
SF1 'becomes "L". In addition, the internal control signal DSF
2'is also a signal generated by the timing generator 16 and its logical state is determined by the logical state of the external control signal DSF2 at the falling edge of the external control signal * RAS. That is, as shown in the time chart of FIG. 7, if the external control signal DSF2 is "L" at the fall of the external control signal * RAS, the internal control signal DSF2 'becomes "L", while the time of FIG. As shown in the chart, when the external control signal * RAS falls, if the external control signal DSF2 is "H", the internal control signal DSF2 'becomes "H".

Therefore, as shown in the time chart of FIG. 7, when the internal control signal CBR is "H", the internal control signal DSF1 'is "H" and the internal control signal DSF is
If 2'is "L", the reset signal RST1 is "L".
And the reset signal RST2 becomes "H". Therefore, the old mask register 17 is not reset and the previous mask data is maintained as it is. On the other hand, the stop register 23 is reset and the stored data regarding the boundary is cleared.

On the other hand, as shown in the time chart of FIG.
When the internal control signal CBR is "H", the internal control signal DS
When F1 'is "L" and the internal control signal DSF2' is "H", the reset signal RST1 becomes "H" and the reset signal RST2 becomes "L". Therefore, the old mask register 17 is reset and the mask data stored therein is cleared, but the stop register 23 is not reset and the data related to the previous boundary is maintained as it is.

Further, although detailed description is omitted, when the internal control signal CBR is "H", the internal control signal DSF1 '.
And DSF2 'are both "L", the reset signals RST1 and RST2 are both "H". On the other hand, when the internal control signal CBR is "H" and both the internal control signals DSF1 'and DSF2' are "H",
The reset signals RST1 and RST2 both become "L".

FIG. 9 is a list showing the above results by using the external control signals DSF1 and DSF2. As is apparent from the figure, in the * CAS before * RAS reset cycle, when both the external control signals DSF1 and DSF2 are "H", neither the old mask register 17 nor the stop register 23 is reset. External control signal DSF1 is "H", and external control signal D
When SF2 is "L", the old mask register 17
Is not reset, but the strobe register 23 is reset. When the external control signal DSF1 is "L" and the external control signal DSF2 is "H", the old mask register 17 is reset but the stop register 23 is not reset. External control signals DSF1 and DSF
When both 2 are "L", old mask register 1
7 and the stop register 23 are both reset.

As described above, according to this video RAM, the old mask register 17 and the stop register 2
3 independently of reset signals RST1 and R
Reset signal generation circuit 50 capable of applying ST2
Is provided, for example, the stop register 23
You can only reset the * CAS Before *
Even when the RAS reset cycle is executed, the mask data stored in the old mask register 17 can be continuously used as it is. Therefore, even when the * CAS before * RAS reset cycle is executed as in the conventional case, it is not necessary to write the same mask data to the old mask register 17 again.

[Second Embodiment] FIG. 10 is a block diagram showing the entire structure of a video RAM according to a second embodiment of the present invention. As shown in the figure, this video RAM has a memory cell array 5 having a plurality of memory cells arranged in a matrix of rows and columns, and a sense amplifier 13 or the like in all columns of the memory cell array 5. And a color register 21 for holding data to be written in a memory cell via the flash write bus 20.

The video RAM further includes serial registers 7a and 7b for outputting data read from a desired row of the memory cell array 5 to the outside through the serial data input / output buffer 15, and a desired 1 of the memory cell array 5. A data transfer bus 6 for transferring data between the rows and serial registers 7a and 7b is included. In addition, the portions shown by the same reference numerals as those of the conventional video RAM shown in FIG. 26 are the same or corresponding portions.

FIG. 11 is a circuit diagram showing in more detail the sense amplifier 13, flash write bus 20, data transfer bus 6, serial registers 7a and 7b, etc. of this video RAM. As shown in the figure, the sense amplifier 13 is connected to the color register 21 via the transfer gate 19 and the common flash write bus 20, but in this embodiment, the transfer gate 19 and the flash write bus 20 are further connected. A transmission gate 57 is connected between the two. These transfer gates 19 are conventional,
All are controlled simultaneously by one control signal FW.
On the other hand, the transmission gate 57, which is the first feature of this embodiment, has a pair of control signals CMF for every fixed number.
0 and * CMF0 to CMFn and * CMFn.

On the other hand, the transfer gate 22 and the transmission gate 58 are connected in the middle of the data transfer bus 6. These transfer gates 22 are also conventional, and are all controlled simultaneously by one control signal DT. The transmission gate 58 has a pair of independent control signals CM for each fixed number.
DT0 and * CMDT0 to CMDTm and * CMD
Simultaneously controlled by Tm.

The transmission gate 57 provided in the flash write bus 20 is a means for masking the flash write bus 20, and these transmission gates 57 control signals DMF0 and * CMF0 to CMFn supplied from the control signal generation circuit 59. And * CMFn. On the other hand, the transmission gate 58 provided in the data transfer bus 6 is
These transmission gates 58 are means for masking the data transfer bus 6, and these transmission gates 58 are provided with control signals CMDT0 and * CMDT0 to * CMDT0.
Controlled by CMDTm and * CMDTm. Therefore, the data transfer bus 6 in this embodiment transfers the data stored in some of the memory cells forming one desired row of the memory cell array 5 to the register elements forming the serial registers 7a and 7b. It is a partial transfer means for transferring.

Next, the partial flash write operation by this video RAM will be described. Transmission gate 57 connected in the flashlight bus 20
When "H" is given as the control signals CMF0 to CMFn, and "L" is given as the control signals * CMF0 to * CMFn, it becomes conductive. On the other hand, when "L" is applied as the control signals CMF0 to CMFn and "H" is applied as the control signals * CMF0 to * CMFn, these transmission gates 57 are rendered non-conductive.

Therefore, some of these transmission gates 57 are made conductive and the others are made non-conductive, and these transmission gates 57 are made conductive.
When the control signal FW is applied to all the transfer gates 19 connected in series with the data, the data stored in the color register 21 is written in the memory cells in the column in which the transmission gate 57 is in the conductive state. The data stored in the color register 21 is not written to the memory cell in the column in which the transmission gate 57 is in the non-conductive state, but the previously written data is maintained as it is.

According to this video RAM, since flash writing can be partially performed, it is possible to clear a part of the screen on the CRT in a short time.

12 and 13 show which transmission gate 5 in the flashlight mode.
7 is a time chart showing a load column mask address cycle for determining whether 7 is made conductive or non-conductive.

For example, as shown in FIG. 12, when the external control signal * RAS falls, the external control signal * WB / * WE
Is set to "L" and the external control signal DSF1 is set to "H" to set the flash write mode. Then, when the external control signal * CAS falls, the external control signal DSF1
If is "H", the column mask address may be loaded from the address terminals A0 to Aj. In this case, if the external control signal DSF1 is "L" at the fall of the external control signal * CAS, the flash write bus 20
Normal flashlight is executed without masking.

Alternatively, as shown in FIG. 13, when the external control signal * RAS falls, the external control signal * WB / * WE
Is "L" and the external control signal DSF1 is "H", the flash write mode is set, and whether or not to mask the flash write bus 20 is determined according to the logical state of the external control signal DSF2 at this time. You may do it. In this case, if the external control signal DSF2 is "H" at the fall of the external control signal * RAS, then at the fall of the external control signal * CAS, the address terminals A0 to A0.
The column mask address is loaded from Aj.

Further, FIG. 14 is a time chart showing a load column mask address cycle in the case where a column mask address is loaded in advance before the flash write mode is set. As shown in the figure, in the * CAS before * RAS cycle, the external control signal * R
At the fall of AS, if the external control signals * WB / * WE are "L" and the external control signal DSF1 is "H" and the external control signal DSF2 is "H", the address terminals A0 to Aj
The column mask address may be loaded from. In this case, even if the load column mask address cycle as shown in FIG. 12 or 13 is subsequently executed to set the flash write mode, the column mask address at the falling edge of the external control signal * CAS is It will be ignored.

Next, the partial data transfer operation by this video RAM will be described. The column mask address is loaded by executing the load column mask address cycle shown in FIG. 14 in the same manner as described above, and a part of the data transfer bus 6 is masked according to this column mask address. That is, control signals CMDT0 to CMDTm are applied to a part of these transmission gates 58.
"H" is given as the control signal * CMD at the same time
When "L" is given as T0 to * CMDTm, those transmission gates 58 are rendered conductive.
On the other hand, "L" is given as the control signals CMDT0 to CMDTm, and at the same time, the control signals * CMDT0 to * CMD
When "H" is applied as Tm, those transmission gates 58 are turned off.

As described above, since a part of the data transfer bus is electrically isolated by the transmission gate 58, the data transfer bus 6 is disconnected even if the control signal DT is applied to all the transfer gates 22. Partial memory cell array 5 and serial register 7
No data transfer is performed between a and 7b. Therefore, from the memory cell array 5 to the serial register 7a
In the read data transfer for transferring the data to and 7b, some of the data in the serial registers 7a and 7b are rewritten, but the other data is maintained in the previous state.

Then, by the stop register function, a part of the data stored in the serial registers 7a and 7b is output to the outside via the serial data input / output buffer 15. Only the data to be output from the serial registers 7a and 7b can be transferred from the memory cell array 5 to the serial registers 7a and 7b, and finally, the data that is not output from the serial registers 7a and 7b is possible. As far as possible, serial registers 7a and 7
It is possible not to transfer to b. For this reason, wasteful data transfer is not performed, and power consumption associated with data transfer can be reduced.

Data transfer by this video RAM is as follows:
In addition to read data transfer and write data transfer, split data transfer and normal data transfer, there are data transfer with a column mask and data transfer without a column mask.

As shown in the time chart of FIG. 15, the read data transfer mode and the write data transfer mode, and the split data transfer mode and the normal data transfer mode are the external control signal at the falling edge of the external control signal * RAS, respectively. It is determined by the logical state of * WB / * WE and the logical state of the external control signal DSF1. Further, the data transfer mode with the column mask and the data transfer mode without the column mask are different from each other in the external control signal DSF at the falling edge of the external control signal * RAS.
2 logic states.

That is, when the external control signal * DT / * OE is "L" at the fall of the external control signal * RAS, the data transfer mode is set. If the external control signal * WB / WE is "H" at the fall of the external control signal * RAS, the read data transfer mode is set, and the external control signal * WB / *
If WE is "L", the write data transfer mode is set.
If the external control signal DSF1 is "H" at the fall of the external control signal * RAS, the split data transfer mode is set, and if the external control signal DSF1 is "L", the normal data transfer mode is set. In addition, external control signal * R
If the external control signal DSF2 is "H" at the fall of AS, the data transfer mode with the column mask is set, and if the external control signal DSF2 is "L", the normal data transfer mode without the column mask is set.

In this embodiment, both the flash write bus 20 and the data transfer bus 6 are
The transfer gate 19 or 22 and the transmission gate 57 or 58 are connected in series.
For example, in the read data transfer mode,
This is because the data in the memory cell array 5 can be efficiently transferred to the serial registers 7a and 7b by making the transmission gate 58 conductive after making the transmission gate 22 conductive. on the other hand,
This is because in the write data transfer mode, data can be smoothly transferred from the serial registers 7a and 7b to the memory cell array 5 by making the transfer gate 22 conductive after making the transmission gate 58 conductive. . Therefore, it is possible to partially perform flash write or partially perform data transfer without the need for the transfer gates 19 and 22.

[Third Embodiment] FIG. 16 is a block diagram showing the entire structure of a video RAM according to a third embodiment of the present invention. As shown in the figure, this video RAM has a memory cell array 5 having a plurality of memory cells arranged in a matrix of rows and columns, and a part of the memory cells forming one row of the memory cell array 5. Partial flash write bus FW for writing data in a fixed number of units
B0 to FWBn and these partial flash write buses F
Control signal generation circuit 6 for controlling WB0 to FWBn
1 and these partial flash write buses FWB0 to FW
A color register 21 for holding data to be written in the memory cell of the memory cell array 5 via Bn,
Further, partial data transfer buses PDTB0 to PDTBm for mutually transferring data in a fixed number unit between some of the memory cells forming one row of the memory cell array 5 and the serial registers 7a and 7b, A control signal generation circuit 62 for controlling these partial data transfer buses PDTB0 to PDTBm is included. Note that, in FIG. 16, the same reference numerals as those in FIG. 26 showing the conventional video RAM indicate the same or corresponding portions.

FIG. 17 shows the sense amplifier 13 of the video RAM and the partial flash write buses FWB0 to FWB.
3 is a circuit diagram showing in more detail parts such as n, partial data transfer buses PDTB0 to PDTBm, and serial register 7. As shown in the figure, the sense amplifier 13 is connected to the color register 21 via the flash write bus 20 common to the individual transfer gates 63 for each column. Different from the conventional ones, these transfer gates 63 are given the same control signals FW0 to FWn in a fixed number unit.

On the other hand, the sense amplifier 13 is connected to the serial register 7 via the transfer gates 64 and 65 for each column. The same control signals DTA0 to DTAm and DTS0 to DTSm are applied to the transfer gates 64 and 65 in a fixed number unit.

Next, the partial flash write operation by this video RAM will be described. Also in the case of this video RAM, the column mask address is loaded when the load column mask address cycle shown in FIG. 12, FIG. 13 or FIG. 14 is executed as in the second embodiment described above. Control signals FW0 to FW are supplied to the transfer gate 63 in accordance with the loaded column mask address.
When "H" is given as n, the transfer gates 63 are turned on, while the control signals FW0 to F
When "L" is given as Wn, those transfer gates 63 are turned off. Thus, when only some of the transfer gates 63 are conductive,
When the flash write is executed as in the conventional case, the data of the color register 21 is written in the memory cell of the memory cell array 5 via the transfer gate 63 and the sense amplifier 13 which are in the conductive state. On the other hand, in the memory cell in the column corresponding to the portion where the transfer gate 63 is in the non-conducting state, the previous data is maintained as it is.

Next, the partial data transfer operation by this video RAM will be described. In this case as well, FIG.
When the load column mask address cycle shown in FIG. 13 or 14 is executed, the column mask address is loaded. Next, the data transfer cycle shown in the time chart of FIG. 15 is executed, and the presence or absence of the column mask is selected. That is, the external control signal * RA
If the external control signal DSF2 is "H" at the fall of S, column masking is performed, and the external control signal DS
If F2 is "L", it means that the column mask is not used.

First, the external control signal DSF2 is "H",
When column masking is to be performed, the partial data transfer buses PDTB0 to PDTB0 to PDTB0 according to the previously loaded column mask address.
Control signals DTA0 to DTBm and DTS0 to transfer gates 64 and 65 provided in PDTBm.
~ DTSm is given. That is, the control signal DTA0
When "H" is applied to .about.DTA, m and DTS0 to DTSm, transfer gates 64 and 65 are rendered conductive. On the other hand, control signals DTA0 to DT
When "L" is applied to Am and DTS0 to DTSm, transfer gates 64 and 65 are turned off. Therefore, the transfer gate 6
Partial data transfer bus PD in which 4 and 65 are conductive
Data transfer is performed in TB0 to PDTBm, but data transfer is not performed in partial data transfer buses PDTB0 to PDTBm in which transfer gates 64 and 65 are non-conductive.

On the other hand, the external control signal DSF2 is "L".
When the column mask is not used, all the data transfer buses DTB0 to DTB0 regardless of the column mask address.
Data transfer is performed in DTBm.

As described above, since only a part of the data can be transferred from the desired one row of the memory cell array 5 to the serial registers 7a and 7b, the stop register function finally causes the serial registers 7a and 7b to be transferred.
Data that is not output from b can be prevented from being transferred as much as possible. Therefore, it is possible to reduce power consumption associated with data transfer.

In this embodiment, two transfer gates 64 and 65 are provided in one partial data transfer bus PDTB0 to PDTBm.
This is for efficient data transfer according to the read data transfer mode and the write data transfer mode. That is, in the read data transfer mode, it is desirable to make the transfer gate 64, which is the upstream side of the data transfer, conductive, and then make the transfer gate 65, which is the downstream side thereof, conductive. On the other hand, in the write data transfer mode, It is desirable that after the transfer gate 65 on the upstream side of the data transfer is turned on, the transfer gate 64 on the downstream side is turned on.

[Fourth Embodiment] FIG. 18 is a block diagram showing the entire structure of a video RAM according to a fourth embodiment of the present invention. As shown in the figure, the video RAM serially stores data read from a desired row of the memory cell array 5 including a plurality of memory cells arranged in a matrix of rows and columns. Data that is serially output to the outside via the data input / output buffer 15 or data that is externally input from the outside via the serial data input / output buffer 15 is stored in the memory cell array 5.
Serial register 7 for simultaneously writing into a desired one row and a divided data transfer bus SDTB0 for mutually transferring data between the memory cell array 5 and the serial register 7.
To DTBm and these divided data transfer buses SDTB0 to SDTB0
A control signal generation circuit 66 for controlling SDTBm,
Stop register 23 and address pointer 25 for causing the serial register 7 to operate as a stop register
Including and

The video RAM further includes an address buffer 8, a row address decoder 9, a column address decoder 10, a data input / output buffer 11, an I / O bus 12, a sense amplifier 13, a serial selector 14, and a serial data input / output buffer 15. , Timing generator 16,
Old mask register 17 and color register 2
Including 1. Note that the same reference numerals as those in FIG. 26 showing the conventional video RAM indicate the same or corresponding portions as those of the conventional one.

FIG. 19 is a circuit diagram showing in more detail the sense amplifier 13, divided data transfer buses SDTB0 to SDTBm, and serial register 7 of the video RAM. As shown in FIG.
Can be divided up to (m + 1) times by the stop register function. That is, the serial register 7 can be divided into a maximum of (m + 1) boundaries. On the other hand, each divided data transfer bus SDTB0 to SDTB0
A transfer gate 67 is provided in SDTBm, and these transfer gates 67 are (m +
1) It is possible to independently control every fixed number so as to correspond to the boundary when divided into pieces. That is, the divided data transfer buses SDTB0 to SDTBm
Is a division transfer unit that divides the data stored in the memory cells forming one desired row of the memory cell array 5 into the register elements forming the serial register 7 by a predetermined number and transfers the divided pieces.

First, the divided data transfer operation and stop register operation by this video RAM will be described. In order to simplify the description, the memory cell array 5
Is a 1 M-bit unit composed of 1024 rows × 1024 columns, and the serial register 7 can be divided into up to 32 boundaries by the stop register function.

In FIG. 20, the serial register 7 and the divided data transfer buses SDTB0 to SDTBm are respectively set to 4
It is a schematic diagram for demonstrating operation | movement at the time of dividing | segmenting into one part.

First, the serial register 7 is divided into quarters by the load / stop register cycle shown in FIG. 6, and the first boundary 68 and the second boundary 6 are divided.
9, third boundary 70 and fourth boundary 71
To set.

Then, the divided data transfer bus SDT is executed by a load / transfer boundary cycle as shown in FIG.
B0 to SDTBm are divided into quarters, and each is independently controlled by control signals DT0 to DT31.

The divided data transfer buses SDTB0 to SDTB
Since TBm can be divided into a maximum of 32 pieces like the serial register 7, the divided data transfer buses SDTB0 to SDT0
The transfer gate 67 provided in Bm has 3
Two control signals DT0 to DT31 are provided. Therefore, in this case, the control signals DT0 to DT7, DT
8-DT15, DT16-DT23 and DT24-D
T31 is the same signal.

Here, divided data transfer buses SDTB0-SDTB0-
The unit of data transferred by SDTBm is particularly called a "transfer boundary". This transfer boundary is, as shown in the time chart of FIG. 21, * CAS before * R.
In the AS cycle, if the external control signal * WB / * WE is "L", the external control signal DSF1 is "H", and the external control signal DSF2 is "H" at the fall of the external control signal * RAS, The transfer boundary is loaded.

The split read data transfer mode is set by the data transfer cycle shown in FIG. 15, and the control signals DT0 to DT7 are first set in accordance with the transfer boundary.
When "H" is given to the transfer gate 67 as the data, the data of Xa which is a quarter of the desired one row of the memory cell array 5 is divided into the divided data transfer buses SDTB0 to SDT.
The first boundary 6 of the serial register 7 by B7
8 and then the start address TAP1 is specified which specifies the position to be accessed first in the first boundary 68 when the external control signal * CAS falls.

In response to the serial clock SC, the serial selector 14 sequentially selects from the start address TAP1 and the data of the first boundary 68 is output to the outside via the serial data input / output buffer 15. While the first boundary 68 is being accessed, split data transfer is performed, and the data in the Xb row of the memory cell array 5 is transferred to the divided data transfer bus SDTB8.
~ SDTB15 transfers to the second boundary 69, and the start address TAP2 in the second boundary 69 is determined in the same manner as described above.

After that, when the final address END1 of the first boundary 68 is accessed, the start address TAP2 of the second boundary 69 is subsequently accessed. Similarly, in response to the serial clock SC, this second
Boundary 69 data of start address TAP2
The data in the Xc row of the memory cell array 5 is transferred by the divided data transfer buses SDTB24 to SDTB31 to the fourth data while the data is sequentially output from the divided data transfer buses SDTB24 to SDTB31.
Is transferred to the boundary 71 of the start address TAP
3 is set.

When the final address END2 of the second boundary 69 is accessed, the start address TAP3 of the fourth boundary 71 is subsequently accessed.

According to such divided data transfer operation and stop register operation, the boundary which is the unit of data continuously output from the serial register 7 and the unit of data which is transferred by the divided data transfer buses SDTB0 to SDTBm. Since the transfer boundary is matched, almost no data that is finally output by the serial register 7 is transferred to the serial register 7, and data is transferred only to the extent that wasteful data transfer is not performed. The associated power consumption is reduced.

Next, the serial register 7 is divided into quarters and the divided data transfer buses SDTB0 to SDTBm are divided into eight.
The operation in the case of being divided into ones will be described. FIG. 22
[Fig. 3] is a schematic diagram for explaining the operation in this case.

First, the boundary of the stop register 7 is loaded by the load / stop register cycle shown in FIG. 6, and the serial register 7 is divided into quarters. On the other hand, the load / transfer boundary shown in FIG.
The transfer boundary is loaded by the cycle, and the divided data transfer buses SDTB0 to SDTBm are divided into ⅛.

Next, when the split read data transfer mode is set by the data transfer cycle shown in FIG. 15, first, when the data of Xa of the memory cell array 5 is divided into 1/4 of the serial register 7 by the divided data transfer buses SDTB0 to SDTB7. First Boundary 6 in
8 is transferred to the portion corresponding to the start address TAP
1 is set. Then, in response to the serial clock SC, data is sequentially output from the start address TAP1. Split data transfer is performed while the first boundary 72 in the 1/8 division is being accessed, and the data in the Xb row of the memory cell array 5 is divided into the second boundary 69 in the 1/4 division. Data is transferred by the data transfer buses SDTB8 to SDTB15,
The start address TAP2 is determined.

After that, when the final address END1 of the first boundary 72 at the time of 1/8 division is accessed, the fourth boundary 7 at the time of 1/8 division continues.
5 are sequentially accessed from the start address TAP2. Similarly, in response to the serial clock SC, 1/8
While the fourth boundary 75 at the time of division is being accessed, split data transfer is performed, and the data in the Xc row of the memory cell array 5 is transferred to the divided data transfer bus SD.
It is transferred to a portion corresponding to the fourth boundary 71 at the time of the quarter division by TB24 to SDTB31, and the start address TAP3 is determined.

When the final address END2 of the fourth boundary 75 at the time of 1/8 division is accessed, the seventh boundary 7 at the time of 1/8 division is continuously accessed.
8 are sequentially accessed from the start address TAP3.

As described above, according to this video RAM, the division number of the serial register 7 and the data transfer bus SD
Since the number of divisions TB0 to SDTBm can be set independently, the boundary of the serial register and the transfer boundary can be matched, or the transfer boundary can be made larger than the boundary of the serial register, or vice versa. It is also possible to make the transfer boundary smaller than the register boundary.

FIG. 23 is a circuit diagram showing the address pointer 25 of the video RAM shown in FIG. 18 in more detail.

As shown in the figure, the address pointer 25 includes 10 counter units 74,
It is composed of a counter circuit capable of counting up to 4 counts. Note that this counter circuit is for the case where the serial register 7 is composed of 1024 register elements. In FIG. 23, the address signal TA
0 to TA9 are for defining the start address TAP, and are stored in the counter unit 74 from the address terminals A0 to Aj via the address buffer 8 at the rise of the control signal DTA. The control signal SCT has the same phase as the serial clock SC, and is a signal for sequentially incrementing this counter. Further, in this counter circuit, a carry signal is applied from the lower counter unit 74 to the upper counter unit 74.

Here, the difference from the conventional counter circuit is that a transmission gate 75 is provided on the carry output line of the counter unit 74 which takes in the address signals TA4 to TA9, and a transmission gate 76 is provided on the input line of the control signal SCT. That is the point. In these transmission gates 75 and 76, the control signals BU0 to BU4 are "H" and the control signals * BU0 to BU0.
If BU4 is "L", a carry is applied from the lower counter unit 74 to the upper counter unit 74 in response to the control signal SCT. On the other hand, "L" is given as the control signal BU0 of the transmission gates 75 and 76, "H" is given as the control signal * BU0, and "L" is given as the control signal BU1 and "L" is given as the control signal * BU1. If H "is given, the upper two counter units 74, which take in the address signal TA8, do not change even if the serial clock SC is input. That is, this counter circuit can count up to 256 counts.

Here, when "L" is applied as control signals BU0 and BU1 and "H" is applied as control signals * BU0 and BU1, transfer is performed by the load / transfer boundary cycle shown in FIG. The boundary is loaded and the divided data transfer buses SDTB0-STB0-S
It is assumed that DTBm is divided into quarters, the boundary of the serial register 7 is loaded by the load / stop register cycle shown in FIG. 6, and the serial register 7 is divided into quarters. In this case, the counter circuit shown in FIG. 23 has two counter units 7 higher than the counter unit 74 which takes in the control signal TA8.
Since 4 does not change even when the serial clock SC is input, it is possible to count up to 256 counts, which is 1/4 of 1024 that can be originally counted by this counter circuit.

Therefore, after the data is transferred from the desired one row of the memory cell array 5 to the first boundary 68 of the serial register at the time of the quarter division by the data transfer cycle shown in FIG. When the serial access is performed in response to, the final address of the first boundary 68 is accessed soon. While the first boundary 68 is being accessed, the transfer operation is not performed even once, and the serial clock S
When the serial access continues to be performed in response to C, when the last address of the first boundary is accessed, the start address TA of the first boundary 68 is again generated.
P1 is accessed.

Such operation is performed in a quarter of the video RAM.
Is treated as one video RAM. For this reason, the video R
It is possible to handle part of the AM as if it were one video RAM.

[Embodiment 5] FIG. 24 is a block diagram showing an overall structure of a video RAM according to a fifth embodiment of the present invention. As shown in the figure, this video RAM includes a plurality (i + 1) of memory cell arrays 5 each having a plurality of memory cells arranged in a matrix of rows and columns. The serial register 7 has the same number of register elements as the memory cells to be configured and outputs the data stored in these register elements to the outside through the serial data input / output buffer 15.
including.

The video RAM further includes an old mask register (OMR) 17 for setting which memory cell array 5 of the plurality of memory cell arrays 5 is externally input with data, and a serial register 7. It includes a stop register 23 and an address pointer 25 for setting a boundary which is a unit of continuously output data, and a reset signal generation circuit 50 for independently resetting the old mask register 17 and the stop register 23.

This video RAM is further provided with a flash write bus (FW bus) commonly connected to all columns of each memory cell array 5 via a sense amplifier 13 or the like.
20, a means (FWM) for masking a fixed number of each flash write bus 20, a control signal oscillation circuit (CONT.) 59 for controlling each mask means, and each via the flash write bus 20. Memory cell array 5
Color register 21 for holding data to be written in the memory cell.

The video RAM further includes divided data transfer buses SDTB0 to SDTB for mutually transferring data between each memory cell array 5 and each serial register 7.
m and these divided data transfer buses SDTB0 to SDTB
Control signal generation circuit (CONT.) 6 for controlling m
6, a means (DTM) for masking each of the divided data transfer buses SDTB0 to SDTBm in a fixed number, and a control signal generating circuit (CONT.) For controlling each masking means.
60 and 60 are included.

That is, this embodiment is a combination of the above-mentioned first, second and fourth embodiments.

In addition to this, the video RAM also includes an address buffer 8, a row address decoder (RAD) 9, a column address decoder (CAD) 10, and a data input / output buffer (I
/ O. BUF) 11, I / O bus 12, sense amplifier 1
3, a serial selector 14, a serial data input / output buffer (I / O.BUF) 15, and a timing generator 16. Incidentally, the same parts as those in FIG. 26 showing the conventional video RAM indicate the same or corresponding parts as the conventional one.

Here, the reset signal generating circuit 50 is similar to that shown in FIG.
Internal control signals CBR, TSF1 'generated by
And TSF2 ', the old mask register 17
And the stop register 23 are independently supplied with the reset signals RST1 and RST2. The reset signal generation circuit 50 is the reset means which is the first feature of this embodiment.

Similarly to the one shown in FIG. 11, the sense amplifier 13 is connected to the color register 21 via the transfer gate 19 and the common flash write bus 20, but the transfer gate 19 and the flash write bus 20 are connected to each other. The transmission gate 57 between is connected. These transfer gates 19 are conventional and are all controlled simultaneously by one control signal FW. On the other hand, the transmission gate 57 has a pair of control signals CMF0 and * CMF0 to CMFn generated by the control signal generation circuit 59.
And * CMFn to control every fixed number.
These transmission gates 57 are mask means (FWM) for masking the flash write bus 20 which is the second feature of this embodiment. On the other hand, the transfer gate 22 and the transmission gate 58 are connected to an intermediate portion of the data transfer bus 6. These transfer gates 22 are also conventional, and are all controlled simultaneously by one control signal DT. These transmission gates 58 have a pair of control signals CMDT0 and * generated by a control signal generation circuit 60.
It is controlled by CMDT0 to CMDTm and * CMDTm simultaneously for every fixed number. These transmission gates 58 are mask means (DTM) for masking the data transfer bus 6 which is the third feature of this embodiment.

Similarly to the one shown in FIG. 19, each serial register 7 has (m +
1) It can be divided up to a fraction. That is, the serial register 7 can be divided into a maximum of (m + 1) boundaries. On the other hand, the transfer gate 6 is provided in each of the divided data transfer buses SDTB0 to SDTBm.
7 are provided, and these transfer gates 67 are provided.
Can be independently controlled for each fixed number so as to correspond to the boundary when divided into (m + 1). These divided data transfer buses SDTB0 to SDTBm
Is a fourth characteristic of this embodiment, in which the data stored in the memory cells forming one desired row of the memory cell array 5 is divided into a certain number of register elements and transferred to the register elements forming the serial register 7. It is a division transfer means.

Next, the operation of the video RAM will be described. Since the old mask register function by the old mask register 17, the stop register function by the stop register 23 and the flash write function by the color register 21 are all optional functions, There are combinations of when each function is operated and when it is not operated. Further, the data transfer function can be said to be an optional function when the video RAM is simply operated as a DRAM, but since it is normally operated as the video RAM, it will be described as an essential operation. However, since the data transfer bus in this embodiment can be masked or divided into a certain number, it is divided into a masked case and a non-masked case, and a divided case and a non-divided case. I will explain separately.

First, the case where all of the old mask register function, stop register function and flash write function are not operated will be described. The data transfer bus is not masked and is not divided.

In this case, since the old mask register function cannot be operated, data can be written from all the data input / output terminals WIO0-WIOi to all memory cell arrays. Further, since the stop register function cannot be operated, all the data read from each memory cell array 5 to the serial register 7 is output to the serial data input / output terminals SIO0 to SIOi. The divided data transfer buses SDTB0 to SDTBm are not divided,
Further, since it is not masked, all the data from one row of the memory cell array 5 selected by the row address decoder 9 is transferred to the serial register 7 via the divided data transfer buses SDTB0 to SDTBm.

When only the old mask register function is operated, the data input / output terminals WIO0 to WIO0 to the memory cell array 5 whose data input / output buffer 11 is not masked by the old mask register 17 are used.
Data can be written from WIOi. The other operations of the output from the serial register 7 and the data transfer are the same as those described above, and thus the description thereof will be omitted.

When only the stop register function is operated, the address terminals A0 to A stop register 2
The serial register 7 is divided in accordance with the boundary-related data fetched in 3. Therefore, the data read from the memory cell array 5 to the serial register 7 is
In response to the serial clock SC, each boundary is serially output. Other than that, the writing of data from the random access port and the data transfer from the memory cell array 5 to the serial register 7 are the same as in the case where the old mask register function is not operated, and the description thereof will be omitted.

When both the old mask register function and the stop register function are operated, data can be written into the memory cell array 5 only from the random access port not masked by the old mask register 17, and the memory cell array The data read from 5 to the serial register 7 is serially output for each boundary according to the boundary defined by the stop register 23. In this case, since the mask data stored in the old mask register 17 and the data regarding the boundary stored in the stop register 23 can be given the independent reset signals RST1 and RST2 from the reset signal generation circuit 50, respectively. Cleared independently. Therefore, for example, the stop register 2
Since only 3 can be reset, the mask data stored in the old mask register 17 can be continuously used as it is even when the * CAS before * RAS reset cycle is executed.

Next, a case where the flash write function is operated for all the rows and a case where only a part thereof is operated will be described.

When the flash write function is operated for all rows, the data input / output terminals WIO0 to WI
The data stored in the color register 21 from the Oi via the data input / output buffer 11 is simultaneously written to all the memory cells forming one row of the memory cell array selected by the row address decoder 9 via the flash write bus 20. Get caught. At this time, since it is necessary to write the data in all the one row, all the transmission gates 57 provided in the flash write bus 20 are made conductive so that all the flash write buses 20 are not masked.

When the flash write operation is performed on only a part of one row of the memory cell array 5, any flash write bus 20 is generated by the control signal generating circuit 59 according to the column mask address preloaded from the address terminals A0 to Aj. It is set whether or not to mask. That is, the flashlight bus 2 without mask
The transmission gate 57 in 0 is connected to the predetermined control signals CMF0 and * CMF0 to CMFn and * CM.
It is made conductive by applying Fn. on the other hand,
The transmission gate gate 57 in the masked flash light bus 20 is controlled by a predetermined control signal CMF.
0 and * CMF0 to CMFn and * CMFn are applied to keep them non-conductive. In this state, if all transfer gates 19 in the flash write bus 20 are made conductive by giving a predetermined control signal FW, the color register 21 is added to the memory cells in the columns where the flash write bus 20 is not masked.
Although the data stored in the memory cell is written into the memory cell of the column where the flash write bus 20 is masked,
The data stored in the color register 21 is not written, but the previously written data is maintained as it is.

According to this video RAM, since flash write can be partially performed, for example, CR
A part of the screen on T can be cleared in a short time.

Next, combinations of the case where the stop register function is operated and the case where it is not operated, the case where the data transfer bus is masked and the case where it is not masked, and the case where the data transfer bus is further divided and the case where it is not divided will be described. .

First, when the stop register function is not operated and only the data transfer bus is masked, the column mask address is first loaded into the control signal generation circuit 60 from the address terminals A0 to Aj. Next, the transfer gate 22 in the data transfer bus is made conductive at the same time by applying a predetermined control signal DT,
Then, the predetermined signals CMDT0 and * CMDT0 to CMDTn and * according to the column mask address are continuously applied.
Applying CMDTn to transmission gate 58 in the data transfer bus causes a portion of that transmission gate 58 to become conductive. Then, the data of the column whose data transfer bus is not masked is transferred from the memory cell array 5 to the serial register 7. On the other hand, since the data in the column whose data transfer bus is masked is not transferred, the serial register 7 corresponding to that column is
The previous state of the data is maintained. Therefore, the serially transferred data is serially output from the serial register 7 in a state in which the newly transferred data and the previously transferred data are mixed.

When the stop register function is not operated and only the data transfer bus is divided, the column mask address is loaded from the address terminals A0 to Aj into the control signal generating circuit 66 in advance. Then, a prescribed control signal DT0-DTm according to the column mask address is applied to transfer gate 67 in divided data transfer buses SDTB0-SDTBm to make a part of transfer gate 67 conductive. Then, in the data transfer buses SDTB0 to SDTBm which are made conductive and are not masked, the data transfer bus SDT is transferred from the memory cell array 5 to the serial register.
Data is transferred via B0 to SDTBm. on the other hand,
Masked data transfer buses SDTB0 to SDTB
In m, no data is transferred from the memory cell array 5 to the serial register 7. Therefore, the newly transferred data and the previously transferred data are serially output from the serial register 7 in a mixed state.

When the stop register function is not operated and the data transfer bus is masked and divided,
The control signal generating circuit 60 is previously supplied from the address terminals A0 to Aj.
The column mask data is loaded in each of 66 and 66. Then, the control signals according to these column mask addresses are sequentially transferred to the data transfer buses SDTB0 to SDTB0 to
By applying it to transmission gate 58 and transfer gate 67 in SDTBm, only part of data transfer buses SDTB0 to SDTBm are rendered conductive. Then, the data of the memory cell array 5 in the column which is made conductive is transferred to the serial register 7. Here, data is transferred from the memory cell array 5 to the serial register 7 only when both the transfer gate 58 and the transfer gate 67 are made conductive.

On the other hand, by operating the stop register function,
If neither the data transfer bus is masked or divided,
All the data in one row of the memory cell array 5 selected by the row address decoder 9 are simultaneously transferred to the serial register 7 via the divided data transfer buses SDTB0 to SDTBm. On the other hand, since the data related to the boundary is previously input to the stop register 23 from the address terminals A0 to Aj, the serial register 7 continuously outputs the data for each boundary. This operation is an operation that also exists in the conventional video RAM.

Further, by operating the stop register function,
When only the data transfer bus is masked, in the unmasked divided data transfer buses SDTB0 to SDTBm, data is transferred from the memory cell array 5 to the serial register 7, but the masked divided data transfer buses SDTB0 to SDTBm. In, the data is not transferred from the memory cell array 5 to the serial register 7, and the previously transferred data is maintained as it is for that portion. Then, according to the boundary-related data stored in the stop register 23, data is serially output from the serial register 7 for each boundary. Therefore, the data that is not output from the serial register 7 by the stop register function is
By masking the data transfer buses SDTB0 to SDTBm, it is possible to prevent the transfer, and it is possible to reduce the power consumption accompanying the data transfer.

Also, by operating the stop register function,
When only dividing the data transfer bus, the data of one row of the memory cell array 5 selected by the row address decoder 9 is divided into a fixed number of pieces and the serial register 7 is divided.
Transferred to. On the other hand, according to the boundary-related data stored in the stop register 23, the serial register 7 serially outputs data for each boundary. Therefore, only the data in the boundary that will be output from the serial register 7 can be transferred from the memory cell array 5.
Wasteful data that is not output from the memory cell array 5 is not transferred to the serial register 7. Therefore, similarly to the above, it is possible to reduce the power consumption associated with the data transfer.

Further, when the stop register function is operated and both the data transfer bus is masked or divided, only the divided data transfer buses SDTB0 to SDTBm which are not masked by the mask means (DTM) are used to serialize data from the memory cell array 5. The data is transferred to the register 7. On the other hand, the data transferred to the serial register 7 is serially output to the outside for each boundary according to the boundary-related data stored in the stop register 23. Therefore, similarly to the above, only the data output from the serial register 7 can be transferred from the memory cell array 5 to the serial register 7, and the power consumption accompanying the data transfer can be reduced.

Various embodiments of the semiconductor memory device represented by the video RAM according to the present invention have been described above.
The present invention is not limited to the above-mentioned embodiments, but can be implemented in other modes. For example, in the above-described embodiment, all the data transfer buses are capable of mutually transferring data between the memory cell array 5 and the serial register 7, but the data transfer from the memory cell array 5 to the serial register 7 is only in one direction. It may be possible.

Further, as for the ones for which the flash write is partially performed described in the second, third and fifth embodiments, there is no data transfer bus, serial register, etc.
It can also be applied to a simple DRAM.

Further, in the above-mentioned embodiment, it is possible to output or input data from the serial access port, but it is sufficient that at least output is possible.

In addition, the number of data transfer buses to be masked at the same time or the unit for dividing the data transfer buses is not particularly limited.
The present invention can be carried out in a mode in which various improvements, modifications, variations, etc. are added based on the knowledge of those skilled in the art, such as controlling each book.

[0153]

According to the semiconductor memory device of the first aspect of the present invention, since the old mask register means or the stop register means can be reset independently, for example, the old mask register means can be reset. Alternatively, only the stop register means can be reset.

According to the semiconductor memory device of the second aspect of the present invention, a desired memory cell array of the memory cell array can be provided.
Since the same data can be simultaneously written to some of the memory cells forming the row, only some of the data stored in the memory cells can be rewritten in a short time.

According to the semiconductor memory device of the fifth aspect of the present invention, only the data stored in a part of the memory cells forming one desired row of the memory cell array is stored in the serial register means. Since it can be transferred to the register element configuring the above, it is possible to transfer only necessary data and not transfer unnecessary data.

According to the semiconductor memory device of the sixth aspect of the present invention, the data stored in the memory cells forming a desired one row of the memory cell array is divided into a predetermined number and serial register means is provided. Since the data can be transferred to the constituent register elements, the data that will not be finally output to the outside by the serial register means can be transferred as little as possible.

Further, according to the semiconductor memory device of the seventh aspect of the present invention, a desired memory cell array of a desired memory cell array can be provided.
Since the data stored in the memory cells forming a row can be divided into a certain number of pieces to be transferred to the register elements forming the serial register means so as to correspond to the boundary, the serial register means finally externally Data that is never output to can be prevented from being transferred as much as possible.

Further, according to the semiconductor memory device of the eighth aspect of the present invention, a fixed number of data in the same column among the data stored in the memory cells forming one desired row of the memory cell array. It is possible to repeatedly transfer only the data and to repeatedly output the data in the same boundary by the serial register means. Therefore, one boundary and a portion of the memory cell array corresponding to this boundary are one video RAM. Can be treated like.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a video RAM which is a first embodiment of the present invention.

FIG. 2 is a block diagram showing in more detail a main part of the video RAM shown in FIG.

FIG. 3 is a circuit diagram more specifically showing the CBR reset signal generating circuit shown in FIG.

4 is a time chart showing a load old mask register cycle for loading mask data into the old mask register of the video RAM shown in FIG. 1. FIG.

5 is a time chart showing a write per bit cycle in an old mask mode in the video RAM shown in FIG.

6 is a time chart showing a load / stop register cycle for loading data regarding a boundary into a stop register of the video RAM shown in FIG. 1. FIG.

FIG. 7 is a time chart showing a * CAS before * RAS old mask register No-Reset cycle in which only the old mask registers shown in FIGS. 1 and 2 are not reset.

FIG. 8 is a time chart showing a * CAS before * RAS stop register No-Reset cycle in which only the stop register shown in FIGS. 1 and 2 is not reset.

FIG. 9 is a table showing a summary of operations of the CBR reset signal generation circuit shown in FIGS. 1 and 2.

FIG. 10 is a block diagram showing an overall configuration of a video RAM which is a second embodiment of the present invention.

11 is a circuit diagram showing in more detail a main part of the video RAM shown in FIG.

12 is a time chart showing an example of a load column mask address cycle for loading mask data of the flash write bus or the data transfer bus shown in FIGS. 10 and 11. FIG.

13 is a time chart showing another example of the load column mask address cycle for loading the mask data of the flash write bus or the data transfer bus shown in FIGS. 10 and 11. FIG.

14 is a time chart showing still another example of the load column mask address cycle for loading the mask data of the flash write bus or the data transfer bus shown in FIGS. 10 and 11. FIG.

FIG. 15 is a time chart showing a data transfer cycle for data transfer in the data transfer bus shown in FIGS. 10 and 11.

FIG. 16 is a block diagram showing an overall configuration of a video RAM which is a third embodiment of the present invention.

17 is a circuit diagram showing in more detail a main part of the video RAM shown in FIG.

FIG. 18 is a block diagram showing the overall structure of a video RAM according to a fourth embodiment of the present invention.

19 is a circuit diagram showing in more detail a main part of the video RAM shown in FIG.

20 is a schematic diagram for explaining the operation of the video RAM shown in FIG.

21 is a time chart showing a load / transfer boundary cycle for loading a transfer boundary which is a unit for dividing the data transfer bus in the video RAM shown in FIG.

22 is a schematic diagram for explaining the operation of the video RAM shown in FIG.

23 is a circuit diagram more specifically showing a stop register of the video RAM shown in FIG.

FIG. 24 is a block diagram showing an overall configuration of a video RAM which is a fifth embodiment of the present invention.

FIG. 25 is a block diagram schematically showing a configuration of an image processing system using a conventional video RAM.

FIG. 26 is a block diagram showing an overall configuration of an example of a conventional video RAM.

27 is a circuit diagram showing in more detail a main part of the conventional video RAM shown in FIG.

FIG. 28 is a block diagram showing an overall configuration of a portion shown in FIG. 27.

FIG. 29 is a time chart showing a data transfer cycle for performing data transfer in the conventional video RAM shown in FIG. 26.

30 is a diagram for explaining a stop register operation by the conventional video RAM shown in FIG.

31 is a time chart showing a load / stop register cycle for loading data regarding a boundary into a stop register of the video RAM shown in FIG. 26. FIG.

32 is a schematic diagram for explaining a stop register operation by the conventional video RAM shown in FIG.

33 is a block diagram showing a part of the conventional video RAM shown in FIG. 26. FIG.

FIG. 34 is a circuit diagram more specifically showing a CBR reset signal generation circuit in the conventional video RAM shown in FIG. 33.

FIG. 35 is a * CAS before * RA for explaining the operation of the conventional CBR reset signal generation circuit shown in FIG.
It is a time chart which shows a S Reset cycle.

36 is a * CAS before * RA for explaining the operation of the conventional CBR reset signal generating circuit shown in FIG.
It is a time chart which shows an S No-Reset cycle.

[Explanation of symbols]

5 memory cell array 6, 6a, 6b data transfer bus 7, 7a, 7b serial register 17 old mask register 20 flash write bus 21 color register 23 stop register 25 address pointer 50 CBR reset signal generation circuit 57 transmission gate (flash write bus mask means ) 58 transmission gate (data transfer bus mask means) 59, 60, 61, 62, 66 control signal generation circuit 68, 69, 70, 71, 72, 73, 74, 75, 7
6,77,78,79 boundary PDTB0 to PDTBm partial data transfer bus SDTB0 to SDTBm divided data transfer bus

Claims (8)

[Claims] 1. A plurality of memory cell arrays each including a plurality of memory cells arranged in a matrix of rows and columns, further comprising the same number of register elements as the memory cells forming one row of the memory cell array, Serial register means for serially outputting the data stored in these register elements to the outside, and data stored in the memory cells forming one desired row of the memory cell array to the register elements forming the serial register means. Transfer means for transferring, input means for simultaneously inputting data from the outside to the plurality of memory cell arrays, and setting to which memory cell array of the plurality of memory cell arrays the data is input by the input means The old mask register means and the serial register means are connected. To include a stop register means for setting a boundary which is a unit of data to be output, and reset means for resetting the old mask register means and said stop register means each independently semiconductor memory device. 2. A memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns, and data is stored in a part of the memory cells forming one desired row of the memory cell array. A semiconductor memory device comprising: partial flash write means for writing simultaneously; and data holding means for holding data to be written in a memory cell by the partial flash write means. 3. The partial flash write means, a flash write bus electrically connecting the data holding means and each memory cell forming one row of the memory cell array, and intervening in each of the flash write buses. 3. The switching device according to claim 2, further comprising: a switching element that opens and closes the flash light buses at the same time; and a masking unit that is connected in series with the switching element and that masks a part of the flash light buses. Semiconductor memory device. 4. The partial flash write means includes a flash write bus for electrically connecting the data holding means and each memory cell forming one row of the memory cell array, and the partial flash write means is provided in each of the flash write buses. 3. The semiconductor memory device according to claim 2, further comprising a switching element capable of opening and closing the flash light bus arbitrarily. 5. A memory cell array having a plurality of memory cells arranged in a matrix of rows and columns, and the same number of register elements as the memory cells forming one row of the memory cell array. The serial register means for serially outputting the stored data to the outside, and the data stored in a part of the memory cells forming one desired row of the memory cell array constitute the serial register means. A semiconductor memory device including a partial transfer means for transferring to a register element. 6. A memory cell array having a plurality of memory cells arranged in a matrix of rows and columns, and the same number of register elements as the memory cells forming one row of the memory cell array. Serial register means for serially outputting the stored data to the outside, stop register means for setting a boundary which is a unit of data continuously output by the serial register means, and a desired one row of the memory cell array And a division transfer unit for dividing and transferring the data stored in the memory cell forming the above to the register elements forming the serial register unit by a predetermined number. 7. A fixed number, which is a unit of data transferred by the division transfer unit, and a boundary, which is a unit of data continuously output by the serial register unit, are matched. 7. The semiconductor memory device according to item 6. 8. The division transfer means is configured to repeatedly transfer a fixed number of data in the same column of the memory cell array, and the serial register means is configured to repeatedly output data in the same boundary. The semiconductor memory device according to claim 7, wherein the semiconductor memory device is a memory device.