JPS6054076A - Picture enlarging and reducing circuit - Google Patents

Abstract

PURPOSE:To enable simple enlarging, reducing and rotation of a picture by controlling transfer of picture information by registers based on the command of enlarging and reducing obtained by repeated addition of the ratio of enlarging and reducing in horizontal and vertical directions set arbitrarily. CONSTITUTION:A picture enlarging and reducing circuit 1 consists of a system controlling circuit 10 that makes control of the whole and access control to a picture memory 2 and a constant setting section 20 that stores address information of the picture memory 2 and ratio of enlarging and reducing and can be changed the content of setting by a host processor 3. The circuit 1 is provided with a timing generating circuit 30 that generates timing signals of enlarging and reducing by repeated addition of ratio of enlarging and reducing. Further, the circuit 1 consists of a horizontal direction enlarging and reducing circuit 40 made up of plural shift registers that make shift output according to timing signals from the timing generating circuit 30 and a buffer memory 50 that temporarily stores picture data after enlarging and reducing of the output.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an image enlarging/reducing circuit which has a simple configuration, can obtain predetermined enlargement and reduction ratios, and facilitates image rotation.

[Prior art]

As a conventional image enlargement/reduction circuit, there is one shown in FIG. 1, for example. This image enlargement/reduction circuit includes a 32-bit shift register 101 in which the enlargement rate and reduction rate are initially set by the system control unit, and an image storage device R200.
A 32-bit shift register 102 in which data in the row direction (or column direction) of the original image data is set; A shift register 103, 32-decimal counters 104 and 105 that count the effective length of image data in the shift registers 102 and 103, an inverter 106 that inverts and outputs enlargement/reduction commands, and output signals of the shift register 101 and the inverter 106. an AND gate 107 that generates an output signal by performing a logical product with an output signal; an AND gate 108 that generates an output signal by performing a logical product of the shift register 101 and an enlargement/reduction command; an OR gate 109 which takes the logical sum of the output signals of the inverter 107 and generates an output signal; It is composed of an AND gate 112 that takes the logical product of the output signal of the OR gate 109, and an AND gate 112 that takes the AND of the output signal of the OR gate 101.

FIG. 2 shows an example of an image processing apparatus in which the next image enlargement/reduction circuit shown in FIG. 1 is used as each of the horizontal and vertical enlargement/reduction circuits.

It is constructed using a 32-bit word image storage device 200 for storing the original image data and the shift register 103, expansion or reduction/J% new image data, and a microprocessor to control the entire system. a system control unit 300 that performs image processing, and a row-direction scaling circuit 400 configured as shown in FIG.
A column direction scaling circuit 5 that enlarges or reduces the column direction data of the original image data to create new column direction image data.
00, a host CPU 600 that transfers image data input from various terminal devices to the image storage device 200 or transfers enlarged/reduced data to an output device, and the host CPU 600 and the image processing device are electrically coupled. The configuration includes a channel coupling circuit 700 that controls access to the image storage device 200 from each circuit, and an access control circuit 800 that controls access to the image storage device 200 from each circuit.

In the above configuration, image information such as document information is stored in the image storage device 200 from the host CPU 600 via the channel coupling circuit 700, and is stored in the system control unit 3.
00KJ is the magnification rate or #: 1 decimal magnification circuit 4
00 and 500, and control the data transfer rtb of the original image data according to this reduction ratio to create new image data and transfer it to the image storage device R200. The new image data after enlargement or reduction stored in the image storage device 200 is outputted to an external device or a transmission line via the host cPU 600.

Image enlargement/reduction operation at this time: Forward direction enlargement/reduction circuit・■
A case in which 00 is enlarged twice will be described below in detail.

The enlargement/reduction command is given to the system control unit 300↓, l is given for enlargement, and O is given for reduction, and a 32-bit binary number corresponding to the enlargement rate or reduction rate is set in the shift register 101. Ru. For example, 010101 to enlarge by 2 times, 011 to enlarge by 4 times.
101110111...: A total of 32 arrays
The bit configuration is set in the shift register 101.

In the case of expansion by 2 times, the expansion/reduction jii command is 1, the shift register 101 is 010101...O20m, and in the initial state, 1 means that there is no clock signal source,
Counters +04 and 105 are set to 0. In this state, the original 32 bits of the row direction data of the image data are transferred to the C shift register 102 from the image storage device 200.1.

The clock signal is input after the transfer, but it's not a good idea.)10
Since the level of 10 of 9 is 1 and the output level of the OR gate 11O is O, even if an output signal is generated at the ant game 1.ill, no output signal is generated at the ant game 112.

The p counter 105 is incremented by the output signal of the AND gate iii, and the leftmost 1-bit data of the shift register +02 is transmitted to the shift register 103. , then a clock signal is output, and the shift register 101el
Bit left shift weight is AND gate 107 and 10
8 can be output. This^me or gate 109 and 110
A Lebel output signal is generated on both sides of the
1 and 112 - output signals are also generated, and the counters 104 . Both shift register i
02. Both u03 are shifted to the left by 1 bit. At this time, the data transferred to the shift register 103 is the same as the data when the previous clock was generated (no output signal was generated from the AND gate 112 last time, so there was no shift); It is 2!i- because 1 bit of image data is transferred by L2 bits.

When 32 clocks are output, the counter 105 outputs Nutuawata, 1st memory i'%, 200
The data in the shift register 1133 is stored in the stored image data. Further, when the count l (+4) counts to 32, a fetch command is issued, and the next original image data is set in the /ft register 102.

In this way, by outputting the generation ratio of the output signals of the AND gates 111 and 112 applied to the shift registers 102 and 103 according to the magnification ratio, and moving the data within the two registers according to the magnification ratio, the expansion is possible. can be done. Reduction is data movement fr1 of shift register i03
This can be done by thinning out 02, and the expansion and contraction in the IC1 column direction can be processed using the same procedure as in the row direction, so the explanation will be omitted.

With the above configuration, image data can be enlarged or reduced without performing multiplication processing or the like.

However, in the conventional image enlargement/reduction circuit, it is necessary to set the enlargement or reduction instruction in the shift register 10IK, so it is necessary to create the data pattern in advance, and the number of bits of the prepared data pattern is The sheath quality was relatively poor.

[Object and structure of the invention]

The present invention has been made in view of the above, and has a simple configuration to quickly obtain images with arbitrary enlargement and reduction ratios, and to enable rotation of the image. Repeat the arbitrary setting formula ft, enlargement and reduction ratio,
The present invention provides an entire image enlarging/reducing circuit which controls the transfer of image information through a plurality of registers based on commands for enlarging and reducing f'L and fc obtained by addition.

The image enlargement/reduction circuit according to the present invention will be explained in detail below.

〔Example〕

FIG. 3 shows an embodiment of the present invention, in which the image information to be enlarged or reduced is stored and connected to each of the image memory 2 and the host processor 3 for controlling the system. This is an image enlargement/reduction circuit l. The image scaling circuit 1 includes a system control circuit io that uses a microprocessor to perform overall control and access control to the image memory 2, and the image memory 2.
The address information, enlargement ratio, and reduction ratio are stored, and the setting contents are stored in the constant setting section 20, which can be changed arbitrarily by the host processor '9-3. a horizontal enlargement stripe subcircuit 40 consisting of a timing generation circuit 30 that generates timing signals for enlargement and reduction, and a plurality of shift registers that hold image information and perform shift output according to timing signals from the quimink generation circuit 30; The enlarged image data outputted from the horizontal enlargement/reduction circuit 40 is composed of a rougher memory 50 that temporarily stores the image data after reduction.

FIG. 4 is a diagram showing detailed configurations of the timing generation circuit 30 and the horizontal enlargement/reduction circuit 40 shown in FIG. 3.

The timing generation circuit 30 repeatedly adds the values of the horizontal expansion rate and reduction rate stored in the register 21.
A temporary register 31 used for C, an adder 32 that generates a carry signal by addition operation via the temporary register 3tt, and a carry and reduction command (J'' level and enlargement command (reduction command) inversion) signal)
A logic AND circuit 33 that takes the logic of the clock pulse and an expansion/species 1 small command, and an AND circuit 34 that takes the logic of the clock pulse and the expansion/species 1 small command.
An OR circuit 35 outputs the logic tree 1 of the output signals of AND circuits 33 and 34 as a shift clock; An AND circuit 37 which takes a logic private sum, an OR circuit 38 which outputs the logical sum of the outputs of the AND circuits 36 and 37 (the logical sum of the Q numbers) and a shippuffer memory store timing signal form a configuration formula i1.

The horizontal enlargement/reduction circuit 4o includes a plurality of shift registers (for example, formation of a 16×16 bit matrix) which inputs image information in parallel and outputs it serially.
a shift register group 41 comprising six registers);
OR circuit 35 outputs iL shift clock, RcI! l
and a shift counter 4z which counts the number of bits and sends an overflow signal to the system control circuit 1o when the counted value reaches the number of bits of the shift register.

Further, the timing generation circuit that generates the vertical enlargement/reduction timing signal is configured to determine the vertical enlargement ratio and t111.
A carry signal is generated by a register 22 whose fractional ratio is n for storage, a temporary register 39 whose n is used to repeatedly add the value of the vertical expansion/reduction ratio, and an assisting operation via the temporary register 39. Adder 45
It is made up of a lot more.

In the above configuration, the image information is stored in the image memory 2 under the control of the host processor 3, with the white and black parts of the information corresponding to the hit values of 0 and 5. Address information of the 19 image memory 2, enlargement rate, reduction rate, etc. are arbitrarily set. FIG. 5 shows the relation between the image in the image memory 2 and the memory address. The image memory 2 has an image memory pitch of n from θ to address (n-+), and ) digits. The image memory address register of the system control 1 circuit 10 has address (n11).

Each time the adder 45 repeatedly adds, the image memory pitch n is added to the image memory address register.

When C3 occurs, data is read from the image memory 2 and sequentially set in the shift registers 16 (+61) of the shift register group 41. When the adder 32 and the shift register are output formula n and a reduction command is issued, the AND circuit is When the AND condition of 36 is satisfied, the OR circuit 38 outputs the output timing signal, and each time this signal is output, the system control circuit 10 transfers the image information to be serially outputted from the shift register group 41 to the buffer memory. On the other hand, when the shift clock Cs output from the OR circuit 35 reaches the maximum number of bits of the shift register,
Shift counter 42 overflows and sends an overflow signal to system control circuit IO. Upon receiving the overflow signal, the system control circuit IO sets the read information from the image memory 2 in the shift register group 41 again, and transfers the image information of the next row shown in FIG. 5 to each shift register. From then on, every time the (-flow signal is sent out, reading from the image memory 2 is performed. (M+1)
The expression is executed repeatedly until the digits are completed. Reading is performed sequentially in the address order of blocks 1 (Bl), B2, . . . Bn, and the reduced image information of each block is stored in the buffer memory 50. For example, in B1 (nt
), B2 can read from address (n-2).

FIG. 6 shows an example of reduction at a reduction rate of 50%.

The register 21 is set to 0.5, and as shown in the table below, when the trap adder 32 adds 10 times, 5 carries are output, during which time 10 clock pulses are output, and a whisper is output. 〃The shift clock C3 for which the level reduction command is output is outputted from the OR circuit 35 ↓ 10 times, and the OR circuit 38 outputs 5 buffer memory store timing signals. Therefore, l/2 of the number of bits read from the image memory 2 to the register group 41 is transferred from the register group 41 to the Shibarahua memory 50, and image information reduced by 50% is output to the buffer memory 50. You will be robbed.

When enlarging an image, set the reciprocal of the reduction ratio for the horizontal direction, and set the enlargement ratio -1 for the vertical direction.
At the same time, on the horizontal side, the addition clock and carry are reversed to generate the shift clock Cs and the buffer memory store timing signal, and the horizontal side is enlarged, and on the vertical side, every time a carry occurs, K +i The same information read by the image memory 2 is written into shift registers i and (i+1) so that every two lines have the same content.

Furthermore, when rotating an image, the address allocation of the image memory 2 is made different before and after the rotation, and the order in which the buffer memory 50 transfers information to the image memory 2 is changed accordingly. For example, an image rotated by 90 degrees as shown in FIG. 7 is obtained (in FIG. 7, the image is also reduced by 50 inches).

Note that the timing generation for expansion and contraction can be replaced with registers, ALU, etc. in the microcomputer.
p) Also, by providing a plurality of shift registers and buffer memories, information with gradation can be handled.

〔Effect of the invention〕

As explained above, according to the image enlargement/reduction circuit of the present invention, a plurality of Since the transfer of image information is controlled by the register, images with arbitrary enlargement and reduction ratios can be obtained with a simple configuration, and even rotated images can be obtained.

[Brief explanation of drawings]

Figure 1 is a diagram of the conventional image enlargement process for one small circuit.
FIG. 2 is a block diagram showing an example of an image processing device 1k4l constructed using the image enlargement/reduction circuit shown in FIG. The figure shows a detailed diagram of the timing generation circuit 30 and the horizontal enlargement/reduction circuit 40 in FIG. 3, FIG. 5 shows the address layout 171° of the image memory 2, and FIG. FIG. 7 is an explanatory diagram showing an example of a rotated image by the misfire J. Explanation of symbols 1: Image enlargement/reduction circuit, 2: Image memory, 3
...Host Brosse, The, 10...System control unit,
20...Constant setting section, 21.22...Register, 3
0...Timing generation circuit, 31.39...Denvolary register, 32.45...Adder, 33, 34
, 36.37...AND circuit, 35.38...OR circuit, 40...horizontal enlargement/reduction circuit, 4l...shift register section, 42...shift count, 50...
・Buffer memory.

Claims (1)

[Claims] An image processing device that converts each pixel of an image into a digital signal and stores it in an image memory, and processes the stored image information to enlarge or reduce the image, which can be used at any horizontal or vertical enlargement rate. and a constant setting part in which the reduction rate is set by the setting part, and the enlargement or reduction ratio set by the constant setting part are repeatedly added to generate an enlargement or reduction timing signal. a timing signal generating section that generates a shift clock and a buffer memory store timing signal according to mutual logical conditions of the timing signal, the clock pulse, and the enlargement/reduction command; A shift register group including a plurality of shift registers for shifting horizontal direction information of yυ, and a buffer memory for temporarily storing enlarged or reduced image data of the shift register group ↓ are provided. An image scaling circuit featuring: