JPS5537672A - Conversion system of dot pattern - Google Patents

Conversion system of dot pattern

Info

Publication number
JPS5537672A
JPS5537672A JP11092378A JP11092378A JPS5537672A JP S5537672 A JPS5537672 A JP S5537672A JP 11092378 A JP11092378 A JP 11092378A JP 11092378 A JP11092378 A JP 11092378A JP S5537672 A JPS5537672 A JP S5537672A
Authority
JP
Japan
Prior art keywords
row
column
address
input
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11092378A
Other languages
Japanese (ja)
Inventor
Haruka Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP11092378A priority Critical patent/JPS5537672A/en
Publication of JPS5537672A publication Critical patent/JPS5537672A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To convert an input dot pattern, row by row or column by column, by converting a row-unit input of dot patterns of characters into a column-unit output or reversely by information of a switching display line.
CONSTITUTION: Row-address decoder 2 attains access to memory 8 and row data input-output buffer 5 writing or reading data in or from row address 2 or are provided and further column-address decoder 3 and column data input-output buffer 4 writing or reading data in or from column address are provided and address input line ADDR signal transmitted to row or column decoder 2 and 3 is switched by multiplexer 1 and a data line IND signal transmitted to row or column buffers 4 and 5 is by myltiplexer 6. Then data read to row or column buffers 5 or 4 is switched by multiplexer 7, thereby converting dot patterns, row by row or column by column.
COPYRIGHT: (C)1980,JPO&Japio
JP11092378A 1978-09-09 1978-09-09 Conversion system of dot pattern Pending JPS5537672A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11092378A JPS5537672A (en) 1978-09-09 1978-09-09 Conversion system of dot pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11092378A JPS5537672A (en) 1978-09-09 1978-09-09 Conversion system of dot pattern

Publications (1)

Publication Number Publication Date
JPS5537672A true JPS5537672A (en) 1980-03-15

Family

ID=14548042

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11092378A Pending JPS5537672A (en) 1978-09-09 1978-09-09 Conversion system of dot pattern

Country Status (1)

Country Link
JP (1) JPS5537672A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57129764U (en) * 1981-02-06 1982-08-12
JPS5965371A (en) * 1982-10-06 1984-04-13 Canon Inc Central processor
JPS6054076A (en) * 1983-09-02 1985-03-28 Fuji Xerox Co Ltd Picture enlarging and reducing circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57129764U (en) * 1981-02-06 1982-08-12
JPS6111218Y2 (en) * 1981-02-06 1986-04-09
JPS5965371A (en) * 1982-10-06 1984-04-13 Canon Inc Central processor
JPS6054076A (en) * 1983-09-02 1985-03-28 Fuji Xerox Co Ltd Picture enlarging and reducing circuit

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