JPS54114114A - Still picture receiving device - Google Patents

Still picture receiving device

Info

Publication number
JPS54114114A
JPS54114114A JP2178078A JP2178078A JPS54114114A JP S54114114 A JPS54114114 A JP S54114114A JP 2178078 A JP2178078 A JP 2178078A JP 2178078 A JP2178078 A JP 2178078A JP S54114114 A JPS54114114 A JP S54114114A
Authority
JP
Japan
Prior art keywords
frame
memory
switch
data
reading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2178078A
Other languages
Japanese (ja)
Inventor
Kunio Wakamatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP2178078A priority Critical patent/JPS54114114A/en
Publication of JPS54114114A publication Critical patent/JPS54114114A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To increase the application range and thus to enhance the using efficiency for the still picture receiving device featuring the frame capacity by securing easy switching between the frame display and the field display.
CONSTITUTION: The following component units are provided: writing data switch 17 which delivers the data transmitted via the transmission line to two field memories 16a and 16b which form the picture memory of 1-frame capacity after switching selectively; reading data switch 21 which performs reading after switching selectively the data written into memory 16a and 16b; address designation register 18 and 19 which designate the address when the data writing and reading is carried out for memory 16a and 16b; frame/field display change-over switch SW1 which designates the frame display or the field display; write/read field selector switch SW2 which designates memory 16a and 16b at the writing and reading time; and switch signal generator 24 connected to SW3 respectively.
COPYRIGHT: (C)1979,JPO&Japio
JP2178078A 1978-02-27 1978-02-27 Still picture receiving device Pending JPS54114114A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2178078A JPS54114114A (en) 1978-02-27 1978-02-27 Still picture receiving device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2178078A JPS54114114A (en) 1978-02-27 1978-02-27 Still picture receiving device

Publications (1)

Publication Number Publication Date
JPS54114114A true JPS54114114A (en) 1979-09-06

Family

ID=12064567

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2178078A Pending JPS54114114A (en) 1978-02-27 1978-02-27 Still picture receiving device

Country Status (1)

Country Link
JP (1) JPS54114114A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5992687A (en) * 1982-11-19 1984-05-28 Nec Corp Still picture transmitter
JPS6280481U (en) * 1985-11-06 1987-05-22

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5992687A (en) * 1982-11-19 1984-05-28 Nec Corp Still picture transmitter
JPH0212433B2 (en) * 1982-11-19 1990-03-20 Nippon Electric Co
JPS6280481U (en) * 1985-11-06 1987-05-22
JPH051185Y2 (en) * 1985-11-06 1993-01-13

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