JPS58169665A - Vertical-horizontal converting circuit of image array for image memory system - Google Patents

Abstract

PURPOSE:To ensure a vertical-horizontal conversion of an image array with a simple constitution, by providing a means to perform an exchange between the row and column addresses. CONSTITUTION:A memory mode signal MM has a value ''1'' that shows an image buffer processing action, and a rotary mode signal RM has a value ''1'' that indicates that the rotary storage is needed for the format. In such a case, the output of an AND gate 9 is set at ''0'', and a data selector 8 delivers A' and t'. The signal A' gives an indication to data selectors 5 and 6 an exchange between the row and column addresses for a vertical-horizontal conversion. As a result, an image which underwent a vertical-horizontal conversion is stored in an image memory 1.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to image processing equipment such as printers and facsimile machines. An image memory system for the storage of image information, and in particular an image array that allows image information in portrait and landscape formats to be arbitrarily exchanged and stored from one format to another. Related to vertical/horizontal conversion circuits.

(2) Technical background Recent printers are A4. There are many systems that allow printing in any format, such as 9 characters vertically or horizontally, on paper of a specified size such as BS. In printers of this type, there are cases where it is desired to output an image in a portrait format onto a landscape paper, or vice versa. For this purpose, the image buffer in the printer is usually the image buffer shown in Figure 1(a).
(b) As shown in K, format B4, which has the maximum size both vertically and horizontally, can be accepted to meet output requests in any format. For example 4095 x 4095
A rectangular address space of memory is provided.

However, as shown by the shaded area in Figure 1, such a memory between rectangular address walls has a lot of wasted area, and the utilization efficiency of the memory elements suffers. to the bones.

The image buffer is usually 2K to speed up processing.
This is even more so since there are multiple units provided and these are used by switching over alternately.

Therefore, as an improvement measure, as shown in Figure 2.

The image storage area t in the image memory is fixed at the image array position of the maximum vertical size on the left side.

The remaining right side area is used as a character block (C, G), an area to store control instructions, a work area, etc.

A method has been proposed in which the lower part is left unused and no memory element is mounted thereon.

In this case, depending on the format e size.

It becomes necessary to convert a horizontally long or vertically long 7 format into a vertically long or horizontally long format, respectively. This conversion is a 90 degree rotation conversion on the coordinate axes, and simply exchanging the row address and column address will cause the image to be inverted and rotation cannot be achieved by 90 degrees. It would be good if there was an address calculation system and an access system that rotated the coordinate axis Y of the entire memory by 90 degrees.

For this purpose, it is necessary to prepare two sets including an address calculation system and an access system for normal access processing, which increases the burden on the hardware.

On the other hand, Japanese Patent Publication No. 54-39098 (Memory System for Image Processing: IBM)
In the image memory system of the type disclosed in Japanese Patent No. 56-101498, in order to speed up storage processing, a plurality of image points called an image array are divided into the same number of storage modules. Distributed and simultaneous read/write processing is performed. Third
The figure shows an example of such an image subarray. With image point 1 (i@j)t-base point at the top position, either P-bit image sub-array of PXI or IXP is selected. In this case, it is necessary to switch the designation t of the image sub-array at the same time as the image array is rotated.

(3) Object of the Invention The object of the present invention is to provide an image memory system of the above-described image distribution U processing format without changing the conventional address calculation system and access system.
To provide an image array vertical/horizontal conversion circuit with a simple configuration, which can simultaneously set a character generator area and a work area.

Another object of the present invention is to provide another modification of the invention disclosed in Japanese Patent Application No. 1983-213492 previously filed by the same applicant.

(4) Structure of the invention The principle of the invention will be explained with reference to FIG. The figure @ is on the original image memory of 9. When writing this.

By exchanging row address i and column address j with t,
As shown in Figure 5, only an image inverted by 1 is stored in the image memory. Therefore, the present invention performs access in reverse order from the end of the row address on the image memory as shown in 5 as shown in @, and as a result, as shown in 5 in @, when loading in ■, Address conversion processing is performed so that the normal image 9 of @ is output as if it had been stored.

To achieve this, the present invention has a configuration in which the row address i) for selecting an image point in the image array, the column address j, and the two image points glXP are specified in any subarray of PXI. In an image memory system having an image memory whose access is controlled by a signal means t,

1) Specifying signal means R, M, signal @A instructing mutual conversion between 1 row address i and column address j, and the above signal When the means RM changes the format specification,
The signal means t is inverted to indicate completion, and the signal means A
V invert and 9th line address ik! lr column address j′
As for the 1st column address j, when writing, the new row address 11 is used as it is, but when reading, the address exchange means sets the value obtained by subtracting the column address value from the shrimp column address value jmax of the image array as the new row address 11. It is considered as a V% characteristic to have the following characteristics.

(5) Examples of the invention Below, nine embodiments of the present invention will be explained.

FIG. 5 is an explanatory diagram of the configuration of an image memory used in this embodiment, and FIG. 6 is an explanatory diagram of signals of an external register that controls the vertical/horizontal conversion circuit of this embodiment.

In FIG. 5, (a) shows the image array before vertical/horizontal conversion, and FIG. 5(b) shows the image array after conversion. It has 4095 allele positions in each row and 9 columns.

Each 12-bit row address i, 1. and 1), select the image point I (i, j )Y by Iat, hejl, . The image sub-array has a 16-bit configuration, and using the sub-array type designation signal t, the Pxl type shown in FIG. 3 is expressed as r=1.1xP type vt=o.

In Fig. 6, (a) indicates each format) 84/
A4. For B5/A5, 9-rotation mode signal R that instructs whether to use portrait or landscape image arrangement.
Mt-indicated. For example, as shown in FIG. 5(a), A
If it is desired to use the 4/B4 format in landscape orientation, the image must be rotated and stored in portrait orientation in the image memory, as shown in FIG. 4(b). RM this
=@l" for shallow water. Also, when using A4/B4 in portrait orientation, there is no need for rotation conversion, so RM="O". In the case of A5/B57 ohmakt, it is the opposite of A4/B4. The following relationship holds true: In this way, in the case of RM-“l”, the vertical/horizontal conversion process must be activated.

In FIG. 186(b), the memory mode signal MM is.

t-Indicates whether the image memory access request is for a single character generator or work area (=@0") or for an image buffer area (="1").

The access mode signal t is the access type of the image subarray IXPt-horizontal mode (=@O''),
PXl is designated as vertical mode (="1"), and address inversion mode signal A is.

Row address 118 for image array rotation transformation. and column address j1□.

In FIG. 6 <C>, the bladder release signal R and the write signal W are used for accessing 9 rows in the address inversion mode.

Used to indicate forward or reverse access. Signal B and signal W are complementary values, one is ``
When I', the other shows "01t".

When A='1' and R='l', -j, that is, when there is a continuation, the subtraction circuit for generating row addresses in the reverse order is made functional.

Next, the embodiment circuit Y in FIG. 7 will be explained.

In the figure, 1 is an image memory, 2 is a real memory configured as a module, and 3 is a memory module number M based on a row address i and a column address j in the image memory space.
This is an address calculation circuit that calculates (蓼, j) and its storage location A<i, i>.

4 is a vertical/horizontal conversion circuit; 5 and 6 are data selectors that exchange addresses in the row and 1 column; 7 is a subtraction circuit that subtracts j1□-8 from the maximum column address value j max; and 8 is a data selector. , 9 is a NAND gate, 10 to 12 are inverters for generating an inverted signal t, and 13 and 14 are ANL) gates.

In operation, the memory mode signal MM
Takes a value t of 1” indicating buffer processing operation.

When the rotation mode signal kLM takes a value of "1" indicating that format rotation storage is necessary, the output of the NAND gate 9 becomes "0".

The data selector 8 selects A and rY from among the manual inputs A, A, t, and T and outputs the selected data.

The signal λ instructs the data selectors 5 and 6 to transpose row and column addresses for vertical/horizontal conversion.

Here, when the write signal W takes a value of "1" indicating a write operation, the data selector 6.

The data selector 5 outputs the row address j 11-01 to the column address J'n■, and the data selector 5 outputs jll, 't', and row address "11-0" input through the AND gate 14.
I will appear on.

On the other hand, the write signal W is "0", so the bladder is out 11!
When the I No. R is 1", the subtraction circuit 7 and the A
ND game) 13, reverse address (j max −
'1l-tl) is sent from data selector 5 to '1l-L
output to l.

On the other hand, it may be image buffer processing (MM=″0
”), or when image buffer processing does not require vertical/horizontal conversion processing (RM="0").

The output of the NAND gate 9 becomes "1", and the data selector 8 selects and outputs the input A, 71. In this case, t '11-0 in data selectors 5 and 6
becomes “11-0, and t jll-0 becomes jl□1.
will be released as is. These signals are respectively supplied to the address calculation circuit 3. In this case, R,W
Regardless of the value of , the function of generating a reverse address by the subtraction circuit 7 is not activated. (6) Effects of the invention As described above, the image memory 1 retains the conventional configuration and receives the input signal t/7''11-11 in the same form as the conventional one.
'j'1□, processing is easy, and memory can be used efficiently with a simple circuit.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the conventional image memory usage state, FIG. 2 is an explanatory diagram of the improved image memory usage state,
#! Figure 3 is an explanatory diagram of the image subarray. FIG. 4 is an explanatory diagram of the vertical/horizontal conversion escape in the present invention. FIG. 5 is an image memory configuration diagram of the embodiment, FIG. 6 is an explanatory diagram of signals controlling the vertical/horizontal conversion operation of the embodiment, and section 7 is a configuration diagram of the embodiment. In the figure, l is an image memory, 4 is an aspect conversion circuit, 5, 6.8 is a data selector, 7 is a subtraction circuit, 9 is a NAND gate, 10 to 12 inverters, 13.14
indicates an AND gate. , % Applicant Fujitsu Ltd. Representative Patent Attorney Fumihiro Hase (1 other person) (S(b) (C) ↑Ghi

Claims (1)

[Claims] A row address i and a column address j for selecting an image point in an image array, and P image points 1xxP.
or signal means t specified in any subarray of PXI
In an image memory system having an image memory whose access is controlled by When the signalman 1jA instructing the format and the signal means RM change the format designation. The above signal means ty is inverted to T, and the signalman &
AV is inverted and the 1st row address iv becomes a new column address j1. For the 9th column address j, when writing, it is used as the new row address il, but when reading, it is the value obtained by subtracting the column address value from the maximum column address value jmax of the image array. 1. An image array vertical/horizontal conversion circuit comprising address conversion means for converting vfIfr to a row address i1.