JPS58166581A - Addressing system of memory - Google Patents

Abstract

PURPOSE:To reduce hardware, by using the value of a memory address register as an upper address part and using part of the value of a word counter as a lower address part for generating access address. CONSTITUTION:Under the control of a direct memory access control circuit 5, direct memory access between memories 2 and 3 is performed. The transfer starting address of the memory 2 is generated by all bits (upper address part) of the memory address register MAR4 for access control over the memory 2 and the lower bits (lower digit address part of the number of transfer words) of the word counter register WCR5. By the address, access to the memory 2 is attained and the read data is sent to the memory 3 through a data line 8. Thus, the amount of hardware is reduced and a load on software is reduced.

Description

Detailed Description of the Invention (1) 0 Technical Field of the Invention The present invention relates to a memory addressing method in which a memory access is generated from an address to be accessed in a memory tube, a value in a memory address register, and a value in a word count register. related to

(2)0 Background of the Invention Conventionally, there is a direct memory access method for transferring data from one memory to another between two memory memories, and the memory address register and word count are used to control this method. Unless each register has enough hardware to accommodate the maximum number of bits that must be handled, it will not be possible to handle all of the direct memory accesses between memories. Therefore, as the memory capacity increases, the amount of hardware for the registers described above also increases.In addition, in platforms where the word length of the address is longer than the word length of the data, software is required to set the registers, etc. An increase in the load cannot be avoided.

(3), Prior art and problems Conventional direct memory access method 1111 As shown in the figure, first the transfer start address is set in the memory address register a by the direct memory access control circuit, and the number of words to be transferred is stored in the word current register C. Write down the sound control circuit. After the data at the address of memory d indicated by the address of register a is transferred to another memory, the value of register a is counted up by the value t1, and the value of register C is counted down by the value t-1. This operation is repeated until the value of register C becomes zero.

In data transfer using this method, each register must be able to hold the maximum address and number of words related to the transfer, but as the amount of data transferred increases, #'i
However, it is not uncommon for each register to use all of the word lengths it handles. Nevertheless, the hardware must have the maximum capacity to handle what it has to do. Furthermore, when hardware is provided to enable such processing, if the word length of the address is longer than the word length of the data, there is a drawback that the software load increases when setting the registers, etc. .

The present invention was devised in view of the drawbacks of the conventional methods as described above, and its purpose is to reduce the amount of hardware and reduce the load on software.
The purpose of this invention is to provide a J addressing scheme.

(5) 1 Structure of the Invention The object of the present invention is to provide a memory addressing method in which memory is accessed using a memory address register and a word count register. This is achieved by performing the access to the memory while generating the access address by using at least a part of the value of the word count register as the upper address part and the lower address part of the access address.

(6) Example of 1 invention Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The m2 diagram shows an embodiment of the invention. In the figure, 1 is a direct memory access control circuit, and under the control of this circuit, access is performed between memory 2 and memory 3 using the direct memory access method. This is a memory address register in which the upper address part of the access address used for

Reference numeral 5 denotes a word count register in which the control circuit 1 sets the number of words to be accessed in the memory 2, and outputs at least a part of the number as the lower address part of the access address.

Further, 6 and 7 are a memory address register and a word count register corresponding to registers 4 and 5, respectively, and are registers used for accessing the memory 3.

A data line 8 connects the memory 2 and the memory 3.

The addressing of the memory system having the above configuration in the C7 section will be explained below.

In the direct memory access method, first, the direct memory access control circuit 1 sets a memory address register (hereinafter abbreviated as MAR) 4, which controls access to the memory 2, as shown in FIG. At the same time, the number of words t to be accessed in the memory 2t is set in the word count register (hereinafter abbreviated as WCR) S, as shown in FIG.

Similarly, the direct memory access control circuit IK sets the specified number of baskets in MA]1g and WCR7, respectively.

Then, the transfer start address f of the memory 2, which is located as M in FIG.
MAR6 is generated from the lower address part of the number of transfer words), accesses the address in memory 2 specified by that address, reads data from there, and sends it to memory 3 via data @8\. The above data is written to the write address generated using the values of WCH7 and WCH7.

This transfer operation is performed by subtracting 1 from WCR each time data is transferred. At that time, in the above example, if a digit error occurs from the 7th bit of WCR, 1 is also added from MAR in response.

Then, when the WCR becomes zero, the above transfer operation is ended.

In the above example, the number of transfer words is limited to the number of words (1024) that can be indicated by the word length of 10 bits of WCH, and the transfer start address is an MA that cannot indicate the lower 6 bits of MA.
Since it is specified by the value of R, the address #i6 pit is set only when the maximum number of words that can be specified (64) t.As can be seen from this, according to the present invention, the above example Now, the hardware can be reduced by 16 bits for MAR and 6 bits for WCR, totaling 12 bits. As a result, if the word length of the address is longer than the word length of the data, the negative 1fI due to software in setting MARlWCR can be reduced.

In the above embodiment, access address generation tMA
A case will be described in which IL and wciioiit are fixed, but they may be made variable. It is also possible to change the transfer order from the smaller address to the larger address without adding or changing hardware. Furthermore, the present invention can be applied to address-rendering methods other than the left-left memory access method.

(7) If the cost is more than the effect of one invention, the present invention can reduce the hardware required for memory access by +11% (21%, it is possible to reduce the software load in the reactive system). be,

[Brief explanation of the drawing]

Figure 1 shows the configuration of the main parts necessary for the conventional method, Figure 2 shows the configuration of the main parts of the embodiment of the present invention, and Figure 3 shows the access address generated by the invention and its respective address parts. FIG. In the figure, 1 is a direct memory access control circuit, 2.3 is a memory, 4.6 is a memory address register, 5.7 is a word count register, and 8 is a data line. 1 patentee: Fujitsu Limited No. 111 No. 311

Claims (1)

[Claims] In a memory addressing method in which memory is accessed using a memory address register and a word count register, the value of the memory address register is used as an upper address part of the memory access address,
A memory addressing method characterized in that the memory is accessed while generating the access address using at least a part of the value of the word count register as a lower address part of the access address.