JPS62145346A - Data transfer method - Google Patents

Abstract

PURPOSE:To perform data transfer efficiently between a processor with 2n-bit width and a frame memory where image data with (n)-bit width is stored by providing an interface between the both. CONSTITUTION:When image data is transferred from the frame memory 12 to the processor 11, (n)-bit image data stored in the 1st address of the frame memory is sent to the interface 13 and stored and (n)-bit image data stored in the 2nd address succeeding to the 1st address is sent to the interface 13, which outputs the image data stored in the 1st and the 2nd addresses to a data bus 14 on the side of the processor 11 as (2n)-bit data. Further, when image data from the processor 11 is stored in the frame memory 12, the (2n)-bit image data from the processor is sent to the interface 13, which divides the data into the high-order and low-order (n)-bit image data and stores them in the frame memory 12.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a data transfer method, and particularly to a data transfer method that efficiently transfers data between a 2.n-bit width processor and a frame memory that stores n-bit width image data. Regarding possible data transfer methods.

<Prior art> In image processing systems, for example, λ- is an industrial camera (IT
In some cases, the image captured in step V) is temporarily stored in a frame memory, and then the hindlimb image is read from the frame memory and subjected to predetermined image processing. In such image processing, as a matter of course, it is necessary to transfer image data between the image processing processor and the frame memory.

Incidentally, depending on the system, the frame memory stores image data in units of n bits (for example, 8 bits), and the processor stores image data in units of 2.n bits. There is a system that can process images in units of (16 bits).

In such a system, when data is written from the processor to the frame memory, image data is packed into the upper 8 bits or lower 8 bits and sent to the interface, after which the data is interfaced, converted into 8-bit data, and transferred to the frame memory. That's what I do. or,
When transferring image data from the frame memory to the processor, 8-bit image data is also sent to the interface9.
After that, the image data is packed into the upper or lower 8 bits through an interface and transferred to the processor. That's what I do.

<Problems to be Solved by the Invention> However, the conventional transfer method has a problem in that the transfer efficiency is poor because the processor can only use 8 bits out of 16 bits.

For example, when a processor retrieves a piece of data from external memory
The overhead required to read (n bits) is calculated by Δ the time required to read data from external memory after a1 access.
If it is a, it will take (a+Δa) time,
Therefore, for two data (2・n bits), 2・
A time of (a+Δa) is required.

Also, if b is the overhead required for the processor to write one piece of data (n bits) to external memory, and Δb is the time it takes for the data to be written to external memory after access, then
(b+Δb) time is required, so for two data (2・n bits), 2・(b+Δb)
time will be required.

From the above, an object of the present invention is to provide a data transfer method that can efficiently transfer data to each other even when the processor has a 2·n pit width and the frame memory has an n bit width.

Means to solve problems〉 The figure is a block diagram of a system implementing the present invention.

11 is a 16-bit wide processor, 12 is a frame memory that stores 8-bit image data, 13 is an interface arranged between the processor and the frame memory, and 14
15 is a 16-bit data bus on the processor side, and 15 is an 8-bit data bus on the frame memory side.

Processor 11 with a pit width of 2・n(=16) and n(=8
) frame memory 12 that stores image data of pit width;
An interface 13 is provided between them.

When transferring image data from the frame memory 12 to the processor 11, the n-bit image data stored at the first address of the frame memory is transferred to the interface 1.
At the same time, the n-bit image data stored at the second address following the first address is sent to the interface 13, and the image stored at the first and second addresses is sent to the interface 13. data 2・n
Data bus 14 on the processor 11 side as bit data
Output to .

Also, the image data from the processor 11 is transferred to the frame memory 1.
2, the processor sends a total of 2·n bits of image data to be stored in two consecutive addresses in the frame memory to the interface 13, and first the lower n bits of image data are stored in the frame memory via the interface. After outputting the side n-bit data to the data bus 15 and storing it in the frame memory, similarly store the upper n-bit image data in the frame memory.

<Example> The figure is a block diagram of a system implementing the present invention.

11 is a 16-bit wide processor, 12 is a frame memory that stores 8-bit image data, 13 is an interface arranged between the processor and the frame memory, and 14
1 is a 16-bit data bus on the processor side, and 15 is an 8-bit data bus on the frame memory side.

The interface 13 is the first to third path buffer section 1
3a, 13b, 13c, and a timing control section 13d called a state machine.

The first nopass puffer section 13a is the frame memory 12
An 8-bit latch circuit LCH stores 8-bit image data read from the first address of data bus 14
It has eight path buffers BFa that output to the top eight lines.

The second path buffer section 13b has eight path buffers BFb for outputting the image data of the upper 8 points of the 16-bit data outputted from the processor 11 to the 8-bit data bus 15 on the frame memory side.

The third path buffer unit 13c includes an 8-side path buffer BFc that outputs n-bit image data to the lower 8 lines of the 16-bit data bus 14 of the processor 11, and
It has eight pass buffers BFd for outputting the lower 8 bits of image data of the 16-bit data outputted from 1 to the 8-bit data bus 15 on the frame memory 12 side.

The timing control unit 13d controls the timing of data transfer by appropriately inputting timing signals to each path buffer and latch circuit.

Now, the processor 11 for image processing continuously stores images captured by an industrial camera or images obtained by predetermined image processing in each address of the frame memory 12, and also stores the images stored in the frame memory 12. Image data is read continuously from each address and predetermined image processing is performed.

Therefore, when transferring image data from the frame memory 12 to the processor 11, the image data read from two consecutive addresses are arranged in series to generate a total of 16 bits of image data, and the image data is transferred to the processor 11 at once. Can be transferred. Furthermore, when transferring image data from the processor 11 to the frame memory 12, the image data to be stored in two consecutive addresses can be arranged in series to generate 16-bit image data and transferred at once. .

If two pieces of image data can be transferred at once in this way, the transfer time can be shortened and the system throughput can be improved.

Now, when a request to transfer one screen worth of image data from the frame memory 12 to the processor 11 occurs, a read control section (not shown) reads 8-bit image data from the first address of the frame memory 12 and transfers it to the interface 13.
and stored in the latch circuit LCH of the first pass buffer 13a.

After that, the read control unit advances the address by one and reads the (i-th) address.
+1) Send the next 8-bit image data from the address to the interface 13.

The timing control unit 13d of the interface 13
+ 1) At the timing when the image data of the address is transferred, the bus buffers 7BFa and BFc of the first and second pass buffer sections 13a and 13c are triggered to latch LCH.
The 8-bit image data read from the first address stored in is the upper data, and the (i'+1
) The 8-bit data read from the address is output as lower data to the 16-bit data bus 14 on the processor 11 side, and then the processor 11 takes in the 16-bit data.

Thereafter, the above process is repeated and one screen worth of image data stored in the frame memory 12 is taken into the processor 11.

On the other hand, if a request to transfer image data to the frame memory 12 occurs from the processor 11, the processor 11 transfers the image data to the frame memory 12.
The two image data are arranged in series and output to the 16-bit data bus 14 as 16-bit data.

The timing control section 13d triggers the path buffer BFb of the second path buffer section 13b at the timing when the 16-bit data is transferred from the processor 11.
The upper 8 bits of image data of the bit data bus 14 are input to the 8-bit data bus 15 on the frame memory 12 side, and a write control section (not shown) stores the image data at the first address of the frame memory 12.

Next, the timing control section 13d triggers the pass buffer BFd of the third pass buffer section 13c to output the lower 8 bits of image data to the 8-bit data bus 15 on the frame memory 12 side, and the write control section (not shown) The image data is stored at the (i+1)th address of the frame memory 12.

Thereafter, the above processing is continued and a predetermined image is stored in the frame memory 12.

From the above, according to the present invention, if the overhead required for the processor 11 to read one piece of data (8 bits) from the frame memory is a1 and the time for reading data from the frame memory 12 is Δa, then the overhead required for the processor 11 to read one piece of data (8 bits) from the frame memory 12 is Only the time (a+2·Δa) is required, and the data reading time can be shortened compared to the conventional method.

Also, the overhead required for one processor 11 to write one piece of data (8 bits) to the frame memory 12 is
The time it takes for data to be written into the memory 12 for one frame is Δ
b, then for 16-bit data (b+2・Δb
), the data writing time can be reduced compared to the conventional method.

Note that the above is a case where the processor can process 16 bits and the image memory can read and write data in 8 bit units, but if the processor can process 24 bits and the image memory can read and write data in 8 bit units, 8
It is also possible to separate the images into three parts for each focus and process them in the same way.

<Effects of the Invention> According to the present invention, a processor with a width of 2·n bits and a
An interface is provided between frame memories that store bit-width image data, and when image data is transferred from the frame memory to the processor, the first frame memory
The n-bit image data stored at the address is sent to the interface to be stored, and the n-bit image data stored at the first address (
ζ The n-bit image data stored in consecutive second addresses is sent to the interface, and the interface transfers the image data stored in the first and second addresses into two consecutive addresses.
When outputting n-bit data to the data bus on the processor side and storing image data from the processor in the frame memory, a total of 2.n bits of image data stored in two consecutive addresses in the frame memory from the processor is interfaced. The configuration is such that the image data of the upper or lower n bits is first stored in the frame memory via the interface, and then the other image data is stored in the frame memory. Even when the memory has a width of n bits, data can be mutually transferred efficiently.

[Brief explanation of drawings]

The figure is a block diagram of a system implementing the present invention. 11--Processor, 12--Frame memory, 13--Interface, 14--16-bit data bus, 15--8-bit data bus 13a-13c--7 first to third bus buffers, 13
d: Timing control section, LCH: Latch circuit

Claims (1)

[Claims] 2. An interface is provided between an n-bit width processor and a frame memory that stores n-bit width image data, and when image data is transferred from the frame memory to the processor, the first frame memory The n-bit image data stored at the address is sent to the interface for storage, and the n-bit image data stored at the second address following the first address is sent to the interface, and the interface When outputting the image data stored at the second address as 2·n bit data to the data path on the processor side, and storing the image data from the processor to the frame memory,
A total of 2.n bits of image data stored in one address is sent to the interface, first the upper or lower n bits of image data are transferred to the frame memory via the interface, and then the other image data is transferred to the frame memory. A data transfer method characterized by: