JPH05257458A - Address generating circuit for memory - Google Patents

Abstract

PURPOSE:To enable the efficient use of a memory corresponding to variable screen size by converting the H-directional and Vdirectional logical addresses of a screen image generated by a logical address generation part into physical addresses of an actual memory by an address conversion part by using the H-and Vdirectional sizes of the screen image. CONSTITUTION:The H-directional logical address and V-directional logical address obtained by the address generation part 1 are converted into the physical addresses of the memory 3 by the address conversion part 2 by using an expression mentioned below according to those logical addresses and the H- directional or V-directional size of the screen image. Namely, the conversion is carried by using (V-directional address)X(H-directional size of screen)+(H- directional address) or (H-directional address)X(V-directional size of screen)+(V- directional address). Consequently, a function for varying and outputting addresses is provided on the assumption that memories having various capacities are connected for the screen image.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address generating circuit of a memory, and more particularly, in a motion compensation predictive coding apparatus or the like, which is an LSI, writes image data in a frame memory or stores a plurality of frames in which image data is stored. The present invention relates to an address generation circuit for reading data from a memory and performing motion compensation interframe coding or motion compensation frame interpolation coding.

[0002]

2. Description of the Related Art In the above motion compensation predictive coding apparatus, etc. for coding image data,
DRAM as a frequently used memory is 256K (2
56k × 1, 64k × 4), 1M (1M × 1, 256k)
X4), 4M (4Mx1, 1Mx4, 512kx8, 2
56k × 16) etc.

In these DRAMs, the screen size was fixed, but in the future, the DRAM will be used as a frame memory of a motion compensation predictive coding apparatus capable of handling the screen size variably.
However, in the conventional technology, when the above-mentioned DRAM is used according to the screen size, for example, as shown on the left side of FIG. When handling a screen image IM that is long in the (horizontal) direction, the amount of data per screen is less than or equal to the capacity of the DRAM, but when writing data to the DRAM with the screen image IM, a larger capacity DRAM 'is used. May be needed.

Therefore, it is an object of the present invention to realize an address generation circuit of a memory having a function capable of variably outputting an address on the assumption that memories having various capacities are connected to a screen image.

[0005]

In order to achieve the above object, an address generating circuit of a memory according to the present invention provides logical addresses in the H direction and V direction of a screen image as conceptually shown in FIG. Using the generated logical address generator 1, both logical addresses, and the size of the screen image in the H direction, from the logical address, (the logical address in the V direction) ×
An address conversion unit 2 for converting a physical address of the actual memory 3 represented by (size of the screen image in the H direction) + (logical address in the H direction).

Further, according to the present invention, the address conversion unit 2 described above is used.
Instead of using both logical addresses and the size of the screen image in the H direction, (H direction logical address) × (size of the screen image in the V direction) +
You may use the address conversion part 2 which converts into the physical address of the actual memory 3 represented by (the logical address of V direction).

In the above case, as shown in FIG. 3, the address translation unit 2 outputs the physical address as it is at all bits simultaneously, or outputs it in a multiplexed form.
Is preferably selected.

Further, as shown in FIG. 4, when the physical address is multiplexed and output, the address converting unit 2 may expand the output to double or more in the same time slot and output it. ..

Further, as shown in FIG. 5, the address conversion unit 2 switches the row address and the column address on the duplicated side of the physical address so that the address selection becomes 2: 1. You can

[0010]

The present invention shown in FIG. 1 will be described with reference to FIG.
The image data IM is considered in the H (horizontal) direction and the V (vertical) direction (screen image), and there are two systems of an address (row address) in the H direction and an address (column address) in the V direction within one cycle. It is easier to process the data when there is a, but considering the case where one memory does not match the screen image as in the example on the left side of Fig. 2 (b), it is converted to the physical address of the memory. Memory 3
It enables highly efficient use of.

Therefore, according to the present invention, according to the logical address in the H direction, the logical address in the V direction and the size of the screen image in the H or V direction obtained from the address generating unit 1, these logical addresses are converted into the address converting unit 2. Is converted into the physical address of the memory 3 by the following formula. (Address in V direction) x (Size of screen in H direction) +
(Address in H direction) Or (Address in H direction) x (Size of screen in V direction) +
(Address in V direction)

By doing so, as shown in the example on the right side of FIG. 2A or 2B, writing / reading of the memory 3 can be efficiently performed.

Further, in the present invention, as shown in FIG.
Physical address X1 in the H direction created by the address conversion unit 2
To Xm and all bits X1 to Xm, Y1 to Yn (m + n bits) of physical addresses Y1 to Yn in the V direction are output as they are in state A shown in FIG. Or H as in states B and C
By having a function of selecting whether to output the physical address in the directional direction and the physical address in the V direction after multiplexing, it is possible to easily use the DRAM for various screen sizes.

In the case of the above multiplex output,
As shown in FIG. 4, the address conversion unit 2 outputs the state B (H-direction address X1 to Xm) and C (V-direction address Y1) which are expanded in the same time slot and output at least twice in the same time slot. ~ Yn), the necessity of buffering the output physical address outside the circuit can be reduced, and the memory 3 can be used easily.

Further, as shown in FIG. 5, the address conversion unit 5 selects an address by exchanging the row address and the column address on the duplicated side of the physical address in the state A. If there is a state C that is set to 2: 1, in the above case (FIGS. 3 and 4), 3: 1 address selection is always necessary, but since only two states occur, 2: 1 selection is performed. Will be good and the hardware scale can be reduced.

[0016]

FIG. 6 shows an embodiment of the address generating circuit of the memory according to the present invention shown in FIG. 1, which is an embodiment applied to the motion compensation frame interpolation coding apparatus 10. .. Motion-compensated frame interpolation coding is a method in which the screen to be coded is divided into blocks, the blocks with the smallest error are searched from the blocks to be coded in the immediately preceding and immediately following screens and their neighborhoods, and both and both are averaged. In this case, the block with the smallest error in the frame is inter-frame coded.

Therefore, since the encoder 10 normally accesses a plurality of frame memories, in this embodiment the frame memories for eight planes are accessed. Therefore, in addition to the address, which frame memory is accessed. 3 bits (BANK) indicating is added.

Therefore, the logical address generated by the address generator 1 is BANK 3 bits (B00, as shown in the figure).
Up to B02), 8 bits in the H direction (H00 to H07), and 12 bits in the V direction (V00 to V11), a total of 23 bits.

The address conversion unit 2 that receives the 23-bit logical address is a register 2 that stores the size in the H direction.
1, a multiplier 22 for multiplying the H direction size by the V direction logical address from the address generator 1, an adder 23 for adding the multiplication result of the multiplier 22 and the H direction logical address, and a BANK bit And a latch circuit 24 for latching the output bit of the adder 23 and matching the timing to give a 23-bit physical address to the frame memory (DRAM) 3.

Therefore, in this address conversion unit 2, the logical address from the address generation unit 1 is calculated by the following formula: (logical address in V direction) × (H-size of screen) + (logical address in H direction) ( 1) to 23-bit physical address (B0
2 to B00, Z19 to Z00).

In the above equation (1), H and V are just exchanged to obtain the following equation: (logical address in V direction) × (H-size of screen) + (logical address in H direction) By 2), a logical address can be converted into a physical address in exactly the same way.

7 to 10 show an embodiment of the address conversion shown in FIG. 2. In FIG. 7, a screen image of a screen size (480 pixels in the H direction 20 × V direction 24) is shown. DRAM (H direction 32x)
An example in which the data is stored in 1024 pixels in the V direction) is shown. FIG. 8 shows a state in which the data is stored in the DRAM after being converted into a physical address according to the above equation (1).

FIG. 9 shows a concrete 10-bit state in which the logical address of FIG. 7 is converted into the physical address of FIG. 8. In the physical address, the pixel number is the same as that of the DRAM.
Will be the address of.

Further, FIG. 10 shows a screen of 352 (H direction) × 288 (VIF direction) (CIF size) which is often handled by an image device.
This is an example of storing data in a DRAM of 2 × 512 pixels, and if the logical address (address of screen image) in the same figure (a) is left, only one screen of data can be stored in the DRAM. When the data is converted into a physical address and stored as shown in FIG. 8B, data for two screens can be stored in the same DRAM.

FIG. 11 shows a circuit embodiment which realizes the address selection shown in FIG. 3. In this embodiment, the output bit (m + n = 23) of the address conversion unit 2 in which only the latch circuit 24 is shown. A bit T) for inputting all bits, a terminal T1 for inputting only 8 bits of the H-direction address of these m + n = 23 bits, and a terminal T1 for these m + n
, A terminal 20 for inputting only 12 bits of the V-direction address of 23 bits is included.

In order to select these three terminals T0 to T2, the selector 20 is further provided with a row / column address switching signal ADRS from the address generator 1 (not shown).
A control terminal S1 for receiving EL and a control terminal S2 connected to a switch SW for selecting all-bit output / multiplex output are provided. These control terminals S1 and S2 are shown in FIG. 3 (b). When the logical relationship as shown is obtained, a state A in which all bits are output, a state B in which only an m-bit H-direction address is output, and a state C in which only an n-bit V-direction address is output occur. , States B and C are controlled so as to occur in one cycle, and thus, a multiplexed output is obtained. The signal ADRSEL is always output to the outside because it is used as an address multiplex timing signal when outputting all bits of the address.

FIG. 12 shows a circuit embodiment for realizing the address selection shown in FIG. 4. The difference between this embodiment and the embodiment of FIG. 11 is that the multiplexed outputs of states B and C are In order to output 2m bits in state B and 2n bits in state C when they occur, the terminal T1 of the selector 20 is set to 2m bits (16 bits) and the terminal T2 is set to 2n bits (24 bits). Is.

FIG. 13 shows a circuit embodiment for realizing the address selection shown in FIG. 5. The difference between this embodiment and the embodiment of FIG. 11 is that all m + n (2
3) A state A and a state B form a multiplex in one cycle by creating a state B in which the row address and the column address in the bits Z00 to Z19 and B00 to B02 are exchanged, and thus the state C is formed. Therefore, the connection line from the latch circuit 24 to the selector 20 selects 2: 1 for all bit output format in state A or multiplex output format as shown in the figure. It is input to the selector 20 and S
Either format is selected from the outside by W1. At this time, the ADRSEL signal for switching between the row address and the column address is always output to the outside in order to cope with the multiplex outside the device in the all-bit output format.

[0029]

As described above, according to the address generating circuit of the memory of the present invention, the logical addresses in the H direction and the V direction of the screen image generated by the logical address generating unit are
Since the size of the screen image in the H / V direction is used to convert to the physical address of the actual memory by the address conversion unit, it is possible to efficiently use the memory corresponding to the variable screen size.

[Brief description of drawings]

FIG. 1 is a block diagram showing in principle the configuration of an address generation circuit of a memory according to the present invention.

FIG. 2 is a block diagram for explaining the operation of the present invention.

FIG. 3 is a diagram showing a mode (part 1) of address selection by an address conversion unit according to the present invention.

FIG. 4 is a diagram showing a mode (part 2) of address selection by the address conversion unit in the present invention.

FIG. 5 is a diagram showing a mode (3) of address selection of an address conversion unit in the present invention.

FIG. 6 is a diagram showing an example of the present invention.

FIG. 7 is a diagram showing a relationship between a screen size and a DRAM.

FIG. 8 is a diagram showing an example of data storage in a DRAM by a physical address according to the present invention.

FIG. 9 is a diagram showing an example of address conversion in the present invention.

FIG. 10 is a diagram showing a comparison between a conventional example and a method of using the DRAM of the present invention.

FIG. 11 is a diagram showing an embodiment (No. 1) of the address selection circuit in the present invention.

FIG. 12 is a diagram showing an embodiment (No. 2) of the address selection circuit in the present invention.

FIG. 13 is a diagram showing an embodiment (part 3) of the address selection circuit in the present invention.

[Explanation of symbols]

 1 address generating unit 2 address converting unit 3 memory (DRAM) 20 selector

Front page continued (72) Inventor Tsutomu Fujigo 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (5)

[Claims] 1. A logical address generator (1) for generating logical addresses in the H direction and V direction of a screen image, and using both logical addresses and the size of the screen image in the H direction, Logical address in V direction)
An address conversion unit (2) for converting to a physical address of the actual memory (3) represented by × (size of the screen image in the H direction) + (logical address in the H direction), and Address generation circuit of memory. 2. A logical address generator (1) for generating logical addresses in the H direction and V direction of a screen image, and using both logical addresses and the size of the screen image in the H direction, Logical address in H direction)
An address conversion unit (2) for converting a physical address of the actual memory (3) represented by × (size of the screen image in the V direction) + (logical address in the V direction), and Address generation circuit of memory. 3. The address conversion unit (2) according to claim 1 or 2, characterized in that it is possible to select whether the physical address is output as it is for all the bits as it is, or the physical address is multiplexed and output. Memory address generation circuit. 4. The address translating unit (2), when the physical address is multiplexed and output, is expanded to double or more and output in the same time slot. Address generation circuit of the described memory. 5. The address conversion unit (2) is characterized in that the address selection is made 2: 1 by exchanging a row address and a column address on the duplicated side of the physical address. 5. An address generation circuit of the memory according to item 4.