JPH0311473A - Video processing system - Google Patents

Abstract

PURPOSE:To perform a fast processing with simple configuration by holding input digital data in every constant unit, and performing the cyclic processing of the output of an arithmetic part which calculates a parameter required for a video processing, etc., with a conversion part provided with a fast memory and a light arithmetic part, etc. CONSTITUTION:Digital data from an input part 10 is held at a memory in the arithmetic part 20 in every constant unit, and the constant number of constant units is arithmetically processed, and the parameter required for the video processing is calculated. The parameter is inputted to the fast memory of the conversion part 30, and the branch output of the fast memory is processed at a reduction part, and is inputted circularly to the fast memory, then, it is outputted after a processing such as an integrating processing, etc., is applied, thereby, a video processing system capable of performing the fast processing can be obtained with simple circuit configuration.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital video processing system, and particularly to a video processing system effective for real-time video processing and display, real-time image analysis, and the like.

[Prior Art] Conventionally, for example, in image processing systems that recognize images based on features extracted from input images, digital processing has been used due to the sophistication, reproducibility, and quantitative nature of processing results, and the diversity of processing. systems are often used. In this digital processing system, it is necessary to treat the video as a collection of pixels, and the calculations regarding the pixels become enormous. Therefore, although there have been attempts to speed up video processing using a dedicated IC for image processing, the purpose of this dedicated IC is extremely narrow and cannot be applied to a wide range of video processing.

In order to solve these problems, conventionally, a neighborhood processing section processes pixel data in fixed neighborhood units, a calculation section calculates the parameters necessary for video processing based on this data, and a conversion section processes the pixel data based on this data. A video processing system has been proposed that performs processing such as integration based on the processing results of the parts.

[Problem to be solved by the invention]

However, in conventional video processing systems, the neighborhood processing section is configured by combining a line memory and a flip-flop, and its circuit configuration is not sufficiently simplified.

The present invention was created to solve the above problems, and
The object of the present invention is to obtain a video processing system that has a simple circuit configuration, can be applied to a wide range of video processing, is capable of faster processing than a general-purpose ultra-large computer, and has high cost performance.

[Means to solve the problem]

The video processing system according to the present invention does not have a neighborhood processing section, that is, it has an input section into which digital data is input, holds the digital data input to this input section in units of a fixed number, and stores this fixed number of digital data. A calculation section that calculates the parameters necessary for video processing based on the data of the number of objects, and the output of this calculation section is input to a high-speed memory, and the output of this high-speed memory is branched and sequentially passed through a light calculation section and a switching means. The present invention is characterized in that it includes a converter formed by converting the high-speed memory back to the above-mentioned high-speed memory.

〔Example〕

The present invention will be explained below based on illustrated embodiments.

In FIG. 1, the video processing system has an input section 10 into which pixel data is input.
The data is sequentially processed in the calculation section 20 and the conversion section 30. In the calculation unit 20, calculation processing such as numerical calculation or state calculation is performed, and in the conversion unit 30, post-processing is performed to obtain the final processed image and feature amount.

As shown in FIG. 2, pixel data PIT is generally arranged sequentially for each scan line. In general, in image processing, as shown in FIG. 3, for example, 3×3 pixel data P
P (!-1>・(j・1)・P+・(j−1+・P
l・jsPi・(j・1)・P(!.+1+ (j−1
1, P (direct. Ill J% P (1411, (j+1
Various processes are applied to +. Note that the size of this processing area may be set to 2×2, or may be set to a larger area, or may have a shape other than a square. Normally, neighborhood processing is required to maintain such 3×3 and other areas, but this neighborhood processing section is omitted in the present invention.

The pixel data is input to the calculation unit 20, where parameters necessary for video processing are calculated. For example, the average density is one of such parameters, and can be determined by the calculation unit 20.

The calculation unit 20 includes a state calculation unit 21 and a numerical calculation unit 22, as shown in FIG. In the state calculation unit 21, the number of connections, an index of whether the pixel is a processing target, parameters T, F, D, and E for determining the Euler number, and a comparison signal representing the state of the processed image and its vicinity. , and others are calculated. On the other hand, the numerical calculation section 11 performs density averaging, first-order differentiation, second-order differentiation, filter processing, and other processing. The processing of these calculation units 21 and 22 is sped up by hardware pipeline processing.

FIG. 5 shows the configuration of the calculation section 20. Although the calculation section 20 is shown in detail in this figure, the state calculation section 21 is omitted.

In the calculation unit 20, image data stored in any of the memories 41, 42, and 43 is sent to a multiplexer (MUX) 49.
is selected and input. Each memory 41.42.4
3 is connected to the multiplexer 49, and is also connected to the integration section 2 of the calculation section 20 via buffers 51, 52, and 53.

That is, one of the memories 41, 42, 43 stores the input image, and the other memory stores the input image.
The processing result of the calculation unit 20 is stored via 2.53.

The arithmetic unit 20 includes three flip-flops 23, 24, and 25 connected in series, a multiplier 26, and a selector 27. The first flip-flop 23 receives pixel data Plj along one scan line every clock signal as shown in FIG. Output to 26. The second flip-flop 24 delays the pixel data input from the first flip-flop 23 by l clocks and outputs the delayed pixel data to the third flip-flop 25 and the multiplier 26 . The third flip-flop 25 is
The pixel data input from the flip-flop 24 of
The signal is further delayed by one clock and output to the multiplier 26.

Therefore, three consecutive pixel data are input to the multiplier 26 at the same time.

The multiplier 26 multiplies each pixel data by an appropriate numerical value and outputs the result of the calculation to each input terminal of the selector 27. The selector 27 guides the multiplication results input to each input terminal to an arbitrary output terminal or distributes them to a plurality of arbitrary output terminals. The integrating unit 28 integrates the data of the operation results derived from the selector 27 while performing addition, subtraction, and other operations.

The calculations within this integration unit 28 are performed hierarchically, and different calculations are performed simultaneously in each layer and passed to the next stage in a pipeline process, which improves the calculation speed of the entire calculation circuit. .

Now, as an example of the calculation content in the calculation unit 20, a calculation method for obtaining a 5obel operator in the y direction, which is one of the methods for emphasizing edges, will be described. This 5o
The bel operator calculates ΔyfiJ =P(i-1++(j-11+2Pt++j-n+P() in the 3×3 convolution in FIG.
;・Yi), (j-th (P (i-11+ (j611
+2 P it tihn + P <=. l) + (
j, 1) ).

The pixel data stored in the memory 41 is read out sequentially, and the pixel data P(i11+ +j-11, P it (
j-11, P(i. -+1+ (j-H+ 2 P i, (j-n
+P +i. I), (j-11 are calculated and stored in Pi+fj-1 of the memory 42. Similarly, pixel data P (!-11, (j, 1
1, Pi++j. 1. , P (i*I)+fjl) are read, and the arithmetic unit 20 calculates (-1) and (
-2) and (-1), and the sum is P in the memory 42.
It is stored in L+ (Ji). This kind of processing is 1
This is done for the screen (512x512 pixels). Note that when data is stored in the memory 42, the pixel data Pi is rearranged and arranged in the vertical direction, unlike in FIG.

Next, among the data read out from the memory 42, the data Pi++j-11 and Pit(ji+) are transferred from the flip-flops 25 and 23 to the multiplication unit 26 and then to the integration unit 2.
8, the sum of these is determined, and thereby the 5obel operator Δyfij in the 3×3 convolution is determined.

This processing result is stored in the memory 43 at P it F-th, and such processing is applied to all pixel data in one screen.

Other arithmetic operations such as smoothing or differentiation are performed in exactly the same manner.

The calculation results in the calculation unit 20 are stored in the memory 41.
42 or 43, and then manually inputted to the conversion unit 30 (FIG. 1) to perform final video processing or to obtain feature quantities.

The conversion section 30 is conceptually configured as shown in FIG. ing. A selector 33 is connected to the input of the high-speed memory 31, and the output of the light arithmetic unit 32 is input to this selector 33. Data D1 is input to the address input of the high speed memory 31, and the selector 3 is input to the data input of the high speed memory 31.
3 output terminals are connected. Data D2 is input to the selector 33 in parallel with the output of the light calculation section 32, and the selector 33 selectively guides the output of the light calculation section 32 or the data D2 to the high speed memory 31. As the high-speed memory 31, a high-speed static RAM or the like can be used.

By returning the data that has passed through the light calculation unit 32 to the input side of the high-speed memory 31, it is possible to repeatedly perform the same calculation process on one piece of data, or to perform the same process on a series of data groups and then sequentially store them in the high-speed memory 31. It also becomes possible to perform extremely diverse processing such as data integration, data gradual reduction, and data successive comparison. It is also possible to use it as a table by giving an address to the high-speed memory 31 using the data D1 and reading out the data stored at that address.

As the light arithmetic unit 32, for example, an adder can be adopted. In this case, in addition to the output of the high-speed memory 31, data D3 is input to the light arithmetic unit 32, that is, the adder, and furthermore, the high-speed memory 31 is input with the signal S of C3 (chip select) or WE (write enable). Ru.

For example, when calculating the area of a binary image or a labeled image, the pixel value is specified as the address DI, the data stored in that address is output from the high-speed memory 31, and the adder 32 adds this data to D3 (here Then, set it to "1") and return the added value to the selector 33 and store it again at address D1 of the high-speed memory 31. As a result, the number of pixels of each pixel value in the image is counted, and the area of each label area is determined.

FIG. 7 shows a second embodiment of the video processing system. In this embodiment, a plurality of input units 1 are used as input units.
0 and the image memory 40 can be selected by a selector 61, and furthermore, a plurality of output units 62 and the image memory 40 can be selected by a distributor 63 as output units. Examples of the input unit 10 include a VTR camera, scanner, video deck, laser disk device, CD-ROM, optical disk, hard disk, communication I/F, and image memory. - Examples of the output section include those listed as input sections that can accept data, and image memory.

Furthermore, in this embodiment, the calculation unit 20, the conversion unit 30, the selector 61, the distributor 63, the distributor 63, and the image memory 4
A controller 64 is connected to 0, and the settings and controls are performed by the controller 64. Overall control and setting and control of the controller 64 are performed by the MPU 65. Further, complicated calculations in video processing are performed by the MPU 65. This is because if the load on the calculation section 20 or the conversion section 30 is too high, the calculation speed will drop significantly, and the processing allocation should be optimized depending on the processing content.

The light operations of the converter 30 include addition/subtraction, extraction of maximum and minimum values, numerical operations such as absolute values, comparison, AND, OR, NAND, NOR, EX-OR, E
Logical operations such as X-NOR can be freely selected and employed.

Since the conversion unit 30 is equipped with a high-speed memory 31, labeling information can be stored at high speed as a look-up table for data reference such as referring to RGB values from a so-called color code, or when labeling an image. Needless to say, it can be applied as a cache memory.

Further, the selector includes any switching means such as a wired OR.

Although the calculation unit 20 is described as processing pixel data in the above embodiment, it is not limited to pixel data, and the present invention can be applied to all digital data.

(Effects of the Invention) As described above, according to the present invention, calculations that can be applied to many processes are performed without providing a neighborhood processing unit, and the final processed video and special @ Since the conversion to obtain the quantity can be performed, an excellent effect can be obtained in that various processing can be realized at high speed with an extremely simple configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the first embodiment of the video processing system according to the present invention, FIG. 2 is a conceptual diagram showing the arrangement of pixel data, and FIG. 3 is a 3×
4 is a block diagram showing an example of the calculation section, FIG. 5 is a block diagram showing the concept of the calculation section, and FIG. 6 is a block diagram showing the concept of the conversion section. FIG. 7 is a block diagram showing a second embodiment of the video processing system. 10...Human power section 20...Calculation section 20 23.24.25...Flip-flop 30...Conversion section 1 spontaneous) 1. Display of the case 1999 Patent application No. 145098 λ Name of the invention Video processing system 3, person making the amendment Relationship to the case Patent applicant name Easel 4 Co., Ltd. Agent address 29 Shiba 5-chome, Minato-ku, Tokyo 108 No. 22 No. 5,
Column 6 of "Detailed Description of the Invention" of the specification to be amended, page 4, lines 10 to 12 of the specification of contents of the amendment' P t+-++0
-55, ... P (i-1>, fjll J
Correct as shown below.

Claims (1)

[Claims] (1) An input section into which digital data is input, and a calculation section that holds the digital data input to this input section in units of a fixed number and calculates parameters necessary for video processing based on this fixed number of data. and a converting section that inputs the output of the arithmetic section to a high-speed memory, branches the output of the high-speed memory, and returns the output to the high-speed memory via a light arithmetic section and a switching means in sequence.