JPH01276241A - Multiple interrupting device - Google Patents

Abstract

PURPOSE:To simplify a system by providing a peripheral device to generate an interruption requesting signal when the priority of its own is made higher than the priority of an interruption priority register and to activate a data bus corresponding to the priority of its own in an interruption response cycle. CONSTITUTION:When the rewrite of a priority register 7 in a CPU 1 is executed, the CPU priority registers of peripheral devices 21-23 are rewritten, and the peripheral device whose priority is higher than the priority of the CPU 1 generates the interruption requesting signal, respectively. Next, then the CPU 1 goes into the interruption response cycle, the peripheral devices 21-23 activate the data bus (1 bit) corresponding to the priorities of their own. The CPU 1 executes the interruption processing of the peripheral device having the highest priority, and the peripheral device stops the generation of the interruption requesting signal. Thereafter, in the same way as above, the interruption processing of the peripheral device having the priority higher than that of the CPU 1 is successively executed. Thus, an interruption requesting signal line can be composed of 1 line.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a multiple interrupt device in a computer/system.

<Prior Art> A multi-side input method with priority in a conventional computer system will be explained with reference to FIG. An interrupt request signal line t corresponding to each interrupt priority signal 44+45+4s is connected between the CPUI and the peripheral device 24.25126.
Connect 4 + z5 + t6 and select the highest priority interrupt among the interrupts that can be interrupted when multiple interrupts occur at the same time. Configure the receiver so that it is attached.

<Problems to be Solved by the Invention> As mentioned above, the conventional technology has the drawback of requiring interrupt request signal lines corresponding to each priority level, which makes the connection between the CPU and peripheral devices complicated. There is.

Measures to Solve Problems〉 The CPU is equipped with an interrupt priority register that holds the priority level at which the CPU can interrupt, and has a CPU interrupt priority register that is updated to the same content every time the register 1cPU is rewritten. , a peripheral device that generates an interrupt request signal when a preset own priority becomes higher than that priority, and activates a data bus (1 bit) corresponding to its own priority in the interrupt response cycle. constitutes a multiple interrupt device.

For Kusaku The operation and effects of the above configuration are shown below.

When the priority register in the CPU is rewritten, the CPU priority registers of peripheral devices are rewritten, and each peripheral device whose priority has become higher than that of the CPU generates an interrupt request signal.

Next, when the CPU enters an interrupt response cycle, the peripheral device activates the data bus (1 bit) corresponding to its own priority. The CPU processes the interrupt for the peripheral device with the highest priority, and that peripheral device stops generating interrupt request signals. Thereafter, interrupt processing for peripheral devices having higher priority than the CPU is sequentially performed in the same manner.

Therefore, the present invention does not need to be configured to accept the interrupt with the highest priority among the interrupts that can interrupt the CPU, as is the case in the past, and can be configured with a single interrupt request signal line.

<Example> An example of the present invention will be described below with reference to the drawings.

FIG. 1 shows the connection relationship between the CPUI and three peripheral devices 21, 2□, and 23.

The CPU and the three peripheral devices 21 + 22 + 23 are connected in parallel by a data bus 3 (8 lines), an interrupt request signal line t (wired OR), an interrupt response signal line 5, and a priority register write signal Ifs6. be done.

The CPUI is provided with an interrupt priority register that holds the priority level at which the CPU can interrupt, and
A CPU interrupt priority register is provided which is updated to the same contents each time I rewrites the interrupt priority register. The peripheral devices 21 to 23 generate an interrupt request signal when their own preset priority becomes higher than the priority of the CPU interrupt priority register.

Also, in the interrupt response cycle, the peripheral devices 21 to 2
It has a function to activate the data bus (1 bit) corresponding to the priority of 3.Here, the priority of each peripheral device 21 to 23 is set to 1.2.3.
(3 is the top). For example, if the CPUI priority is 3 or higher, no peripheral device generates an interrupt request signal. When the CPUI priority is rewritten to 1, the peripheral devices 21+ 2z and 23 transfer the priority 1 on the data bus from the priority register write signal line 6 to the peripheral device 2+ + 2.
2123, peripheral devices 22 and 23 with higher priority than the CPU generate interrupt request signals 42 and 43. Then, when CPU 1 enters the interrupt response cycle,
Peripheral device 22 activates pit 2 of data bus 3, and peripheral device 23 activates bit 3 of data bus 3. In this case, peripheral device 23 has a higher priority than peripheral device 22, so the CPU Performs 23 interrupt processing,
The peripheral device 23 stops the interrupt request signal 43. Thereafter, similarly, interrupt processing for peripheral devices having higher priority than the CPU is sequentially performed.

<Effects of the Invention> As described above, since a multiple interrupt system can be configured with one interrupt request signal line t, the system becomes simpler.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing an embodiment according to the conventional technology. I CPU 2+~26 Peripheral device 41~
46 Interrupt request signal 3 Data node 5 Interrupt response signal line 6 CPU priority register write signal line 7 Interrupt priority register

Claims (1)

[Claims] 1. A computer system comprising a CPU, peripheral devices, a data bus, an interrupt request signal line, and an interrupt response signal line, comprising: a CPU having an interrupt priority register that holds priorities for interrupts; a CPU priority register that is updated to the same content each time the CPU rewrites the interrupt priority register; and a CPU priority register that generates an interrupt request signal when its own priority becomes higher than the priority of the interrupt priority register. A multiple interrupt device consisting of a peripheral device that activates a data bus corresponding to its own priority in an interrupt response cycle.