JPH1011411A - Interruption control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the interruption control system of a multiprocessor system which can dynamically change the interruption information destinations of many interruption generation factors without fixing them. SOLUTION: Information (address) 41 showing an interruption factor is added to the header 44 of a frame 45 from a transmission line 1 and with this information, an interruption number 42 indicating an interruption destination in an interruption correspondence table 7 is retrieved. A flag 43 corresponding to the retrieved interruption number 42 is set to '1' and for the interruption destination that the interruption number corresponding to the flag set to '1', an interruption generating circuit 8 generates an interruption signal (9-12). The contents of the table 7 are rewritable and then the interruption factor and interruption destination are dynamically changed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt control system, and more particularly to an external control system having a plurality of processors, a common bus to which these processors are connected, and an interface function between an external transmission path and the common bus. An interrupt control unit for generating an interrupt signal for transferring data received from a transmission path to the processor.

[0002]

2. Description of the Related Art Conventionally, in an interrupt control system of this type, in an information processing apparatus using a plurality of processors and peripheral circuits, an interrupt signal fixedly allocated at a hardware design stage is used for each occurrence of an event. An interrupt signal is generated.

For example, Japanese Patent Application Laid-Open No. 62-21758 discloses a general interrupt control that recognizes an interrupt request from a peripheral device, generates an interrupt enable signal, and generates an interrupt vector corresponding to the enable signal. Techniques are disclosed.

[0004]

In such a conventional interrupt control technique, the distribution of an interrupt factor and an interrupt signal cannot be dynamically changed. The reason is that since the interrupt generation and detection circuits are all configured by hardware logic circuits, the above distribution method is fixed at the hardware design stage, and the interrupt generation factor is also fixed. is there.

SUMMARY OF THE INVENTION An object of the present invention is to provide an interrupt control system capable of dynamically changing an interrupt notification destination of a large number of interrupt occurrence factors.

[0006]

According to the present invention, a plurality of processors, a common bus to which the processors are connected, and an interface function between an external transmission path and the common bus are provided. An interrupt control unit for generating an interrupt signal for transferring data received from a transmission path to the processor, the interrupt control unit comprising: Interrupt signal generation for generating an interrupt signal to the interrupt destination processor indicated by the interrupt correspondence table stored in advance and the interrupt destination information of the interrupt correspondence table corresponding to the interrupt factor information added in advance to the received data And an interrupt control system.

A flag corresponding to the interrupt factor information is provided in the interrupt correspondence table.
A flag corresponding to the interrupt factor information is set in response to the occurrence of the interrupt factor, and the interrupt signal generating means responds to the setting of the flag to generate the interrupt destination information corresponding to the flag. Is configured to generate an interrupt signal to the interrupt destination processor indicated by.

Further, the interrupt control means has a storage means for temporarily storing the received data, and the processor of the interrupt destination reads the data stored in the storage means via the common bus in response to the interrupt signal. It is characterized by taking it.

Further, the interrupt signal generating means has a register corresponding to each of the processors, and is configured to set the interrupt signal in the register corresponding to the flag in response to the setting of the flag. It is characterized by having.

Still further, the contents of the interrupt correspondence table are rewritable.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation of the present invention will be described. An interrupt correspondence table in which interrupt cause information and interrupt destination information are stored in advance in correspondence with each other is provided, the table is indexed based on the interrupt cause, and an interrupt signal is generated at the corresponding interrupt destination obtained by the index. And send it out. By making the contents of this table freely rewritable instead of fixed, it is possible to dynamically change the interrupt notification destinations of a large number of interrupt occurrence factors.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a system block diagram of one embodiment of the present invention. Referring to FIG. 1, a plurality of CPUs (processors) 13 to 16 are connected to a common bus 17. The data separating circuit 3 is provided between the external transmission line 1 and the common bus 17 and has an interface function between these transmission lines and the common bus.

The data separating circuit 3 transfers the frame data received from the transmission line 1 to a destination indicated by a logical number of the header 44 in the frame data 45 as shown in FIG. The logical numbers correspond to the CPU 13, CPU 14, CP
U15 and CPU16 are respectively assigned in advance, and one CPU has one or a plurality of logical numbers. CPU13 ~
16 and the data separation circuit 3 are mutually connected by a common bus 17 and transfer received frame data 45.

An interrupt control unit 1 for detecting and generating an interrupt is provided to a physical interface 2 for converting the frame data from the transmission line 1 into a form that can be processed in the data separation circuit 3.
8 are connected. The interrupt control unit 18 includes an interrupt correspondence table 7 composed of a memory,
Interrupt 9, interrupt 10, interrupt 1
1 and an interrupt generating circuit 8 for generating one of the interrupt signals. These interrupt signals are allocated to the CPUs 13 to 16, respectively.

The internal bus 6 is connected to a CPU 5, a data reception controller 4, an interrupt controller 18, and a buffer memory 19. The buffer memory 19 is connected to the common bus 17 via a bus interface 20.

Next, the operation of the circuit will be described with reference to FIG. FIG. 2 shows an example of the interrupt correspondence table 7, in which a memory address 41, an interrupt number 42, and a flag 43 are stored in advance so as to correspond to each other. The memory address 41 corresponds to the logical number indicating the cause of the interrupt indicated in the frame header 44, and is shown in hexadecimal (h).

The data separation circuit 3 has a function of distributing the frame 45 coming from the transmission line 1 for each destination. In the physical interface 2, the data received from the transmission line 1 is converted into a format that can be processed in the data separation circuit 3, and the data reception control unit 4 recognizes the logical number in the header 44 of the frame 45 and The corresponding flag 43 in the interrupt correspondence table 7 indicated by the number is rewritten. The data reception control unit 4 rewrites the flag 43 and stores the received frame in the buffer memory 19.

With the rise of the flag as a trigger, the interrupt controller 18 reads the corresponding interrupt number on the interrupt correspondence table 7 and generates an interrupt signal.

For example, when the interrupt signal 9 is generated,
The CPU 13 takes over the frame addressed to itself on the buffer memory 19 via the common bus 7.

The details of the interrupt correspondence table 7 will be described with reference to FIG. 2. If the logical number "0003" is stored in the header 44 of the frame 45 received from the transmission path 1, this "0003" indicates this. The flag 43 on the table 7 is rewritten to "1". In the case where a memory is used in the table 7, for example, "0003" is a value indicating a memory address, and the bit assigned to the flag in the address "0003h" is rewritten.

When the interrupt numbers are sequentially assigned to the interrupt signals of interrupts 9 to 12 as 0, 1, 2, and 3, "000"
When the interrupt generation circuit 8 detects that the flag at the address 3h has changed to "1", it reads the interrupt number "00000000" in the address "0003h" and generates a corresponding interrupt signal. The number is "000
00000 ", the interrupt 9 is output.

Next, another embodiment of the present invention will be described with reference to FIG. In FIG. 3, the same parts as those in FIG. 1 are indicated by the same reference numerals.

Referring to FIG. 3, the interrupt control unit 18 shown in FIG. 1 is eliminated, and only the interrupt correspondence table 7 is connected to the internal bus 6. Further, interrupt signals 9 to
Registers 66 to 69 are newly added to output 12 respectively.

The four registers are connected to the internal bus 6 in a flip-flop circuit configuration, for example.
Data can be set from the data reception control unit 4 or the CPU 5.

In the example of FIG. 1, the interrupt generation circuit 8 recognizes that the flag in the interrupt correspondence table 7 has been set and generates an interrupt signal. However, in the example of FIG. 3, there is no dedicated flag detection circuit. Instead, the data reception control unit 4 identifies the value of the header 44, copies the flag of the table 7 into the corresponding register, and writes an interrupt signal to each CPU.

This embodiment has an effect that the circuit scale can be reduced in realizing the circuit as compared with the embodiment of FIG. 1 described above.

[0028]

The first effect is that the load on the common bus can be reduced in a multiprocessor system. The reason is that since the reception of the frame can be notified by an interrupt, each CPU does not need to confirm the reception of the data separation circuit via the common bus.

The second effect is that the correspondence between each CPU and a logical number can be freely changed. The reason is that the contents of the correspondence table between the logical number and the interrupt are held in a rewritable memory. In addition, this memory can be rewritten during system operation via the internal bus or the common bus.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of an interrupt correspondence table in FIG. 1;

FIG. 3 is a block diagram showing another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Transmission path 2 Physical interface 3 Data separation circuit 4 Data reception control unit 5, 13 to 16 CPU 6 Internal bus 7 Interrupt correspondence table 8 Interrupt generation circuit 9 to 12 Interrupt signal 17 Common bus 18 Interrupt control unit 19 Buffer memory 20 Bus interface

Claims (5)

[Claims] 1. A processor having a plurality of processors, a common bus to which the processors are connected, and an interface function between an external transmission path and the common bus, and delivering data received from the external transmission path to the processor. An interrupt control system in an information processing apparatus, comprising: an interrupt control unit that generates an interrupt signal for generating an interrupt signal, wherein the interrupt control unit stores interrupt factor information and interrupt destination information in association with each other in advance. And interrupt signal generating means for generating an interrupt signal to an interrupt destination processor indicated by interrupt destination information of the interrupt correspondence table corresponding to interrupt factor information added to the received data in advance. Control system. 2. A flag corresponding to the interrupt cause information is provided in the interrupt correspondence table, and a flag corresponding to the interrupt cause information is set in response to occurrence of an interrupt cause. The interrupt signal generating means is configured to generate an interrupt signal to an interrupt destination processor indicated by the interrupt destination information corresponding to the flag in response to the setting of the flag. 2. The interrupt control system according to 1. 3. The interrupt control means has a storage means for temporarily storing the received data, and the processor at the interrupt destination retrieves the data stored in the storage means via the common bus in response to the interrupt signal. 3. The interrupt control system according to claim 1, wherein the interrupt control system is configured to take an interrupt. 4. The interrupt signal generating means has a register corresponding to each of the processors, and is configured to set the interrupt signal in the register corresponding to the flag in response to the setting of the flag. The interrupt control system according to claim 1, wherein: 5. The interrupt control system according to claim 1, wherein the contents of the interrupt correspondence table are rewritable.