KR100498909B1 - Inter-processor communication redundancy device of exchange system - Google Patents

Abstract

end. The technical field to which the invention described in the claims belongs

Inter-processor communication redundancy device of switching system.

I. The technical problem that the invention is trying to solve

The present invention provides a device capable of minimizing message loss when switching paths when implementing dual processor communication in a switching system.

All. Summary of Solution of the Invention

An inter-processor communication duplication unit of the switching system, an operation path control unit for recording specific register values in a duplication variable when requesting a path switching, continuously polling the duplication variable, and assigning the specific values to an internal register when a specific value is detected; On the basis of the values, the preparation path controller for accessing the corresponding area of the receiving buffer to perform message processing, the operation path controller and the preparation path controller, respectively, are connected to each other through a redundant channel and receive the message when receiving the message. It consists of an operation path receiving buffer and a preparation path receiving buffer that writes not only the buffer but also the counterpart buffer.

la. Important uses of the invention

It is used for the communication redundancy device of the exchange system.

Description

Inter-processor communication redundancy device of exchange system

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exchange system, and more particularly, to an apparatus and a method capable of minimizing message loss during route switching during inter processor communication (IPC).

The path refers to each communication path when the processor-to-processor communication (IPC) is implemented in a redundant system. In other words, when the processor-to-processor communication is implemented in duplication, there are two paths for communicating between the processors. In addition, the redundancy refers to a device and a series of operating processes capable of transferring all elements used in an active path to a standby path during path switching. To do this, the memory needs to keep the data identical to each other through the redundant channel, and since the internal registers of the processor cannot use the redundant channel, the values are transferred to the counterpart processor using the redundant memory when switching.

Hereinafter, an interprocessor communication (IPC) redundancy apparatus in a conventional exchange system will be described with reference to FIG. 1. In this case, the processor-to-processor communication has a first path and a second path to implement redundancy. Since the configuration and operation for each path are the same, the following description will be given by way of example in the following description.

The main control part 111a controls the overall operation of the first path. The memory 115a is connected to the main controller 111a and stores various program data and temporary data generated during program execution. In this case, the memory 115a and the memory 115b are connected in a redundant channel to maintain the same data. The control unit 113a stores the IPC message continuously received through communication with the main control unit 111a in a corresponding region of the reception buffer 114a or transmits the stored IPC message through the fibus. The common memory 112a is in charge of communication between the main controller 111a and the controller 112a. The reception buffer 114a stores the IPC message received through the fibus.

In this case, since the memory 115a connected to the main controller 111a is duplicated with the counterpart memory 115b, the two memories always maintain the same data. However, since the reception buffer 114a connected to the control unit 113a does not have a redundant channel, the contents of the two buffers 114a and 114b are not the same. Therefore, a problem may occur that a message of a reception buffer in operation may be lost during path switching. This is because when the communication path is switched to the ready path due to a failure of the currently operating path, the receiving buffer of the waiting path is automatically initialized and used again from the beginning. In this case, since the path switching occurs before the messages received from the bus of the communicating path and stored in the receiving buffer are transferred to the main controller 111a, the messages stored in the receiving buffer 114a are substantially lost. Resulted.

Accordingly, an object of the present invention is to provide an inter-processor communication redundancy apparatus and method that can minimize message loss when switching paths when implementing inter-processor communication in a switching system.

Another object of the present invention is to receive the message received in the receiving buffer of the path in operation during the path switching as it can access (access) even in the preparation of the path, the control unit to determine the location of the message currently being processed correctly to continuously receive the receiving buffer It is an object of the present invention to provide an interprocessor communication redundancy apparatus and method.

That is, the inter-processor communication redundancy device of the switching system for achieving the above objects includes: an operation path controller for recording specific register values in a redundancy variable upon request of path switching; and continuously detecting the redundancy variable to detect the specific value. Substituting specific values into internal registers and accessing the corresponding area of the receiving buffer based on the values, the preparation path controller is connected to the operation path controller and the preparation path controller, respectively, and is connected to each other in a redundant channel. When the message is received, it is characterized in that it consists of an operation path receiving buffer and a preparation path receiving buffer for recording the message in the counterpart buffer as well as its own buffer.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, in adding the reference numerals to the components of each drawing, the same components have the same reference numerals as much as possible even if displayed on different drawings. In describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

2 is a diagram illustrating an interprocessor communication duplication apparatus according to an exemplary embodiment of the present invention. Here, the redundancy apparatus is divided into a first path and a second path, and since the configuration and operation of the first path and the second path are the same, only the first path will be described below. In addition, it is assumed that the first path is a currently operating path, and it is assumed that the second path is a ready path that is transferred when the path is switched.

Referring to FIG. 2, the controller (in this embodiment, the MC68360 chip is used) 221a stores an IPC message received through a P_BUS in a reception buffer or processes a message stored in the reception buffer to generate a PIBUS. To another processor. The control unit 211a includes many internal registers. For example, the control unit 211a may include a GSMR register for enabling and disabling continuous channel reception. In addition, the control unit 211a uses a buffer descriptor (BD) indicating a receive buffer, and a buffer called a receive buffer pointer (RBPTR) is used to determine which buffer technique to use when receiving. Here, if the control unit 211a shows the shape of the corresponding area of the reception buffer 213a using the reception buffer pointer, it is illustrated in FIG. 3. The memory 212a is connected to the control unit 211a and stores various program data and temporary data generated during program execution. In addition, the memory 212a is connected to the memory 212b in a redundant channel so that both memories maintain the same data at all times. The reception buffer 213a stores the IPC message received through the P_BUS. Here, the reception buffer 213a is also connected to the reception buffer 213b in a redundant channel so that the message received through the bus can be stored in the counterpart buffer as well as the own buffer. Here, the variable having the index value of the reception buffer currently being processed is called a reception buffer number (rx_ptr_num).

Hereinafter, an operation process according to an exemplary embodiment of the present invention will be described with reference to FIG. 2.

First, when an IPC message is received through a serial channel, the controller 211a writes the message in an area (receiving buffer) indicated by an internal register BD (buffer description), and generates an interrupt. At this time, the interrupt processing routine is performed, and the control unit 211a stores the index value of the buffer used in the reception buffer 213a in the variable reception buffer number rx_ptr_num and sets a flag corresponding to the buffer. Thereafter, the controller 213a processes the messages in which the flag is set while polling the reception buffer 213a. That is, the messages are delivered to a higher operating system (OS).

If a path change is required due to a cable failure during the above processing, the following process is performed.

First, when the transfer request is received, the operation path control unit 211a may duplicate basic registers (address registers, data registers, data registers, frame registers, frame registers, and stack registers). And specific values corresponding to the current situation in the variables.

In this case, since the preparation path control unit 211b continuously polls the redundancy variable, the operation path control unit 211a may receive specific values recorded in the redundancy variable. That is, the preparation path control unit 211b continuously polls the redundancy variable, receives specific values recorded by the operation path control unit 211a, and substitutes the values into the corresponding region of the internal register of the preparation path control unit 211b. Here, the preparation path controller 211b substitutes a value corresponding to the reception buffer number rx_ptr_num into the reception pointer register RXPTR register among the internal registers. In an actual implementation, the value of (rx_ptr_num * 8) is substituted. Message reception is enabled using the GSMR register among the internal registers of the controller 211b.

In this case, since the two reception buffers 213a and 213b are connected by a redundant channel, they store the same messages. Therefore, even if a path change is made, all the status data (specific register values described above) of the receiving buffer can be transferred from the active path to the ready path, and thus, the path cannot be transferred from the active path to the upper operating system (OS). The loss of messages can be prevented. That is, the control unit 211 in preparation for receiving the specific values for knowing the current status of the reception buffer from the active path can directly access the reception buffer of the ready path, which is connected to the redundant channel and stores the same message as the active path. have.

As described above, the present invention can access the message received in the receiving buffer of the path in operation when the path is changed in the interprocessor communication duplication apparatus, even in the path being prepared. Therefore, it is possible to prevent the loss of messages that occur when the receiving buffer is initialized and used again when switching paths.

1 shows an interprocessor communication (IPC) redundancy device of a switching system according to the prior art;

2 illustrates an interprocessor communication (IPC) redundancy device of an exchange system according to an embodiment of the present invention.

FIG. 3 is a view illustrating a shape in which a controller points to a corresponding area of a reception buffer using a pointer in the configuration of FIG. 2; FIG.

Claims (2)

In the communication redundancy device in the switching system, An operation path controller for recording values of specific registers into a redundancy variable when a path switching request is made; A preparation path controller for continuously polling the duplication variable and assigning the specific values to an internal register when detecting a specific value, and accessing a corresponding region of a reception buffer based on the values to perform message processing; And an operation path receiving buffer and a preparation path receiving buffer, which are connected to the operation path control unit and the preparation path control unit, respectively, and are connected to each other through a redundant channel to record the message in the counterpart buffer as well as the own buffer when the message is received. Interprocessor communication redundancy device. The method of claim 1, wherein the specific registers, An interprocessor communication redundancy device comprising an address register, a data register, a frame register, a stack register, and the like.