JPH04260962A - Synchronization control system in parallel computers - Google Patents

Abstract

PURPOSE:To immediately execute proper processing even when an error is generated in a parallel computer (PE) and to rapidly attain synchronism between plural PEs by detecting all status at the time of forming the synchronism of all PEs in respect to a synchronism/status/stable state detecting method in a system for connecting many PEs through a network and synchronizing them. CONSTITUTION:This synchronism control system is provided with plural status request register means 2 prepared in individual PEs so as to independently output status requests and store the request signals, a status deciding means 4 for deciding the existence of requests from all PE status request registers, a status distributing means 5 for distributing status based upon the decided result, and a status detecting register means 3 for detecting the status based upon the distributed decision result and the output of a synchronism detecting register means 1 and constituted of detecting the status of all the PEs when the synchronism of all the PEs is established.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to an inter-processor synchronization system for parallel computers in which a large number of independently operating computers (hereinafter abbreviated as PE (processor element)) are connected through a communication network and operated in parallel in synchronization with each other. , relates to synchronization, status and stable state detection schemes.

0002

[Background Art] Advances in semiconductor technology have made it possible to construct high-performance microprocessors and large-capacity memories at low cost and in a small size.It is now possible to easily construct parallel computers using large numbers of such microprocessors and memories. It has become possible to create In order to process one task in parallel by multiple PEs, it is sufficient to divide the task and assign it to each PE for execution. When performing this parallel processing in parallel, it is necessary to pay attention to the order of processing. That is,
It may be necessary to ensure that the next process is performed only after all PEs have finished one process. To ensure this, an efficient inter-processor synchronization function is required. This makes it possible to realize a high-speed parallel computer.

A first method for parallel computers is a shared memory method. This method has a memory shared by all PEs, and achieves an inter-processor synchronization function by exclusively reading and writing to a part of the memory.

A second method for parallel computers is the synchronous register method. In this method, a synchronization register is provided for each PE, and the logical product of the outputs of the synchronization registers of all PEs is detected and returned to all PEs, thereby detecting synchronization among all PEs.

A third method for parallel computers is a state detection method. As shown in FIG. 21, in the PEs of the parallel computer system, first, Process 1 is executed within each PE, and after that is completed, messages are sent/received between other PEs as Process 2. When the processing of that message is completed, the process moves to the next one. The host processor learns that all PEs are waiting for a message, and each PE
, and each PE starts processing the corresponding command. In this way, each PE knows its status and moves to the next step.

[0006]

[Problem to be solved by the invention] The shared memory method has
As the number of PEs increases, there is a drawback that memory accesses occur more frequently.

[0007] In the synchronous register method, the synchronous register can be accessed independently for each PE, so that no memory access conflict occurs. The synchronization mechanism of this method is shown in Figure 22.
There is no problem when all PEs are working in the same way without any abnormality in process 1 as in (a). The synchronization register may detect that all PEs have completed processing 1 and synchronization has been established, and then proceed to processing 2. If some kind of abnormality (for example, a program bug, division by 0, overflow, etc.) occurs in one PE in process 1, conventionally there are only two ways to deal with it. There are two methods, as shown in FIG. 22(b), in which an error in processing 1 of one PE is ignored and synchronization is detected in all other synchronization registers, and processing 2 is continued; In this method, when an error is detected in Process 1 of one PE, Process 1 of all PEs is interrupted. in this case,
The former method has the problem that PEs other than those that caused the error in Process 1 continue Process 2 without noticing the error at all, resulting in delayed discovery of the error and wasteful execution of the process. Furthermore, there is a possibility that you may not notice the error until the end and give the wrong answer. In addition, in the latter method, since error information is not transmitted to any PE other than the PE that caused the error in process 1, all PEs other than the PE that caused the error enter a synchronization wait and receive the synchronization signal from the PE that caused the error. Therefore, there is a problem in that the synchronization processing of all PEs is not completed and therefore the process does not proceed to process 2.

Additionally, conventional systems have insufficient ability to detect synchronization or status requests when messages still remain on the network. In other words, if a synchronization request or status request is issued while the message is not present in each PE or remains in the communication path between PEs, the process will move to the next step.
There is a problem in that when a PE that has data remaining in the network to be processed in the previous process is reached, the data is processed in the next step. In other words, when all PEs are in synchronization, only one PE can communicate with other PEs.
There was a possibility that E would know that synchronization was established earlier than E and move on to the next step.

In the parallel computer system of the present invention, by synchronizing all PEs and detecting the status of all PEs at the same time, even if an error occurs in one PE, appropriate measures can be taken immediately so that other PEs can Since it is possible to prevent the execution of incorrect processing or to be placed in a synchronization wait state, the purpose is to achieve inter-processor synchronization at high speed as a result and improve calculation speed.

[0010] Furthermore, in the parallel computer system of the present invention, each PE accurately knows once a stable state has been reached;
In particular, even if all PEs are in the message waiting state, if a message exists in the network, it is not a stable state (the message will eventually arrive at the PE, and that PE will no longer be in the message waiting state). The purpose is to detect a stable state between processors with respect to the synchronization request status by detecting the absence of messages in the synchronization request status.

[0011]

[Means for Solving the Problems] FIG. 1 is a block diagram showing the principle of the first invention. The present invention is a method based on a synchronous register method. In other words, it is a distributed memory type parallel computer having a configuration in which a large number of independently operating computers are connected, and each PE has a synchronization request register and a synchronization detection register, and means for calculating the AND of the synchronization request registers of all PEs, and A parallel computer synchronization method is assumed, which has means for distributing results to all PEs, and synchronization detection means 1 for detecting synchronization of all PEs based on the distributed results.

[0012] The status request register 2 is
For example, when the status is normal, the P
A logic 1 is input from the CPU of E. Next, the determining means 4
Determine that the status of all PEs is normal.

The distribution means 5 distributes the output of the determination means 4 to all PEs. The status of all PEs is normal and all P
When the synchronization detection means 1 of E detects that the synchronization of all PEs has been established, the contents of the status detection register 3 are changed.

When the status detection register 3 detects that the status of all PEs is normal, the process proceeds to the next step. FIG. 2 is a diagram showing the principle of the second invention, which relates to a distributed memory type parallel computer in which a large number of independently operating computers are connected through a communication network, and each PE has a synchronization request register, a synchronization detection register, It has means for taking a logical product of the synchronization request registers of all PEs, means for distributing the result to all PEs, and means 6 for issuing a synchronization request for its own PE and detecting the establishment of synchronization for all PEs. In the second invention, instead of this, there is provided a means 7 for receiving a status signal of the communication network, and further, a signal line for receiving the status signal and an output of a synchronization request register indicate that a synchronization request is present on the own PE. , and synchronization stability request means 8 for detecting that there is no message on the network.

Furthermore, FIG. 3 is a diagram showing the principle of the third invention, which is related to a distributed memory type parallel computer in which a large number of independently operating computers are connected through a communication network.
Each E consists of means for logically multiplying the status request register and status detection register of all PEs with the status request registers of all PEs, and means for distributing the result to all PEs, requesting the status of its own PE and checking the status of all PEs. It has means 9 for detecting the establishment of a request. In the third invention, instead of this, there is provided means 10 for receiving a status signal of the communication network, and further, a signal line for receiving the status signal and an output of a status request register indicate that a status request has been made on the own PE. , and status stability request means 11 for detecting that there is no message on the network.

[0016]

[Operation] In the first invention, in a certain process 1, synchronization of all PEs is established as shown in block 1, and only when it is established in block 4 that the status of all PEs is normal, each PE The system outputs a signal indicating that the status is normal, then clears the status and proceeds to the next process 2. Therefore, if there is an error in process 1, the process does not proceed to process 2 even if synchronization of all PEs is established in process 1, for example. And processing 1
In this case, it is possible to immediately determine that an error has occurred. Since appropriate processing can be performed for the error, it is possible to prevent each PE from performing an incorrect operation or being placed in the same expected state due to an error in one PE.

[0017] The second invention detects a stable state by observing the state of the network. A stable state defined in this invention means that there are no messages on the communication path, and all PEs
There are no messages in PE, and all PEs are waiting for messages. In order for all PEs to be in the message waiting state, each PE must output a synchronization request in the form of an AND with a signal indicating that there is no message on the network, and all other PEs must also communicate with each PE. All they have to do is to know that they are issuing the same synchronization request, that is, to perform synchronization detection. That is, the present invention adds the condition that there are no messages on the network in addition to the conventional synchronization detection. Here, no messages in the network means that each PE has no messages, and each PE
It also says that it is not on the communication path that connects.

The presence of a message on the network means that at least one PE has the message, or all PEs have no message, and all PEs are waiting for a message, but the message is not on the communication path. This is true. The message will eventually reach some PE, and that PE will no longer be in a message waiting state and will be in an unstable state. In other words, even if each PE finishes processing and outputs a synchronization request, if the message remains on the network, the message will someday enter some PE and that PE will execute the message processing again. This is contrary to the fact that the synchronization request was output. Therefore, in the present invention, the synchronization stabilization request is output after detecting that there is no message on the network by checking the network status. This makes it possible to avoid a situation in which the PE must process a message again after outputting the synchronization stability request, which is contrary to the synchronization stability request.

Furthermore, in the third invention, the network state is also detected when detecting the status.

[0020]

Embodiment First, a specific example of a parallel computer system to which the present invention is applied will be described. A parallel computer system to which the present invention is applied is a distributed memory highly parallel computer. 64 to 1024 processor elements (
It consists of a cell) and an engineering workstation (EWS), which is a host computer. Communication between cells and hosts and between cells is carried out using two types of networks: a command bus that connects all cells and hosts, and a torus network that connects cells to each other.

[0021] A single cell is a 32-bit reduced
Instruction Set Computer
(RISC) type microprocessor and high-speed floating point arithmetic unit provide high calculation performance, and high-performance DMA controller provides high-speed and high-performance data communication capability. Special processing hardware (optional) corresponding to the application can be added to each cell, and it can be customized into a dedicated parallel machine suitable for various applications.

FIG. 4 shows the basic system configuration of a parallel computer system to which the present invention is applied. The parallel computer system to which the present invention is applied is a distributed multi-instruction multi-data (MIMD) highly parallel processor. Each processor element is called a cell and has the same configuration. Each cell is comprised of a high-performance 32-bit microprocessor, high-speed FPU, cache memory, large-capacity main memory, network interface, and command bus interface.

[0023] The cells are connected to four adjacent cells by a torus network having a two-dimensional torus topology. In addition, all cells and the host computer are connected by a command bus. Also, each cell has
Optional hardware such as an image input/output device, high-speed I/O interface, disk interface, expansion memory, vector processor, etc. can be added externally.

FIG. 5 shows the hardware configuration of each cell processor in the parallel computer system to which the present invention is applied. The basic unit consists of a RISC microprocessor IU that performs integer operations, logical operations, and control, and a high-speed floating arithmetic unit FPU, and is connected to a high-speed cache memory CM. The cache memory has a capacity of 128KB and uses a copy bag method to achieve a high hit rate and low memory bus traffic.

The message controller MSC has a high-performance DMA controller and a cache controller inside, and realizes high-speed disk transfer. The DRAM controller is a 4Mbit or 1Mbit DRAM
control and detect and correct errors. The command bus interface BIF performs disk transfer with the command bus, and the routing controller RTC performs disk transfer with the torus network.

[0026] MSC, DRAMC, RTC, BIF are:
It is connected to an internal bus called LBUS. LBUS is a 32-bit wide address/data multiplexed bus. The LBUS is taken out to the outside via a connector for each cell, making it possible to add various optional hardware.

After the power is turned on, the system is initialized from the host computer. System initialization is to check the functions and initialize the various resources that this system has. System initialization is performed via the command bus.
This is done by loading the initialization program broadcast from the host and running it. At this time, the cell ID of each cell is also set.

In the initialized cell of this system,
A cell OS (OS that runs a cell consisting of a CPU) is running and waiting for a request to load and execute a user program. User programs are also broadcast to each cell via the command bus. The user program placed in the cell is executed according to instructions from the host.

When it is desired to set initialization data in a cell, it is done by broadcasting the initialization data from the host computer through the command bus. Broadcasting using the command bus can be performed not only from a host to a cell, but also from one cell to another group of cells. Furthermore, it is also possible to broadcast to only those cells whose group IDs match by grouping arbitrary cells.

The torus network has a configuration in which routing units RTC are connected in a torus-shaped network as shown in FIG. The four ports of RTC are
It is called east-west-south-north (EWSN), and between each cell there are N, S, and W.
and E are connected respectively. Each RTC data transfer path consists of 16-bit wide data and control signals. RTC performs relay processing in communication between arbitrary cells at high speed using hardware without the intervention of the CPU of each cell. The maximum configuration is 32×32 (1024 units).

The routing unit RTC has a configuration as shown in FIG. Routing first proceeds in the X direction,
Next, proceed in the Y direction. When the sending cell and receiving cell are the same,
Since the same route is always used (static routing), overtaking of messages does not occur. Inside the RTC, a routing unit in the N-S direction and a routing unit in the W-E direction exist independently and are connected in series.

[0032]Each routing unit performs data destination determination and buffering. In order to reduce the latency of data transfer, it uses a routing method called wormhole routing. In addition, a buffer management algorithm called a structured buffer pool is used to prevent deadlock and throughput degradation even if multiple cells issue transmission requests at the same time.

Wormhole routing is a routing method in which a message header is directly sent out from an input channel to an output channel while creating a relay route. Each relay node buffers a portion of the message.

As shown in FIG. 8, in normal store-and-forward routing, the relay node buffers the entire message, whereas in wormhole routing, only a few words of data called a flit are sent to the relay node. Buffered. When a cell receives the head of a message, it selects a relay route channel and transfers the flit to that channel. Subsequent flits are transferred to the same route selected by the header flit.

By employing wormhole routing, the delay time (latency) from message transmission to reception can be reduced. The latency of store-and-forward routing is proportional to the product of inter-cell distance and message size, whereas the latency of wormhole routing is proportional to the sum of inter-cell distance and message size.

On the other hand, while one message is being transferred, the channel being used by that message is blocked, which may cause deadlock and decrease throughput. RTC has achieved low latency, high throughput, and deadlock-free performance by incorporating a structured buffer pool algorithm into wormhole routing, which is characterized by low latency. This prevents the performance of the entire network from deteriorating due to congestion in a portion of the network when communication is being performed across the entire network. Further, as long as the transmitted message is always received by the destination cell, deadlock will not occur on the network.

The data handled by the RTC is in the format shown in FIG. 9 and consists of a header indicating the beginning of the message, a message body, and an end bit indicating the end of the message. The header carries various control information. The end bit is
The message controller automatically adds it.

Now, in such a system, the synchronization function according to the present invention will be described below. In parallel processing, it is essential to have a mechanism that can guarantee that the processing of all cells is completed before proceeding to the next processing. The synchronization/status system is hardware that efficiently performs synchronization processing.

In FIG. 10, each cell issues a synchronization request after completing its own process 1. Each cell waits for synchronization until it is confirmed that all cells have issued a synchronization request. Establishment of synchronization is notified by the hardware, and then execution of process 2 is started. In other words, in a highly parallel computer such as the system of the present invention, processing often occurs in which the processor waits for all processors to reach a certain state before proceeding to the next state.
The synchronization/status system efficiently realizes this type of synchronization.

The basic operation of the synchronization/status system is as follows. In the synchronous system, each cell has a synchronization request register, and when the logical product (AND) of the outputs of all cells becomes 1, the synchronization detection register is set. At this time, the synchronization request register is also cleared. Since the synchronization detection register being set indicates that all cells have requested synchronization, this can be used to ensure that all cells have reached the part being programmed.

In the status system, each cell has a status request register, and the AND (AN) of the outputs of all cells is performed.
D) is set in the status detection register. The status detection register represents the momentary value of the AND of the status request registers of all cells.

The synchronization/status system of this system has a hierarchical network configuration as shown in FIG. 11 in order to AND the outputs of the registers of a maximum of 1024 cells. In addition, time-sharing operations are performed for each factor so that operations can be performed on multiple factors in parallel. The synchronization/status network is capable of processing 8-factor high-speed synchronization, 8-factor high-speed status, 32-factor slow synchronization, and 32-factor low-speed status by using a time-sharing hierarchical network. Synchronization and status registers are mounted within the BIF chip.

The synchronous system includes resources such as a synchronous request register, a synchronous detection register, a synchronous mask register, and a synchronous interrupt mask register. Each high-speed synchronous system has 8
The low-speed synchronous system is a 32-bit register.

A synchronization request is made by the CPU by setting a synchronization request register. When synchronization is established, the corresponding bit in the synchronization detection register is set and the synchronization request register is reset. The CPU can know whether synchronization has been established by monitoring the synchronization detection register. When synchronization is established, if the corresponding synchronization interrupt mask register is not set, an interrupt is generated in the CPU, so notification can be made using this. Also, if the synchronization mask register is set, that cell will not participate in synchronization. In other words, I do not detect the synchronization,
For other cells, the cell is always in a synchronization request state. Using the mask function, it becomes easy to synchronize only a specific group of cells.

[0045] The status system includes status registers,
There are resources for status detection register and status mask register. The high-speed status system is an 8-bit register, and the low-speed status system is a 32-bit register.

A status request is made by the CPU by setting a status request register. The AND of the values of the status request registers of all cells is set in the status detection register. That is, the value of the status detection register represents the status of all cells at that time. Setting the status mask register causes that cell to not participate in status. For other cells, the status is always requested. By using the mask function, it becomes easy to determine the status of only a specific group of cells.

[0047] Synchronization & status is a function for obtaining the status of each cell at the time when synchronization is established. Sync &
By setting the status mode register, the synchronization system and status system are combined to perform synchronization and status operations. A set of synchronization & status modes is possible for each factor. In sync & status mode, the behavior of the synchronization system remains the same, but the behavior of the status system changes. In the normal mode, the AND of the statuses of all cells is always set in the status detection register. In synchronization & status mode, the status of all cells is set only at the moment synchronization is detected.

FIG. 12 shows how to use synchronization & status. When the CPU of each cell reaches the synchronization request point, it first sets the status request register if the processing up to that point has been executed normally. If there is any error, clear the status request register. Thereafter, the CPU sets the synchronization request register and waits for a synchronization request. When the CPU, which has been waiting for the completion of synchronization, detects the completion of synchronization, it reads the value of the status detection register, confirms that all cells have executed the previous process without error, and then proceeds to the next step. If an error has occurred in one or more cells, the value of the status detection register becomes 0 and all cells complete the process.

With synchronization and status, if some error occurs during processing, the cell can check the overall processing status when synchronization is detected. Since all cells can detect and judge abnormal processing in any one cell and take appropriate processing, cells that have completed normally will not continue to wait for synchronization.

FIG. 13 shows an embodiment of the implementation of the present invention. First, the procedure for detecting synchronization will be described. CPU of each PE (
(see FIG. 14) sets the synchronization request register 21 and waits for synchronization detection. The output of the synchronization request register 21 is logically multiplied by an AND circuit 24 in all PEs, and is returned to all PEs. When all PEs set the synchronization request register 21, the AND output becomes 1, setting the synchronization detection register 23 of all PEs, and simultaneously setting the synchronization request register 21.
Clear.

[0051] The CPU of each PE can know that synchronization has been established by monitoring the synchronization detection register 23 in a dynamic loop or by receiving an interrupt triggered by the synchronization request register 23 being set. The CPU that detects synchronization proceeds to the next step.

In the present invention, in order to obtain status information in addition to synchronization, the following procedure is performed. In FIG. 13, MODE of the output of the mode register 28 is assumed to be 0. Each P
When the CPU E reaches the synchronization request point, it first sets the status in the status request register 31 if the processing up to that point has been executed normally. For example, if there is an error, clear the status. Thereafter, the synchronization request register 21 is set and the process waits for a synchronization request. The output of the synchronization request register 21 and the output of the status request register 31 are ANDed by AND circuits 24 and 34 in all PEs, respectively, and returned to all PEs. When all PEs set the synchronization request register 21, the AND output is 1.
Then, the synchronization detection registers 23 of all PEs are set. AND circuit 2 that simultaneously clears the synchronization request register 21
4 “1” output is the OR circuit 37 on the status line 36,
The signal is sent to the status detection register 33 via the AND circuit 38. When there is no abnormality in the status of all PEs and the output of the status request register 31 is logic 1, the AND circuit 34 outputs logic 1, and this output is distributed again to all PEs. Then, in each PE, the status line 36
The AND circuit 38 performs a logical product of the signal indicating the establishment of synchronization of all the PEs sent via the AND circuit 43 and the signal indicating the establishment of the status request of all the PEs sent from the AND circuit 43. Set 33.

The CPU, which has been waiting for the completion of synchronization, reads the value of the status detection register 33, and after confirming that all PEs have executed the previous process without error, proceeds to the next step. If an error has occurred in one or more PEs, the output of the AND circuit 34 becomes logic 0, and even if all PEs are synchronized, the value of the status detection register 33 is changed to 0 via the AND circuit 39. Therefore, all PEs do not execute the following process. The data on the status line 36 is
Since it becomes valid only when synchronization is detected and updates the status detection register 33, it is guaranteed to detect the status of all PEs when synchronization is established.

By controlling MODE with another mode register 28 which can be read and written by the CPU, the synchronization system and status system can be used independently or can be used as a synchronization and status system. In other words, when MODE output from the mode register 28 is 1, even if the signal on the status line 36 is 0 and all PEs are not synchronized, if there is no abnormality in the status of all PEs, the status detection register 33 can be set to 1. Therefore, the status system can be operated independently regardless of the synchronization system.

FIG. 14 shows the configuration of a PE constructed according to the embodiment of the present invention shown in FIG. 13, and the overall configuration of a parallel computer system. The same parts as those in FIG. 13 are given the same reference numerals and the explanation will be omitted.

One PE includes the CPU 41 and the storage device ME.
A synchronization request register 21, a synchronization detection register 23, a status request register 31, a status detection register 33, a mode register 28, and a counter 51 are connected to M42 via a data bus line. The data bus is connected to a network 44 via an inter-PE communication interface 43, and communication with other PEs is performed. The synchronization request register 21 and status request register 31 of each PE are AN
connected to D circuits 24 and 34, and this AND circuit 24
, 34 are distributed to the synchronization detection register 23 and status detection register 33 of each PE, respectively.

[0057] For parallel computers, synchronization waiting time is wasted time, so it is desirable to shorten it as much as possible. When executing a program, it is important to know which PE has a long synchronization wait time. In the embodiment shown in FIG. 15, a counter 51 for counting clocks is provided for each PE, and the counter 51 counts up when the output of the synchronization request register 21 (before performing the AND operation on all PEs) is 1, and detects synchronization. When this happens, the count ends. When synchronization requests and synchronization detections are repeated, the time required for synchronization is accumulated.

The user first clears the counter 51, executes the program, and finally reads the value of the counter. This allows you to know the synchronization overhead of the program. This type of function can also be achieved with software, but when executed using software, the program execution time changes depending on whether it is measuring or not, making it impossible to measure accurate time and causing unexpected problems. It may also cause bugs.

[0059] If any error occurs during processing, all PEs need to confirm that the error has occurred at the same time as synchronization is detected. For example, as shown in FIG. 16, according to this embodiment, processing 1 ends in 1PE,
After synchronization is established, normal termination can be detected and determined for all PEs, and if an abnormality occurs, appropriate abnormality processing can be taken, so that PEs that have terminated normally do not continue to wait for synchronization. If the process ends normally, the process proceeds to process 2.

In FIG. 16, instead of determining whether the processing has ended normally, it may be determined whether the arithmetic processing in each PE has converged within a predetermined error range, and when convergence occurs, the process may proceed to the next process 2. . In this case, the status of the status request register 31 may be set when the convergence occurs in FIG. 13.

FIG. 17 shows another embodiment of the present invention. The stable state of all PEs is detected by the following process. The network status signal 60 is a signal that indicates the presence of a message on the network when it is 1, and the output of the inverting circuit 61 is a signal that becomes 1 when there is no message on the network. That is, since the network status signal 60 is a signal line from the network and becomes 1 when a message exists in the network, at least one of all PEs
When one network status signal line is 1, it indicates that there is a message in the network.

FIG. 18 shows a method for detecting the network state. First, it is determined whether there is a message in its own PE, and if there is a message in its own PE, it continues to indicate that there is a message in the network. This judgment is
This is done by detecting whether there is data in a predetermined register of the own PE. When there is no message in the own PE, it is determined whether a predetermined period of time has elapsed. This predetermined time corresponds to the data propagation time to the other PE. When a predetermined period of time has elapsed, it indicates that there is no message on the network; that is, there is no message in the own PE, and the fact that the predetermined time has elapsed means that there is no message in both the communication path between the own PE and the other PE. In other words, there are no messages on the network.

In FIG. 17, the synchronization request register 62 is set when the synchronization request signal 63 is 1, and the synchronization request register 62 is set when the processing step of the PE is completed and a synchronization request is sent to another PE. emits. The message reception signal 64 is a signal line indicating that a message has arrived from the network to the own PE. When this signal is 1, the output of the OR circuit 65 is 1, so the synchronization request register 62 is cleared. For example, if one PE issues a synchronization request signal thinking that it has finished processing, and a message arrives later than that PE, the synchronization request register 62 is cleared by receiving this message,
Correct the error in the synchronization request 63 from the PE. Also,
The synchronization request register 62 is also cleared by the AND circuit 68, but this is because after the AND circuit 68 sets the synchronization detection register 69, the synchronization request register 62 in that processing step is reset and the own PE is cleared in the next processing. This is to wait for the synchronization request signal 63 from.

When the CPU has no more messages to process in the PE, it sets the synchronization request register 62, outputs a synchronization request, and waits for a stable state. When a message arrives from this PE, the signal line of the message reception signal 64 becomes 1.
First, the synchronization request register 62 is cleared by the signal line 1. Note that if the CPU clears the synchronization request register 62, it must clear the synchronization request register 62 before receiving the next entire message from the network. When the CPU finishes processing the message, it sets the synchronization request register 62 again.

An AND circuit 66 performs a logical product of the output of the synchronization request register 62, the inversion of the network status signal 60, and the outputs of the message transmission management unit 71 and message reception management unit 72 (see explanation in FIG. 19). Te, AN
A synchronization stability request signal is output from the D circuit 66, and the AND circuit 67 performs a logical product of the synchronization stability request signals from each PE in all PEs, and returns the signal to all PEs. When a message exists in the network, even if a synchronization request from each PE is output from the synchronization request register 62, the output of the inverting circuit 61 is 0, so the AND circuit 66
The output of is 0, and no synchronization stability request signal is output. Therefore, when the network state of at least one PE is 1, the entire logical product output (AND circuit 6
7) does not become 1.

When the synchronization request register 62 of all PEs is set and there is no message in the network, the AN
A synchronization stability request signal is output from the D circuit 66, and the overall AND output becomes 1, and all PEs are output via the AND circuit 68.
The synchronization detection register 69 is set, and the synchronization request register 62 is cleared at the same time. AND circuit 68 includes AND
The output of the circuit 66, which indicates that there is no message on the network and that the PE itself is requesting synchronization, is input, and the output of the AND circuit 67, which indicates that all PEs have requested synchronization stability, is input. The signal that is displayed is also input. This AND circuit 68 confirms that the synchronization stability request signal is reliably output.

Since the synchronization detection register 69 generates an output on the condition that there is no message on the network,
The stable state of all PEs can be known by monitoring the output of the synchronization detection register 69. In the present invention, some PEs do not know the stable state earlier than others and move on to the next step and send a message, but all PEs only after the synchronization detection register 69 detects that the stable state has been established. You can move on to the next step.

FIG. 19 shows a circuit configuration of another embodiment of the present invention, in which the state of the network is taken into consideration when detecting the status of each PE. The stable state of all PEs is detected by the following process.

The network status 70 is a signal line from the network, and when a message exists in the network, at least one signal line of each PE indicates that there is a message in the network. Note that this signal becomes 1 when there is no message on the network.

The message transmission management unit 71 (located in each PE) indicates that there is no message to be transmitted. The message reception management unit 72 (located in each PE) indicates that no message has been received. When receiving a message, the CPU of each PE receives the message from this message reception management section.

[0071] The network state 70 is as follows in each PE:
Message transmission management section 71, message reception management section 72
This signal indicates whether there are any other messages. Message reception 73 is a signal line indicating that a message has arrived from the network to the PE. This signal clears the status request register 75 that was set by the status request 74.

When the CPU has no more messages to process in the PE, it sets the status request register 75 and
Wait until it becomes stable. When a message arrives at this PE, the message reception signal line becomes 1 and the status request register 75 is cleared. When the CPU finishes processing the message, it sets the status request register again.

The output of the logical product of the status request register 75, the network status 70, and the outputs of the message transmission management unit 71 and message reception management unit 72 is obtained by an AND circuit 76, and the AND circuit 77 is an AND circuit for all PEs.
It is taken and returned to all PEs. When a message exists in the network, at least one network state is 0, so the overall AND output will not be 1.

When the status request registers 75 of all PEs are set and there is no message in the network, the overall AND output becomes 1, and the status detection registers 78 of all PEs are set via the AND circuit 79. As each PE receives messages from the network,
When transitioning from the message waiting state to the message processing state (each PE is not in a stable state), the CPU does not clear the status request register 75, but the status request register 75
, the status request register 75 must be cleared before receiving the entire message from the network.

All PEs can know the stable state by monitoring the status detection register 78. Even if one PE learns of the stable state earlier than the others, moves to the next step, and sends a message, the other PEs can detect from the status detection register 78 that the stable state has been established, so they cannot proceed to the next step. can be migrated.

FIG. 20 is a circuit diagram of still another embodiment of the present invention. Components that are the same as those in FIGS. 17 and 19 are given the same reference numerals, and their explanations will be omitted. In this example, FIG.
In the synchronous status method that detects the status after detecting the establishment of synchronization as shown in 3, the presence or absence of a synchronization request,
The network status is also detected when determining the presence or absence of a status request.

[0077]

[Effects of the Invention] According to the first invention, even if all PEs are synchronized, the status of one PE's abnormality processing etc. can be updated to all PEs.
Since it is possible to detect and judge and perform appropriate processing, it is possible to improve the calculation processing time in a parallel computer system.

Furthermore, by providing a mode register as a synchronization/status mode control register, synchronization/status mode control registers are provided.
Both status independent mode and synchronization/status mode can be realized, expanding the scope of application of synchronization/status hardware.

Furthermore, by providing a synchronization wait time integration counter, it is possible to know how the loads of a plurality of PEs are distributed without changing the operation of the PEs. In the second invention, the stable state of all PEs including the network state can be detected by incorporating the network state into the synchronization detection circuit.

Furthermore, when each PE moves from the message waiting state to the message processing state (each PE is not in a stable state) by receiving a message from the network, C
A stable state can be detected quickly and safely by clearing the synchronization request register using the message reception signal line instead of the PU clearing the synchronization request register.

In the third invention, by incorporating the network state into the status detection circuit, the stable state of all PEs including the network state can be detected. In addition, in the present invention, the status request register is directly reset by message reception, so when a message is received, the status request register is reset more easily than when the status request register is set by a status request from the CPU.
A status request can be output from the status request register faster.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle of the first invention.

FIG. 2 is a block diagram showing the principle of the second invention.

FIG. 3 is a block diagram showing the principle of the third invention.

FIG. 4 is a hardware configuration diagram of a parallel computer system to which the present invention is applied.

FIG. 5 is a diagram showing the configuration of a cell.

FIG. 6 is a configuration diagram of a torus network.

FIG. 7 is a configuration diagram of RTC.

FIG. 8 is a diagram showing wormholes and store and forward routing.

FIG. 9 is a diagram illustrating RTC messages.

FIG. 10 is a diagram illustrating synchronization processing.

FIG. 11 is a diagram showing the configuration of a synchronization and status system.

FIG. 12 is a diagram illustrating an example of how synchronization and status processing is used.

FIG. 13 is a configuration diagram of a synchronization & status circuit according to the first embodiment.

FIG. 14 is a diagram showing the configuration of a PE and the overall configuration of a parallel computer system in the first embodiment.

FIG. 15 is a diagram showing a synchronization waiting time counter in the first embodiment.

FIG. 16 is a diagram showing synchronization and status processing according to the first embodiment.

FIG. 17 is a block diagram of a second embodiment.

FIG. 18 is a flowchart of network state detection in the second embodiment.

FIG. 19 is a block diagram of a third embodiment.

FIG. 20 is a block diagram of a fourth embodiment.

FIG. 21 is a flowchart of conventional stable state detection.

FIG. 22 is a diagram showing conventional PE processing and synchronization.

[Explanation of symbols]

Claims (14)

[Claims] 1. A distributed memory parallel computer having a configuration in which a plurality of independently operating PEs are connected, wherein each PE independently makes a synchronization request and a synchronization request register means for holding a synchronization request signal; synchronization determination means for determining that there is a request from the synchronization request register of status request register means (provided in the PE for independently making a status request and holding a status request signal);
2), a status determining means (4) for determining whether there is a request from the status request register of all PEs, a status distributing means (5) for distributing the determination result to all PEs, and a status distributing means (5) for distributing the determination result to all PEs. By having status detection register means (3) that performs status detection based on the distributed judgment results and the output of the synchronization detection register means (1), all PEs can be detected when synchronization is established among all PEs.
An inter-processor synchronous control method characterized by being able to detect the status of. [Claim 2] According to claim 1, by having a mode register for controlling connection/disconnection between the synchronous system and the status system, the system can operate as a synchronous and status system or switch between the synchronous system and the status system as independent systems. An inter-processor synchronous control method characterized by: 3. In the parallel computer synchronization method according to claim 1, each PE has a counter for counting clocks, and the time from when synchronization is requested to when synchronization is detected is accumulated for each PE, and the program A synchronization time measurement method characterized by being able to measure synchronization overhead time for each PE without affecting processing time. 4. An inter-processor synchronous control system in which the status detection register according to claim 1 detects the occurrence of an error in each PE. 5. An inter-processor synchronization control method according to claim 1, wherein the status detection register detects convergence of calculation values in each PE. 6. In a distributed memory parallel computer in which a plurality of PEs operate independently, means for detecting the establishment of synchronization among all PEs, and status request distribution means for distributing the status of each PE to all other PEs; A processor in a parallel computer, comprising: status detection means for detecting that the status of all PEs has reached a predetermined status and synchronization has been established among all PEs; and an output of the status detection means that causes all PEs to proceed to the next step. Inter-synchronous control method. 7. In a distributed memory parallel computer in which a large number of independently operating computers are connected via a communication network, each PE independently makes a synchronization request and a synchronization request register means for holding a synchronization request signal; Means for logically ANDing the outputs from the synchronization request registers and the result for all P
synchronization detection register means (6) for performing synchronization detection based on the distributed results; means (7) for receiving a communication network status signal; and an output of the synchronization request register and the status signal. Synchronization stability request detection means (8
) for detecting that there is no message on the network and that all PEs are in a message waiting state. 8. The parallel computer according to claim 7, further comprising means for indicating that a message has arrived at the PE from the communication network, and a circuit for clearing a synchronization request register by a signal indicating the arrival. Steady state detection method. 9. The synchronization stability request detection means (8) comprises:
8. The stable state detection method for a parallel computer according to claim 7, further comprising means for calculating an AND of a signal on a signal line indicating a network state and an output of a synchronization request register. 10. The synchronization detection register is set by performing a logical product between the output of the synchronization stability request detection means (8) and the fact that all PEs are requesting synchronization stability. Stable state detection method for parallel computers. 11. A claim characterized in that the method has means for indicating that there is no message from the message transmission management section and the reception management section, and performs a logical product between a signal line indicating the state and the output of the synchronization request register. 7. The stable state detection method described in 7. 12. In a distributed memory parallel computer in which a large number of independently operating computers are connected through a communication network, means for performing a logical product of a status request register indicating the status of each PE and the request register with the status of all PEs. and a means for distributing the result to all PEs, a status detection register means (9) for detecting the status based on the distributed result, and a means (10) for indicating the state of the communication network. A stable state detection method characterized in that it is possible to detect that there is no message on the network and that all PEs are in a message waiting state by taking a logical product between the output and a signal indicating the state of the network. Claim 13: By having means for indicating that a message has arrived at a PE from a communication network, and adding a circuit that clears a status request register using a signal indicating the arrival, the stable state of all PEs can be safely checked. 13. The stable state detection method according to claim 12, wherein the stable state detection method is capable of detecting. 14. A means for indicating that there is a message from the message transmission management unit and reception management unit, and performing a logical product of a signal line indicating the status, an output of the status request register, and an output indicating the network status. 13. The stable state detection method according to claim 12.