JP2010134698A - Information processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processing system capable of improving power efficiency in parallel program execution for performing message communication between processor cores. <P>SOLUTION: In the information processing system for performing parallel processing while performing data communication between two or more computation nodes 1, 2 connected through an inter-node network 5, the computation node 1 includes communication control software for shifting the computation node 1 into a power-saving mode when the computation node 2 is yet to be ready for data reception although a running program on the computation node 1 is ready for data transmission. Otherwise, the computation node 2 includes communication control software for shifting the computation node 2 into the power-saving mode when the computation node 1 is yet to be ready for data transmission although a running program on the computation node 2 is ready for data reception. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an information processing system, and more particularly to a technique effective when applied to power saving control in parallel program execution of a multiprocessor system including a plurality of processor cores and memories.

  According to a study by the present inventor, there are techniques described in Patent Documents 1 and 2 and Non-Patent Document 1, for example, regarding information processing systems.

  In Patent Document 1, the compiler automatically extracts tasks having parallelism from the input program, assigns them to a plurality of cores, performs efficient scheduling, estimates the processing time, and sets the operating frequency and power supply voltage. A multiprocessor system for generating code for optimization is disclosed.

  In Patent Document 2, in a system that provides a mailbox queue for communication between processor cores, a processor core that writes to a full transmission mailbox or a processor core that reads from an empty reception mailbox shifts to a low power state, A method is disclosed in which another processor core returns to normal power mode by reading from a transmit mailbox or writing to a receive mailbox.

Non-Patent Document 1 discloses that the operating frequency and substrate voltage of some processor cores that are not performing arithmetic processing are controlled at high speed according to the execution pattern of a program that is a combination of thread level and process level parallel processing. Discloses a low-power circuit technology that improves power efficiency.
JP 2007-305148 A JP 2007-52790 A H. Aoki, et. al. , VLSI Symposium 2008 "A Powerfulet Ecological Parallel Processing System using Execution -basic Adaptive Power-down Control and CompactQuadupple

  By the way, as a result of examination by the present inventor regarding the information processing system as described above, the following has been clarified.

  In the information processing system as described above, due to the increase in power consumption accompanying the miniaturization of semiconductor elements and the complexity of processor design, there is a limit to the improvement of the performance of the processor core by improving the operating frequency and instruction level parallelism. Yes. Therefore, the design of a single processor core is not complicated, and multi-core processing is progressing to increase performance by increasing the number of cores mounted on a processor chip. Furthermore, in an application field where a large amount of operations need to be executed within a predetermined time, a parallel computer configured by connecting a large number of such processor chips and memories is used to obtain the required processing performance. The

  Recently, three-dimensional packaging technology development that stacks multiple chips is underway, and in the future, it will be configured by connecting a number of system-on-chips in which stacked multi-core processors and memories are three-dimensionally tightly coupled. It is predicted that a parallel computer system will be feasible.

  In such a multiprocessor system, in order to obtain an effective performance proportional to the number of cores, it is necessary to perform parallel processing at a thread level and a process level. In this thread level parallel processing, all processor cores to be used need to share a memory space, whereas in process level parallel processing, there is no limit.

  For embedded processors, where the design of the processor core is often simple in nature, improving the performance through multi-core is a common technique. Scalable high-speed processing through parallelization of programs and the large number of logical blocks over time It is necessary to achieve both power saving by finely controlling spatially.

  As one method for solving this problem, there is a technique of a multiprocessor system that generates a code that optimizes an operating frequency and a power supply voltage, as disclosed in Patent Document 1. As a system for providing a mailbox queue for communication between processor cores, there is a technique disclosed in Patent Document 2. Furthermore, there is a technique disclosed in Non-Patent Document 1 as a low power circuit technique for improving power efficiency in the execution of a program composed of a combination of thread level and process level parallel processing.

  However, in the multiprocessor system as described above, to achieve scalable high-speed processing by parallelizing programs, that is, to obtain effective performance proportional to the number of cores even if the number of cores is increased as the amount of processing increases. It is advantageous to use a distributed memory type multiprocessor system in which a plurality of computing nodes each having a local memory are individually connected and exchange data by message communication via a network. Parallel processing is required.

  Each of these compute nodes is a shared memory type multiprocessor system, and MPI (Message Passing Interface) communication library is often used as interprocess communication control software for describing process level parallel processing.

  Accordingly, one of the objects of the present invention is to provide an information processing system that improves the power efficiency of parallel program execution that performs message communication between processor cores in consideration of the necessity for the multiprocessor system as described above. It is in.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, the outline of a typical one is that an information processing system that performs parallel processing while performing data communication between a plurality of computation nodes connected by a network, and the first computation node is operating on the first computation node. Communication control software for shifting the first computing node to the power saving mode when the program is ready for data transmission but the second computing node is not ready for data reception It is characterized by providing. Alternatively, when the second computation node is not ready for data transmission in the first computation node even though the program running on the second computation node is ready for data reception, Communication control software for shifting the second computing node to the power saving mode is provided.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In other words, the effect obtained by the representative one can provide an information processing system that improves the power efficiency of parallel program execution in which message communication is performed between processor cores.

<Outline of Embodiment of the Present Invention>
In the embodiment of the present invention, in order to improve the power efficiency in an information processing system using a multi-core processor, scalable high-speed processing by process level parallelization and fine control of a large number of logical blocks in time and space are performed. The purpose is to achieve both power savings.

  In order to achieve this object, an information processing system for improving the power efficiency of parallel program execution for performing message communication between processor cores is provided. In the execution of parallel programs at the process level, there are typical patterns in which waiting for process execution occurs when performing inter-process communication due to variations in the execution time of each process. Detection is performed by communication control software represented by the MPI communication library, and the communication control software instructs the frequency / power supply voltage control (hereinafter referred to as FV control) unit to shift to the power saving mode.

  This power saving mode can be set for each logical block such as a processor core or cache memory. The power consumption reduction amount and normal power consumption, such as operating frequency change, clock supply stop, power supply voltage change, power supply stop, etc. Has multiple modes with different return times. Therefore, the normal power mode can be used without affecting the execution time of the entire program by using the mode that can restore the normal power mode in several cycles to tens of cycles with software overhead while retaining the data in the memory device. It is possible to return to

  Each calculation node includes a register group for controlling the power saving mode for each logical block belonging to the calculation node, a register group for setting a return condition to the normal power mode, and a return condition determination unit. Data necessary for determining the return condition is acquired from the DMA controller that accesses the transmission / reception data in the memory.

  In the transition to the power saving mode, the processor core of the first (second) computing node that is ready to transmit (or receive) the message receives (or transmits) the second (first) message. It is determined whether or not reception buffer reservation (or preparation of transmission data) has been completed in the computation node. If securing of the reception buffer (or preparation of transmission data) is not completed, the processor core of the first (second) calculation node returns to the normal power mode for the network adapter of the first (second) calculation node. A condition is set, and an instruction to shift the processor core group and peripheral circuits of the first (second) calculation node to the power saving mode is issued to the FV control unit.

  When returning to the normal power mode, the return condition is determined by monitoring a message transmitted / received by the network adapter of the first (second) calculation node, and FV control of the first (second) calculation node is performed. An instruction to shift the processor core group and peripheral circuits to the normal power mode is issued to the unit.

  The amount of variation in process execution time when a plurality of processes are synchronized, which is the target of application of the power saving mode, varies depending on the contents of the program to be executed. When there are multiple modes with different power saving and recovery time, such as operating frequency change, clock supply stop, power supply voltage change, power supply stop, etc. By making it possible to change the power-saving mode and target block to be migrated with the directives written by the program developer, the optimal balance with the increase in execution time required for migration and restoration can be changed to the processing contents of the program. Accordingly, the reduction amount of power consumption and the increase in execution time required for shifting to and returning from the power saving mode are controlled.

  With the above configuration, when executing a program parallelized at the process level, the communication control software detects a typical pattern of waiting for process execution during inter-process communication, and stops or slows down the operation. The power efficiency can be improved by setting the power saving mode with the optimal return time and the return condition to the normal power mode for the logical block that can be set to the same.

  In addition, the power saving control is performed by detecting whether the preparation for data transmission or data reception in the remote computing node is completed within the transmission function or the reception function in the communication control software and performing power saving control. In a system that performs power saving control, it is possible to increase the power efficiency without changing a parallel program that operates in a system that does not support. In addition, it is possible to change the power saving mode and target block to be transferred according to the directives written by the program developer according to the processing contents of the program, reducing the amount of power consumption, and switching to and returning to the power saving mode. It is possible to optimally control the increase in the execution time required for.

  Hereinafter, embodiments based on the outline of the embodiments of the present invention described above will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

<Configuration of parallel computer system>
FIG. 1 is a block diagram showing an example of the configuration of a parallel computer system which is an embodiment of an information processing system of the present invention.

  The parallel computer system according to this embodiment includes a plurality of calculation nodes and an inter-node network. For example, in the example of FIG. 1, two calculation nodes 1 and 2 each having the same configuration, and an inter-node network 5 It consists of Here, the calculation node 1 will be described as a transmission side, the calculation node 2 will be described as a reception side, and a case where the calculation node 2 is remotely located with respect to the calculation node 1 will be described.

  The computation node 1 includes a plurality (two examples in FIG. 1) of processor cores (cores) 111 and 112, local memories (LM) 121 and 122 that can be accessed independently for each of the processor cores 111 and 112, and a processor core 111. , 112, level 1 cache memories (L 1) 131 and 132 for which coherence is guaranteed, a level 2 cache memory (L 2 cache) 14 shared by the processor cores 111 and 112, a main memory 15, The network adapter 16 and the FV control unit 10 that controls the clock and power supply voltage supplied to these logic blocks are mainly configured.

  Transmission data 17 is stored in the main memory 15 of the calculation node 1. Further, the main memory 15 stores communication control software such as an MPI communication library. Further, the network adapter 16 is provided with a return determination unit 161 for returning to the normal power mode and a DMA controller (DMAC) 162 for accessing the transmission / reception data in the memory.

  Similarly, the calculation node 2 includes two processor cores 211 and 22, two local memories 221 and 222, two level 1 cache memories 231 and 232, a level 2 cache memory 24, a main memory 25, and a network adapter. 26 and the FV control unit 20 are mainly configured. The main memory 25 of the calculation node 2 is provided with a reception buffer 27 and further stores communication control software such as an MPI communication library. Further, the network adapter 26 is provided with a return determination unit 261 and a DMA controller 262.

  In this parallel computer system, when a program parallelized at the process level is executed, a plurality of processes that perform data communication with each other are assigned to a certain computing node 1 and 2, respectively. Each process may be parallelized at a thread level in which a thread is assigned to each of the plurality of processor cores 111, 112, 211, and 212 in the computation nodes 1 and 2.

  In FIG. 1, the process operating on the calculation node 1 causes the transmission data 17 on the main memory 15 to be converted to the process operating on the calculation node 2 by calling a transmission function of communication control software such as the MPI communication library. A case is shown in which replication is performed between the computation node 1 and the computation node 2 via the network adapter 16, the inter-node network 5, and the network adapter 26 to the reception buffer 27 on the main memory 25. The inter-node network 5 may be configured with a shared bus, a crossbar switch, or the like.

  Here, the process on the calculation node 2 side that receives data needs to call a reception function of the communication control software in order to prevent overwriting of necessary data in the reception buffer 27. When the reception function is called, the DMA controller 262 of the network adapter 26 may overwrite the data transmitted from the transmission node 1 in the reception buffer 27.

<Replication of data between compute nodes (calling of transmission function precedes reception function)>
FIG. 2 shows that the process 18 of the calculation node 1 calls the transmission function 191 and then the process 28 of the calculation node 2 calls the reception function 292 so that the transmission data 17 is transferred to the reception buffer 27 between the calculation nodes. FIG. 10 is an explanatory diagram illustrating an example of a message that is transmitted between the calculation nodes 1 and 2 by the transmission function 191 and the reception function 292 when copying in FIG. This transmission function 191 performs synchronous communication that returns when the reception function 292 is called and the corresponding reception is started.

  When the process 18 that has completed the preparation of the transmission data 17 calls the transmission function 191 specifying the address and size of the transmission data area with arguments, the transmission function 191 sends a transmission request control message 31 to the calculation node 2. The transmission data 17 is copied to the communication buffer 190. Upon receiving the transmission request control message 31, the network adapter 26 of the computing node 2 records the transmission request in the control message control queue 293 provided on the main memory 25.

  Next, when the process 28 that has completed the preparation of the reception buffer 27 calls the reception function 292 by specifying the address and size of the reception buffer 27 with arguments, the reception function 292 sends the control message 32 of the reception request to the calculation node 1. Send it out. Upon receiving the reception request control message 32, the network adapter 16 of the computing node 1 records the reception request in the control message control queue 193 provided on the main memory 15.

  After the copy of the transmission data 17 to the communication buffer 190 is completed, the transmission function 191 checks the control queue 193 to confirm whether the reception request control message 32 corresponding to the transmission request control message 31 has arrived. . If it has arrived, a data transfer message 33 between the calculation nodes 1 and 2 from the communication buffer 190 to the communication buffer 290 of the calculation node 2 is activated for the network adapter 16. When the reception is completed, the control node 34 is notified of the reception completion control message 34.

  On the other hand, if the reception request control message 32 has not arrived, it means that the execution of the reception side process 28 is delayed with respect to the transmission side process 18, and the transmission function 191 indicates that the reception request control message 32 is delayed. The processor core 111 or 112 of the computation node 1 enters a loop for polling the control queue 193, and no substantial arithmetic processing is performed.

  Therefore, in order to improve the power efficiency of the parallel program execution, the transmission function 191 issues an instruction to the FV control unit 10 to shift the processor cores 111 and 112 of the computation node 1 on which it operates to the power saving mode. Here, the power saving mode to be transferred may be specified as the environment setting of the communication control software, and a certain amount of time from when it is confirmed that the reception request control message 32 has not arrived until the power saving control is performed. A waiting time may be provided, and this waiting time may be designated as an environment setting of the communication control software.

<Registers of FV control unit and network adapter>
FIG. 3 is a configuration diagram illustrating an example of the register group 101 that instructs the FV control unit 10 to shift to the power saving mode and the register group 163 that sets the return condition to the normal power mode in the network adapter 16. The FV control unit 10 shifts to the power mode corresponding to the register when the logical block set in the register 102 is written in any of the register groups 101. The power saving control instruction in the FV control unit 10 may be realized by setting an instruction code in one instruction register. Alternatively, a logical block to be controlled may be specified for each register group 101 by a bitmap.

  When the power saving mode to be transferred is a mode (LVLF) in which the power supply voltage and the operating frequency are lowered, the polling interval is extended, but the transmission function 191 continues to check the control message 32 of the reception request, and has been confirmed. At this point, an instruction is issued to the FV control unit 10 to return the calculation node 1 to the normal power supply voltage and operating frequency, and then return to continue the execution of the process 18.

  When the power saving mode to be shifted is a mode in which the power supply voltage of the processor cores 111 and 112 is zero (power off) or a mode in which the operating frequency is zero (clock stop), the operation of the transmission function 191 is also stopped. After the conditions necessary for characterizing the control message 32 of the reception request are set in the network adapter 16, the mode shifts to the power saving mode. The network adapter 16 passes a message arriving from the inter-node network 5 to the return determination unit 161, and confirms the arrival of the reception request control message 32 and issues a return command to the normal power mode for the FV control unit 10.

<Register group for setting conditions for returning to normal power mode>
FIG. 4 is a configuration diagram illustrating an example of a register group that sets conditions for returning to the normal power mode. The determination of the return condition in FIG. 4 is performed by a logical operation of the registers 40 to 49 indicating conditions regarding a plurality of words of the message packet. The register 40 indicating the condition relating to each word is composed of a valid bit 401, a condition number 402, a word number 403, a bit mask 404, and word data 405. The value of the valid bit 401 is 1, and from the head of the message packet As for the word of the message packet whose number of words is the value of the word number 403, it is determined to be true when the data of the bit whose value of the bit mask 404 is 0 matches the value of the word data 405. Similarly, the registers 41 to 49 include valid bits 411 to 491, condition numbers 412 to 492, word numbers 413 to 493, bit masks 414 to 494, and word data 415 to 495.

  When the result of logical product of conditions having different condition number values after the logical sum of conditions having the same condition number value among the registers 40 to 49 indicating conditions related to a plurality of words is true Issue a return command to power mode. This condition may be a necessary condition that characterizes the reception request control message 32, and it is not necessary to set a necessary and sufficient condition for strictly specifying the reception request control message 32 corresponding to the transmission request control message 31. Good.

  Further, when returning to the normal power mode, the FV control unit 10 monitors the occurrence of an interrupt by generating a reception interrupt from the network adapter 16 to the processor core 111 or 112 upon arrival of the reception request control message 32. Thus, the processor cores 111 and 112 may be realized to return to the normal power mode.

<Replication of data between compute nodes (calling of reception function precedes transmission function)>
FIG. 5 is different from FIG. 2 in that the process 28 of the calculation node 2 calls the reception function 292, and then the process 18 of the calculation node 1 calls the transmission function 191. It is explanatory drawing which shows an example of the message which the function 292 passes between the calculation nodes 1 and 2. FIG. The reception function 292 is of a blocking type that returns when the data received in the reception buffer 27 has been written.

  When the process 28 having completed the preparation of the reception buffer 27 calls the reception function 292 by specifying the address and size of the reception buffer with arguments, the reception function 292 sends a control message 32 of the reception request to the calculation node 1.

  Next, when the process 18 that has completed the preparation of the transmission data 17 calls the transmission function 191 specifying the address and size of the transmission data area with arguments, the transmission function 191 sends the control message 31 of the transmission request to the calculation node 2. Send it out. Upon receiving the transmission request control message 31, the network adapter 26 of the computing node 2 records the transmission request in the control message control queue 293 provided on the main memory 25.

  The transmission function 191 checks the control queue 193 after the copy of the transmission data 17 to the communication buffer 190 is completed, and confirms that the reception request control message 32 corresponding to the transmission request control message 31 has arrived. The data transfer message 33 between the calculation nodes 1 and 2 from the communication buffer 190 to the communication buffer 290 of the calculation node 2 is activated to the network adapter 16. The reception function 292 copies the transferred data from the communication buffer 290 to the reception buffer 27.

  Accordingly, when the reception request control message 31 has not arrived at the time when the reception function 292 sends out the reception request control message 32, the execution of the transmission side process 18 is delayed with respect to the reception side process 28. When the reception function 292 is a blocking type, the processor core 211 or 212 of the calculation node 2 enters a loop for polling the control queue 293, and no substantial arithmetic processing is performed.

  Therefore, in order to improve the power efficiency of the parallel program execution, the reception function 292 issues an instruction to the FV control unit 20 to shift the processor cores 211 and 212 of the computation node 2 on which it operates to the power saving mode. Here, the power saving mode to be transferred may be specified as the environment setting of the communication control software, and a certain amount of time is required from when it is confirmed that the transmission request control message 31 has not arrived until the power saving control is performed. A waiting time may be provided, and this waiting time may be designated as an environment setting of the communication control software.

  When the power saving mode to be transferred is a mode in which the power supply voltage or the operating frequency of the processor core is zero, in which the operation of the reception function 192 is stopped, the conditions necessary for characterizing the control message 31 of the transmission request are set as the network adapter. After setting to 26, the mode shifts to the power saving mode. The network adapter 26 passes a message arriving from the inter-node network 5 to the return determination unit 261, confirms the arrival of the transmission request control message 31, and issues a return instruction to the FV control unit 20 to return to the normal power mode.

<Collective communication function>
By the way, in many programs parallelized at the process level, a collective communication function for performing operations such as broadcast, all-to-all communication, and summation over a plurality of processes is used. All processes in the process group that participate in collective communication call the collective communication function with arguments for both the send buffer and the receive buffer, and within the collective communication function, specify the destination computation node or the receive computation node. A plurality of transmissions and receptions are performed while changing the pattern according to the type of collective communication.

  Therefore, by using the transmission function and the reception function for performing the power saving control in the collective communication function, it is possible to wait between transmission waiting and reception waiting due to variations in process execution times in the process group. It is possible to improve the power efficiency by shifting the processor core to the power saving mode.

  FIG. 6 shows a process group consisting of processes 18, 28, 38, and 48 operating in the calculation nodes 1 to 4 when the calculation nodes 1 to 4 are configured in addition to the calculation nodes 1 and 2. FIG. 10 is an explanatory diagram showing an example of use of a transmission function and a reception function by a collective communication function that performs all-to-all communication, which is an operation in which each process sends its own data to all processes. Here, there is a variation in the execution time of each process, and the call times of the collective communication functions 1C, 2C, 3C, and 4C are different. Further, 12S, 13S, 21S, 24S, 34S, 31S, 43S, and 42S indicate transmission functions, and correspond to each, and 12R, 13R, 21R, 24R, 34R, 31R, 43R, and 42R indicate reception functions.

  The all-to-all communication involves first exchanging data between compute nodes 1 and 2, and between compute nodes 3 and 4, and then between compute nodes 1 and 3 and compute nodes 2 and 4. Is achieved by exchanging data between them. In the process 18 of the calculation node 1, first, the data of the own process is sent to the process 28 by the transmission function 12S to the calculation node 2, and the data of the process 28 is received by the reception function 21R from the calculation node 2. Next, the data of the own process and the process 28 are sent to the process 38 by the transmission function 13S to the calculation node 3, and the data of the processes 38 and 48 are received by the reception function 31R from the calculation node 3.

  In FIG. 6, since the execution of the process 28 is delayed with respect to the process 18, the power saving control described above for the processor core of the calculation node 1 can be applied in the transmission function 12S. Since the execution of the process 38 is delayed with respect to the process 48, the power saving control for the processor core of the calculation node 4 can be applied in the reception function 34R. Further, since the end of data exchange between the calculation nodes 1 and 2 is delayed with respect to the end of data exchange between the calculation nodes 3 and 4, the processor cores of the calculation nodes 3 and 4 in the reception functions 13R and 24R. The power saving control described above can be applied.

  When exchanging data between two computation nodes, the transmission function 12S and the reception function 12R in FIG. 6 absorb the time difference between the execution time of the process 18 and the process 28 by using a synchronous transmission function. Therefore, with respect to the transmission function 21S and the reception function 21R in the reverse direction that are subsequently performed, an increase in execution time can be suppressed by not applying power saving control with a small effect.

  Similarly, when data is exchanged between two computation nodes, the reception function 34R and the transmission function 34S in FIG. Therefore, power saving control is not applied to the transmission function 43S and the reception function 43R, and an increase in execution time can be suppressed.

<Non-blocking transmission and reception functions>
By the way, in order to shorten the execution time of a program parallelized at the process level, or when each process operates asynchronously, only a transmission or reception is started and a return is performed. May be used.

  Calling the non-blocking transmission function returns before the transmission data is copied, so it is necessary to call the transmission completion function to complete the transmission, that is, to confirm that the transmission data has been copied. It becomes.

  Similarly, a call to a non-blocking receive function returns before the sent data is stored in the receive buffer, so that the receive operation is completed and the data is received in the receive buffer. Needs to call the reception completion function.

  FIG. 7 shows a non-blocking type communication from the process 18 operating on the computing node 1 to the process 28 operating on the computing node 2 and a communication example for shortening the execution time by overlapping the arithmetic processing. It is explanatory drawing. Here, 1NS indicates a non-blocking transmission function call, and correspondingly, 1WS indicates a transmission completion function call, and 1ES indicates a transmission completion function return. In addition, 2NR indicates a non-blocking reception function call, and 2WR indicates a reception completion function call, and 2ER indicates a reception completion function return.

  FIG. 7A shows a case where the transmission activation by the process 18 is issued prior to the reception activation by the process 28. The process 18 having completed the preparation of transmission data performs a non-blocking transmission function call 1NS to start transmission. The non-blocking transmission function sends a transmission request control message 31 shown in FIG. 2 to the calculation node 2 and starts copying the transmission data 17 to the communication buffer 190. The network adapter 26 of the computation node 2 that has received the transmission request control message 31 records the transmission request in the control message control queue 293.

  The non-blocking type transmission function returns without waiting for the completion of copying of the transmission data 17, and the process 18 continues the arithmetic processing and then calls the transmission completion function 1WS.

  On the other hand, when the reception buffer corresponding to the transmission function call 1NS is ready, the process 28 of the computation node 2 performs a non-blocking reception function call 2NR and starts reception. The non-blocking type reception function sends the control message 32 of the reception request shown in FIG. 2 to the calculation node 1 and returns, and in parallel with the subsequent data reception by the network adapter 26, the processor core performs arithmetic processing. To continue. Upon receiving the reception request control message 32, the network adapter 16 of the computing node 1 records the reception request in the control message control queue 193.

  The transmission completion function enters a loop for polling the control queue 193 and waits for the reception request control message 32 to arrive. Therefore, no substantial arithmetic processing is performed in the calculation node 1 from the call 1WS of the transmission completion function to the arrival of the reception request 32.

  Therefore, when the reception request control message 32 has not arrived in the call 1WS, the transmission completion function issues an instruction to the FV control unit to shift the processor core of the computing node 1 on which it operates to the power saving mode. Here, the power saving mode to be transferred may be specified as the environment setting of the communication control software, and a certain amount of time from when it is confirmed that the reception request control message 32 has not arrived until the power saving control is performed. A waiting time may be provided, and this waiting time may be designated as an environment setting of the communication control software.

  FIG. 7B shows a case where the reception activation by the process 28 is issued prior to the transmission activation by the process 28. The process 28 that has secured the reception buffer performs a non-blocking reception function call 2NR and starts reception. The non-blocking reception function sends a reception request control message 32 shown in FIG.

  The non-blocking reception function returns without waiting for the reception of data, and the process 28 continues the arithmetic processing and then calls the reception completion function 2WR.

  On the other hand, when the transmission data corresponding to the reception function call 2NR is prepared, the process 18 of the calculation node 1 performs a non-blocking transmission function call 1NS to start transmission. The non-blocking transmission function sends a transmission request control message 31 shown in FIG. The network adapter 26 of the computation node 2 that has received the transmission request control message 31 records the transmission request in the control message control queue 293.

  The reception completion function enters a loop for polling the control queue 293 and waits for the arrival of the control message 31 for the transmission request. Therefore, no substantial arithmetic processing is performed in the calculation node 2 from the call 2WR of the reception completion function until the arrival of the transmission request control message 31.

  Therefore, when the transmission request control message 31 has not arrived in the call 2WR, the reception completion function issues an instruction to the FV control unit to shift the processor core of the computation node 2 on which it operates to the power saving mode. Here, the power saving mode to be transferred or the waiting time until the power saving control is performed may be designated as the environment setting of the communication control software.

  As shown in FIG. 2, in the communication control software that transmits data via the communication buffer 190, the transmission data 17 is used when the transmission function used is not a synchronous type but a blocking type. However, when the memory copy to the communication buffer 190 is completed and the transmission data area can be overwritten, the process can return without waiting for the start of data transfer to the computation node 2. Since the process 18 can continue the process without depending on the execution status of the process 28 of the remote computing node 2, it is not necessary to shift to the power saving mode.

  Even in the transmission completion function of the communication activated by the non-blocking transmission function, the process can be continued without depending on the execution status of the remote computing node as described above, so that it is not necessary to shift to the power saving mode.

  On the other hand, in a program for communicating a large amount of data between processes, the communication method via the communication buffers 190 and 290 shown in FIG. It becomes.

<Method in which network adapter directly accesses transmission data and reception buffer>
FIG. 8 shows that in the transmission function 191 and the reception function 292, when the amount of data transferred by one transmission and reception is larger than the threshold values 194 and 294, the network adapter 16 directly reads the transmission data 17, It is explanatory drawing which shows the system in which the data transferred to the calculation node 2 writes the data directly to the receiving buffer 27 by the network adapter 26.

  At this time, the blocking type transmission function 191 or the transmission completion function of the communication started in the non-blocking type, which is called in advance with respect to the calling of the reception function 292, is the network adapter 16 that transmits all the transmission data 17. Does not return until the reading is complete. Therefore, it is possible to issue an instruction to shift the processor core of the computation node 1 on which the FV control unit operates to the power saving mode. In addition, since the network adapter 16 reads the transmission data 17, the application time of the power saving mode is determined by setting the timing when the processor core returns from the power saving mode to the normal power mode when the reading of the transmission data 17 is completed. Can be extended.

  Furthermore, since the network adapter 26 writes to the reception buffer 27 in the calculation node 2 on the reception side, the timing when the processor core returns from the power saving mode to the normal power mode is the time when the writing to the reception buffer 27 is completed. Thus, power efficiency can be improved.

<Effects of the present embodiment>
As described above, according to the present embodiment, in the communication control software represented by the MPI communication library, a transmission function, a reception function, a transmission completion function activated by a non-blocking type, a reception completion function, or a plurality of functions A system that does not support power saving control by detecting the transition condition to the power saving mode, setting the return condition to the normal power mode, and performing power saving control inside the collective communication function with multiple data transmission / reception In a system that performs power saving control, the power efficiency can be improved and executed without changing the parallel program that operates in step.

  In addition, to improve power efficiency, program development is possible when there are multiple modes with different power savings and recovery times, such as operating frequency change, clock supply stop, power supply voltage change, power supply stop, etc. It is desirable that the person can change the power saving mode to be transferred and the target block according to the processing contents of the program.

  The program developer estimates the degree of variation in process execution time that may occur at the time of calling the communication function to which the power saving control is applied, the frequency and granularity of communication, and executes execution for shifting to and returning to the power saving mode. By contrasting with the increase in time, the optimum power saving mode is selected including the case where communication is performed in the normal power mode. The selected power saving mode is written as a directive that is interpreted as a comment and does not affect execution in a system that does not support power saving control. It is possible to optimally control the reduction amount and the increase in execution time required for shifting to and returning to the power saving mode.

<Additional functions and application examples of this embodiment>
In the following, as an additional function and an application example in the parallel computer system according to the present embodiment, a target block for power saving control, an administrator authority and a user authority, and a system on chip will be described.

<Target block for power saving control>
The target block to be shifted to the power saving mode will be described below. Logic blocks other than the processor core in the parallel computer system shown in FIG. 1 can be targeted for power saving control.

  When the network adapters 16 and 26 and the inter-node network 5 are networks that are not used for communication with an external system and are occupied by the communication function, there is no information to be processed in the network adapter 16 or 26, and a certain period of time. If there is no writing, it shifts itself to the power saving mode, and returns to the normal power mode when information for transmission or reception is written.

  The main memory 15 or 25 can shift to the power saving mode and return to the normal power mode together with the power saving control for the processor cores 111, 112 or 211, 212 by control from the communication function.

  FIG. 1 shows that the coherence of the level 1 and level 2 cache memories 231, 232 and 24 in the reception side calculation node 2 with respect to the level 1 and level 2 cache memories 131, 132 and 14 of the transmission side calculation node 1 Cache memory 231, 232, and 24 in the calculation node 2 on the receiving side saves the area of the reception buffer 27 in the blocking-type reception function from the cache purge to the return. It is possible to shift to the power mode.

  When the transmission data 17 is prepared in the local memory 121 or 122 and data transmission is performed between the local memories independent of the cache memory, the cache memories 131, 132 and 14 in the calculation node 1 on the transmission side are blocked. In this transmission function, it is possible to shift to the power saving mode from the start of data transfer from the calculation nodes 1 to 2 until the transmission function returns.

  When the reception buffer 27 is prepared in the local memory 221 or 222 and data is received between the local memories independent of the cache memory, the cache memories 231, 232, and 24 in the calculation node 2 on the reception side are blocking types. In the reception function, it is possible to shift to the power saving mode from when the data transfer from the calculation node 1 to 2 is started until the reception function returns.

<Administrator authority and user authority>
By the way, one of the features of the present invention is that the operating system for managing resources in the computing node does not perform power saving control with administrator authority, but performs power saving control within a communication function executed with user authority. There are things to do. When the operating system is executing a high-priority process in parallel with the user program execution that shifts to the power saving mode, the power saving with the administrator authority is performed for the power saving control with the user authority. Control needs to be prioritized.

  FIG. 9 is a configuration diagram showing an example of a configuration in which the FV control unit 10 is separately provided with a power saving control register 103 that can set a value only in a privilege mode with administrator authority and a register 104 that sets a control target logical block. . Here, when a value is set in the power saving control register 103 by the administrator authority, the power saving control from the user program cannot be performed.

<System on chip>
As one mode of realization of the present invention, a plurality of system-on-chips in which three-dimensionally stacked multi-core processor chips and memory chips are three-dimensionally coupled using a three-dimensional mounting technique in which a plurality of chips are stacked are connected via a node-to-node network. A connected system configuration can be mentioned. Here, the multi-core processor chip includes a processor core and a cache memory associated with each processor core.

  When stacking multi-core processor chips and memory chips that are not premised on three-dimensional implementation as logical components, the multi-core implemented in two dimensions without having a hardware cache coherence control function for three-dimensional connections. This may only be done inside the processor chip.

  FIG. 10 is an explanatory diagram showing an example of a system-on-chip in which the multi-core processor chips 51 and 52, the memory chips 61 and 62, and the interface chip 71 are connected by the three-dimensional connection buses 81 to 84. Although not limited thereto, for example, in correspondence with FIG. 1, the multi-core processor chips 51 and 52 are provided with a processor core and a level 1 cache memory, and the memory chips 61 and 62 are provided with main memory and local memory. A level 2 cache memory is provided, and the interface chip 71 is provided with a network adapter and an FV control unit.

  The scope of application of the cache memory coherence control is limited to a part of the core group sharing the main memory on the memory chips 61 and 62. In the calculation node of FIG. Since the cache memory on the multi-core processor chip 51 is not affected by the main memory access by the core operating in the other multi-core processor chip 52 when the core shifts to the power saving mode in which the operation is stopped, the power-saving mode is not affected. Can be migrated to. For example, when processing other than the communication function performed on the multicore processor chip 52 is not performed, the cache memory on the multicore processor chip 52 may be subjected to coherence control by main memory access of the communication function. While the operation is not stopped, the power saving mode is applied to the cache memory on the multi-core processor chip 51 to stop the operation.

  In a system-on-chip in which a multi-core processor chip and a memory chip are three-dimensionally mounted as shown in FIG. 10, coherence control by hardware of cache memory is performed for each multi-core processor chip 51 or 52 having a processor core and a cache memory associated therewith. The cache memory can be shifted to the power saving mode according to the range covered by.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is applied to an information processing system composed of multi-core processors connected by a network, thereby shifting to a power saving mode and returning to a normal power mode for each logical block within a communication function of communication control software. By doing so, it is possible to achieve both scalable high-speed processing and power saving by parallelization at the process level.

It is a block diagram which shows an example of a structure of the parallel computer system which is one Embodiment of the information processing system of this invention. FIG. 6 is an explanatory diagram illustrating an example of a message passed between calculation nodes when a transmission function call precedes a reception function call in time in an embodiment of the information processing system of the present invention. FIG. 5 is a configuration diagram illustrating an example of a register group that sets a command to shift to a power saving mode and a condition for returning to a normal power mode in an embodiment of the information processing system of the present invention. It is a block diagram which shows an example of the register | resistor group which sets the return conditions to normal power mode in one Embodiment of the information processing system of this invention. In one embodiment of the information processing system of this invention, it is explanatory drawing which shows an example of the message passed between calculation nodes when the call of a reception function precedes the call of a transmission function temporally. It is explanatory drawing which shows the usage example of the transmission function by the collective communication function which performs all-to-all communication, and the reception function in one Embodiment of the information processing system of this invention. It is explanatory drawing which shows the non-blocking type | mold communication example (a), (b) which overlaps with a calculation process in one Embodiment of the information processing system of this invention. In one embodiment of the information processing system of this invention, it is explanatory drawing which shows the system in which a network adapter directly accesses transmission data and a reception buffer. It is a block diagram which shows an example of a structure of the power saving control register which isolate | separated the register which can be set only with an administrator authority in one Embodiment of the information processing system of this invention. In an embodiment of an information processing system of the present invention, it is an explanatory diagram showing an example of a system-on-chip in which a multi-core processor chip and a memory chip are stacked.

Explanation of symbols

1, 2, 3, 4 Calculation nodes 5 Inter-node network 10, 20 FV control unit (frequency / power supply voltage control unit)
101 Register Group 102 Register 103 Power Saving Control Register 104 Register 111, 112, 211, 212 Processor Core 121, 122, 221, 222 Local Memory 131, 132, 231, 232 Level 1 Cache Memory 14, 24 Level 2 Cache Memory 15, 25 Main memory 16, 26 Network adapter 17 Transmission data 27 Reception buffer 161, 261 Return determination unit 162, 262 DMA controller 163 Register group 18, 28, 38, 48 Process 190, 290 Communication buffer 191 Transmission function 292 Reception function 193, 293 Control queue 194, 294 Threshold value 31 Transmission request control message 32 Reception request control message 33 Data transfer message 34 Reception completion control message 0-49 registers 401-491 enable bits 402-492 condition number 404-494 bitmask 405-495 word data 51, 52 multi-core processor chip 61 memory chip 71 interface chip 81 to 84 three-dimensional connection bus

Claims (20)

An information processing system comprising a plurality of calculation nodes and a network connecting the plurality of calculation nodes, and performing parallel processing while performing data communication between the plurality of calculation nodes connected by the network,
The plurality of computation nodes include a first computation node and a second computation node,
The first computing node is configured to execute the first computing node when a program running on the first computing node is ready for data transmission and the second computing node is not ready for data reception. An information processing system comprising communication control software for shifting the computing node to a power saving mode. The information processing system according to claim 1,
Whether the first calculation node is ready for data reception in the second calculation node, the transmission function in the communication control software, the non-blocking transmission completion function, or the plurality of calculation nodes An information processing system that performs power saving control by detecting within a collective communication function that performs synchronous data transmission and reception. The information processing system according to claim 2,
The information processing system, wherein the communication control software is an MPI communication library. The information processing system according to claim 2,
Each function of the transmission function, the transmission completion function, and the collective communication function can change a power saving mode and a target block to be transferred according to an instruction written by a program developer, and depends on a program processing content. An information processing system that controls a reduction in power consumption and an increase in execution time required for shifting to and returning to a power saving mode. The information processing system according to claim 1,
The first computing node comprises a network adapter connected to the network;
The network adapter includes a register group for setting a condition for returning to the normal power mode, and a determination unit that monitors transmission / reception packets and determines the return condition. When the return condition is satisfied, the frequency / power supply voltage An information processing system for instructing a control unit to return to a normal power mode. The information processing system according to claim 5,
The frequency / power supply voltage control unit includes a register group that controls the transition to the power saving mode,
The register group for controlling the transition to the power saving mode provided in the frequency / power supply voltage control unit, and the register group for setting a condition for returning to the normal power mode provided for the network adapter are obtained from the communication control software. An information processing system comprising: a register group that can be set; and a register group in which an operating system performs power saving control in a privileged mode. The information processing system according to claim 1,
The first computing node is a chip that integrates a plurality of processor cores, a cache memory associated with each processor core, and a main memory, and is three-dimensionally mounted in one package. Coherence by hardware of the cache memory An information processing system for performing a power saving mode shift of a logical block of the cache memory according to a range to which control is applied. An information processing system comprising a plurality of calculation nodes and a network connecting the plurality of calculation nodes, and performing parallel processing while performing data communication between the plurality of calculation nodes connected by the network,
The plurality of computation nodes include a first computation node and a second computation node,
The second computing node is configured such that when the program running on the second computing node is ready to receive data and the first computing node is not ready to send data, the second computing node An information processing system comprising communication control software for shifting the computing node to a power saving mode. The information processing system according to claim 8,
Whether the second calculation node is ready for data transmission in the first calculation node, the reception function in the communication control software, the non-blocking reception completion function, or the plurality of calculation nodes An information processing system that performs power saving control by detecting within a collective communication function that performs synchronous data transmission and reception. The information processing system according to claim 9,
The information processing system, wherein the communication control software is an MPI communication library. The information processing system according to claim 9,
The functions of the reception function, the reception completion function, and the collective communication function can change the power saving mode and the target block to be transferred according to the directives written by the program developer, depending on the processing contents of the program An information processing system that controls a reduction in power consumption and an increase in execution time required for shifting to and returning to a power saving mode. The information processing system according to claim 8,
The second computing node comprises a network adapter connected to the network;
The network adapter includes a register group for setting a condition for returning to the normal power mode, and a determination unit that monitors transmission / reception packets and determines the return condition. When the return condition is satisfied, the frequency / power supply voltage An information processing system for instructing a control unit to return to a normal power mode. The information processing system according to claim 12,
The frequency / power supply voltage control unit includes a register group that controls the transition to the power saving mode,
The register group for controlling the transition to the power saving mode provided in the frequency / power supply voltage control unit, and the register group for setting a condition for returning to the normal power mode provided for the network adapter are obtained from the communication control software. An information processing system comprising: a register group that can be set; and a register group in which an operating system performs power saving control in a privileged mode. The information processing system according to claim 8,
The second computing node is a chip that integrates a plurality of processor cores, a cache memory associated with each processor core, and a main memory, and is three-dimensionally mounted in one package. Coherence by hardware of the cache memory An information processing system for performing a power saving mode shift of a logical block of the cache memory according to a range to which control is applied. An information processing system comprising a plurality of calculation nodes and a network connecting the plurality of calculation nodes, and performing parallel processing while performing data communication between the plurality of calculation nodes connected by the network,
The plurality of calculation nodes include a first calculation node and a second calculation node each having communication control software which is an MPI communication library,
In the communication control software on the first calculation node, the program running on the first calculation node is not ready for data transmission, and the second calculation node is not ready for data reception. The first compute node is shifted to a power saving mode,
In the communication control software on the second calculation node, the program running on the second calculation node is ready for data reception, and the first calculation node is not ready for data transmission. In this case, the information processing system is characterized in that the second computing node is shifted to a power saving mode. The information processing system according to claim 15,
The first calculation node and the second calculation node transmit in the communication control software whether the second calculation node or the first calculation node is ready for data reception or data transmission. A function, a reception function, a non-blocking transmission completion function, a reception completion function, or a collective communication function in which the plurality of calculation nodes perform data transmission and reception synchronously, and perform power saving control Information processing system. The information processing system according to claim 16,
Each of the transmission function, the reception function, the transmission completion function, the reception completion function, and the collective communication function can change the power saving mode and target block to be transferred according to an instruction sentence written by a program developer. An information processing system that controls a reduction in power consumption and an increase in execution time required for shifting to and returning to a power saving mode according to the processing content of a program. The information processing system according to claim 15,
Each of the first calculation node and the second calculation node includes a network adapter connected to the network;
The network adapter includes a register group for setting a condition for returning to the normal power mode, and a determination unit that monitors transmission / reception packets and determines the return condition. When the return condition is satisfied, the frequency / power supply voltage An information processing system for instructing a control unit to return to a normal power mode. The information processing system according to claim 18,
The frequency / power supply voltage control unit includes a register group that controls the transition to the power saving mode,
The register group for controlling the transition to the power saving mode provided in the frequency / power supply voltage control unit, and the register group for setting a condition for returning to the normal power mode provided for the network adapter are obtained from the communication control software. An information processing system comprising: a register group that can be set; and a register group in which an operating system performs power saving control in a privileged mode. The information processing system according to claim 15,
Each of the first calculation node and the second calculation node is a chip that is three-dimensionally mounted in one package by integrating a plurality of processor cores, a cache memory associated with each processor core, and a main memory. An information processing system for performing a power saving mode shift of a logical block of the cache memory in accordance with a range to which coherence control by hardware of the cache memory extends.

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