CN114328350A - Communication method, device and medium based on AXI bus - Google Patents
Communication method, device and medium based on AXI bus Download PDFInfo
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Abstract
The application discloses an AXI bus-based communication method, device and medium, wherein bus signals are received through an AXI bus, then the bus signals are converted into RAM interface signals, the address signals in the RAM interface signals are converted into simplified addresses adaptive to peripheral devices according to the addresses of the peripheral devices, and finally the peripheral devices are informed to execute corresponding actions according to the simplified addresses of the peripheral devices and corresponding data signals. By adopting the technical scheme, after the bus signal of the AXI bus is received, the bus signal is analyzed, and the bus signal is converted into the RAM interface signal suitable for the RAM interface, so that more peripheral equipment can realize the communication with the processor through the AXI bus without additionally developing the AXI bus interface, and the waste of resources is reduced. And the total address signals are optimized, the size of the signals is reduced, data can be stored quickly, and the release speed of the bus authority is improved.
Description
Technical Field
The present application relates to the field of SOC technologies, and in particular, to a communication method, apparatus, and medium based on an AXI bus.
Background
An SOC is called a system-on-chip, also called a system-on-chip, meaning that it is a product, an integrated circuit with a dedicated target, which contains the complete system and has the entire content of embedded software. The bus, which is a connector in the SOC, enables communication between the processor and various peripheral devices. High performance SOCs have increasingly high performance requirements for the bus. The AXI bus is a high-performance, high-bandwidth, low-latency multichannel transmission on-chip bus, and has separate address, control and data phases, supports misaligned data transmission and out-of-order access, and enables the SOC to obtain more excellent performance with a smaller area and lower power consumption, and thus is widely used.
However, most of the interfaces of the peripheral devices are usually RAM interfaces, and do not have AXI bus interfaces, when the SOC uses an AXI bus, the peripheral devices need to additionally develop the AXI bus interfaces, so that the processor and the peripheral devices perform data interaction, and this method causes waste of resources.
Therefore, how to reduce the waste of resources is a problem to be solved urgently by those skilled in the art, when the processor and the peripheral device use the AXI bus for communication, no additional AXI bus interface needs to be developed.
Disclosure of Invention
The purpose of the present application is to provide an AXI bus-based communication method, apparatus and medium, which are used for reducing resource waste without additionally developing an AXI bus interface when a processor and a peripheral device use an AXI bus for communication.
To solve the above technical problem, the present application provides a communication method based on an AXI bus, including:
receiving bus signals of an AXI bus, wherein the bus signals comprise address channel signals and data channel signals;
analyzing the bus signal, and converting the bus signal into an RAM interface signal, wherein the RAM interface signal comprises an address signal and a data signal;
converting the address signal in the RAM interface signal into a reduced address adapted to each peripheral device according to the address of each peripheral device;
and notifying each peripheral device to perform a corresponding action according to the reduced address of each peripheral device and the corresponding data signal.
Preferably, after the step of converting the address signal into the reduced address, the method further includes:
associating the simplified addresses of the peripheral equipment with the corresponding data signals, and storing the simplified addresses in a queue to be processed in sequence;
further, the notifying each peripheral device of performing the corresponding action according to the reduced address of each peripheral device and the corresponding data signal includes:
and informing each peripheral device to execute corresponding actions according to the simplified addresses and the sequence of the corresponding data signals in the queue to be processed.
Preferably, before the step of notifying each of the peripheral devices to perform the corresponding action according to the order of the reduced address and the corresponding data signal in the queue to be processed, the method further includes:
judging whether the peripheral equipment corresponding to the current data of the queue to be processed is in an idle state;
if yes, the step of informing the peripheral equipment to execute corresponding actions according to the simplified addresses and the sequence of the corresponding data signals in the queue to be processed is carried out;
if not, storing the simplified address of the peripheral equipment and the corresponding data signal into an unresponsive queue.
Preferably, the method further comprises the following steps:
and if the peripheral equipment corresponding to the simplified address and the corresponding data signal in the unresponsive queue is detected to be in an idle state, preferentially executing the simplified address and the corresponding data signal in the unresponsive queue.
Preferably, before the step of associating the reduced address of each of the peripheral devices with the corresponding data signal and storing the reduced addresses in the queue to be processed in sequence, the method further includes:
judging whether the queue to be processed is full;
if not, the step of associating the simplified address of each peripheral device with the corresponding data signal and storing the simplified addresses in a queue to be processed in sequence is carried out;
and if so, stopping the analysis of the bus signal.
Preferably, before the step of storing the reduced address of the peripheral device and the corresponding data signal into an unresponsive queue, the method further includes:
judging whether the non-response queue is not full and the queue to be processed is not empty;
if yes, entering the step of storing the simplified address of the peripheral equipment and the corresponding data signal into an unresponsive queue.
Preferably, if the data signal is a read signal, after the step of notifying each of the peripheral devices to execute the corresponding action, the method further includes:
and converting the data returned by the peripheral equipment into a read data path format of the AXI bus and outputting the read data path format to a processor.
To solve the above technical problem, the present application further provides an AXI bus-based communication device, including:
a receiving module, configured to receive bus signals of an AXI bus, where the bus signals include address channel signals and data channel signals;
the analysis module is used for analyzing the bus signals and converting the bus signals into RAM interface signals, and the RAM interface signals comprise address signals and data signals;
the conversion module is used for converting the address signal in the RAM interface signal into a simplified address which is adapted to each peripheral device according to the address of each peripheral device;
and the scheduling module is used for notifying each peripheral device to execute corresponding actions according to the simplified address of each peripheral device and the corresponding data signal.
In order to solve the above technical problem, the present application further provides another AXI bus-based communication device, including:
a memory for storing a computer program;
a processor for implementing the steps of the AXI bus-based communication method as described above when executing the computer program.
To solve the above technical problem, the present application further provides a computer-readable storage medium, having a computer program stored thereon, where the computer program, when executed by a processor, implements the steps of the AXI bus-based communication method as described above.
According to the communication method based on the AXI bus, bus signals are received through the AXI bus, the bus signals comprise address channel signals and data channel signals, then the bus signals are analyzed, the bus signals are converted into RAM interface signals, the RAM interface signals comprise address signals and data signals, the address signals in the RAM interface signals are converted into simplified addresses adaptive to the peripheral devices according to the addresses of the peripheral devices, and finally the peripheral devices are informed to execute corresponding actions according to the simplified addresses of the peripheral devices and the corresponding data signals. Compared with the prior art, the AXI bus interface needs to be additionally developed on the peripheral equipment, which causes waste of resources. By adopting the technical scheme, after the bus signals of the AXI bus are received, the bus signals are converted into the RAM interface signals suitable for the RAM interface, so that more peripheral equipment can realize the communication with the processor through the AXI bus without additionally developing the AXI bus interface, and the waste of resources is reduced. And the total address signal is converted into a simplified address adapted to each peripheral device according to the address of each peripheral device, so that the address signal is optimized, the size of the signal is reduced, data can be stored quickly, and the release speed of the bus authority is improved.
In addition, the communication device and medium based on the AXI bus provided by the application correspond to the communication method based on the AXI bus, and the effect is the same as the above.
Drawings
In order to more clearly illustrate the embodiments of the present application, the drawings needed for the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.
Fig. 1 is a flowchart of an AXI bus-based communication method according to an embodiment of the present application;
fig. 2 is a structural diagram of a communication device based on an AXI bus according to an embodiment of the present application;
fig. 3 is a structural diagram of another AXI bus-based communication device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without any creative effort belong to the protection scope of the present application.
The embedded system is a hot spot in the development of the computer industry at present, and with the rapid development of super-large-scale integrated circuits, the semiconductor industry enters a deep submicron era, the characteristic size of a device is smaller and smaller, the chip scale is larger and larger, and millions to hundreds of millions of transistors can be integrated on a single chip. Such a dense integration level enables the integration of functions previously implemented by several chips, such as a CPU and several I/O interfaces, on a small chip, and a monolithic integrated circuit constitutes a powerful and complete system, which is called a system on chip SOC.
Axi (advanced eXtensible interface) is a high performance, high bandwidth, low latency on-chip bus. The address/control and data phase of the system are separated, unaligned data transmission is supported, meanwhile, in burst transmission, only a first address is needed, simultaneously, a data reading and writing channel is separated, obvious transmission access and disorder access are supported, time sequence convergence is easier to carry out, and the system can meet the requirements of ultra-high performance and complex SOC design.
However, the interface of most peripheral devices on the SOC is usually a RAM interface, and is not provided with an AXI bus interface, when the SOC uses an AXI bus, the peripheral devices need to additionally develop the AXI bus interface, so that the processor and the peripheral devices perform data interaction, and this method causes waste of resources.
The core of the application is to provide a communication method, a device and a medium based on an AXI bus, which are used for reducing the waste of resources without additionally developing an AXI bus interface when a processor and peripheral equipment use the AXI bus for communication.
In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings.
Fig. 1 is a flowchart of an AXI bus-based communication method according to an embodiment of the present application, and as shown in fig. 1, the method includes:
s10: bus signals of an AXI bus are received, and the bus signals comprise address channel signals and data channel signals.
The AXI can enable the SOC to obtain more excellent performance with smaller area and lower power consumption. One of the main reasons AXI achieves such excellent performance is its unidirectional channel architecture. The one-way channel architecture enables information flow on the chip to be transmitted in only one direction, and delay is reduced. In addition to reducing latency, the AXI bus also defines a handshake protocol before and after entering and exiting the low power saving mode. It is specified how to signal entry into the low power mode, when to turn off the clock, when to turn on the clock, and how to exit the low power mode. This allows all IPs to be easily integrated into a unified system, depending on the design of power consumption control. AXI is characterized as follows:
one-way channel architecture: the information flow is transmitted in one direction only, which simplifies the bridging between clock domains and reduces the number of gates. Latency is reduced when signals pass through complex systems on chip.
Supporting multiple data exchange: by executing burst operation in parallel, the data throughput capacity is greatly improved, tasks can be completed in a shorter time, and the power consumption is reduced while the high-performance requirement is met.
Independent address and data channels: the address and data channels are separated, each channel can be optimized independently, the time sequence channel can be controlled according to needs, the clock frequency is increased to the highest, and the delay is reduced to the lowest.
Enhanced flexibility: AXI technology has a symmetric master-slave interface, and can be conveniently used in both point-to-point and multi-layer systems.
The AXI bus has 5 channels, which are a read address channel, a write address channel, a read data channel, a write data channel, and a write response channel, respectively. Each channel is unidirectional. The address channel carries control messages for describing transmitted data attributes, the data transmission uses a write channel to realize the transmission from 'master' to 'slave', and the 'slave' uses a write response channel to complete the write transmission once; the read channel is used to effect the transfer of data from "slave" to "master".
In this embodiment, the address channel signals are read address channel signals and write address channel signals, and the data channel signals are read data channel signals and write data channel signals.
S11: and analyzing the bus signals, and converting the bus signals into RAM interface signals, wherein the RAM interface signals comprise address signals and data signals.
In step S11, the bus signals are converted into RAM interface signals including read address signals, write address signals, read data signals, and write data signals according to reading and writing.
It can be understood that, when the RAM interface signal is a read signal, data returned by the peripheral device needs to be converted into a mode of an AXI bus signal, and the converted data is returned to the processor through the AXI bus.
S12: and converting the address signals in the RAM interface signals into simplified addresses adapted to the peripheral equipment according to the addresses of the peripheral equipment.
In a specific implementation, the address channel signals acquired by the AXI bus from the processor include a total address signal for controlling the operation of each peripheral device, and the corresponding peripheral device needs to be found by reading the total address signal when each peripheral device is controlled. However, repeated reading of the global address signal causes signal redundancy and delays the response time of the peripheral devices, slowing the speed at which the processor releases the bus privilege.
In this embodiment, the total address signal is simplified according to the address of each peripheral device, and the total address signal with a large bit width is converted into a simplified address adapted to each peripheral device. It can be understood that the optimized reduced address and the corresponding data signal are stored on the bus together, and the process is based on the high-frequency clock of the bus, so that the bus can store data quickly, and the release speed of the bus authority is improved.
S13: and informing the peripheral equipment to execute corresponding actions according to the reduced address of the peripheral equipment and the corresponding data signal.
In step S13, each peripheral device is notified to execute the corresponding read data or write data operation based on the reduced address of each peripheral device.
According to the communication method based on the AXI bus, bus signals are received through the AXI bus, the bus signals comprise address channel signals and data channel signals, then the bus signals are analyzed, the bus signals are converted into RAM interface signals, the RAM interface signals comprise address signals and data signals, the address signals in the RAM interface signals are converted into simplified addresses adaptive to the peripheral devices according to the addresses of the peripheral devices, and finally the peripheral devices are informed to execute corresponding actions according to the simplified addresses of the peripheral devices and the corresponding data signals. Compared with the prior art, the AXI bus interface needs to be additionally developed on the peripheral equipment, which causes waste of resources. By adopting the technical scheme, after the bus signals of the AXI bus are received, the bus signals are converted into the RAM interface signals suitable for the RAM interface, so that more peripheral equipment can realize the communication with the processor through the AXI bus without additionally developing the AXI bus interface, and the waste of resources is reduced. And the total address signal is converted into a simplified address adapted to each peripheral device according to the address of each peripheral device, so that the address signal is optimized, the size of the signal is reduced, data can be stored quickly, and the release speed of the bus authority is improved.
On the basis of the above embodiments, in order to increase the data transmission rate, process a large number of data streams, match systems having different transmission rates, the continuous data streams are buffered, data loss during the machine-in and storage operations is prevented, frequent bus operations are avoided, the load on the processor is reduced, and data is processed in a first-in first-out mode.
Specifically, in this embodiment, after the step of converting the address signal into the reduced address, the method further includes:
associating the simplified addresses of the peripheral equipment with the corresponding data signals, and storing the simplified addresses in a queue to be processed in sequence;
further, notifying each peripheral device to execute a corresponding action according to the reduced address of each peripheral device and the corresponding data signal includes:
and informing each peripheral device to execute corresponding actions according to the simplified addresses and the sequence of the corresponding data signals in the queue to be processed.
The communication method based on the AXI bus provided by the embodiment of the application stores the simplified addresses of the peripheral devices and the corresponding data signals into the FIFO memory, processes data in a first-in first-out mode, can increase the data transmission rate, reduces the burden of a processor, and improves the speed of releasing the bus permission.
In a specific implementation, a peripheral device corresponding to a new data signal may still execute an action corresponding to a previous data signal, and cannot respond to the new data signal in time, which may cause other data signals to continue executing a task or cause the new data signal to be lost if the peripheral device is not processed.
Therefore, on the basis of the foregoing embodiment, in this embodiment, before the step of notifying, according to the reduced address and the corresponding data signal, each peripheral device to execute the corresponding action in the order of the queue to be processed, the method further includes:
judging whether the peripheral equipment corresponding to the current data of the queue to be processed is in an idle state;
if yes, the step of informing the peripheral equipment to execute corresponding actions according to the sequence of the simplified addresses and the corresponding data signals in the queue to be processed is carried out;
if not, the simplified address of the peripheral equipment and the corresponding data signal are stored in the unresponsive queue.
It is understood that, in the present embodiment, if the peripheral device is in the idle state, the action corresponding to the current data of the queue to be processed is performed. If the state is not the idle state, the current data is stored in the unresponsive queue, and the data storage of the unresponsive queue is stored in a first-in first-out mode. In the subsequent task execution, the data in the unresponsive queue can be processed preferentially; or processing the data in the unresponsive queue after all the data in the queue to be processed is processed; or processing the current data in the unresponsive queue immediately when detecting that the peripheral device corresponding to the current data in the unresponsive queue is idle.
The communication method based on the AXI bus stores the simplified address and the corresponding data signal which are not responded by the peripheral equipment in time into the unresponsive queue, and avoids signal loss or data processing delay caused by no response.
In the foregoing embodiment, there is no limitation on when to process the data in the unresponsive queue, and on the basis of the foregoing embodiment, in this embodiment, the method further includes:
and if the peripheral equipment corresponding to the simplified address and the corresponding data signal in the unresponsive queue is detected to be in an idle state, preferentially executing the simplified address and the corresponding data signal in the unresponsive queue.
It should be noted that, in this embodiment, the execution speed of the unresponsive queue is prior to that of the pending queue, and if the peripheral device corresponding to the current data of the unresponsive queue and the current data of the pending queue is the same device and is in an idle state, the peripheral device preferentially executes the action corresponding to the current data of the unresponsive queue.
According to the communication method based on the AXI bus, when peripheral equipment corresponding to current data in an unresponsive queue is idle, the current data in the unresponsive queue is processed preferentially, and task delay caused by the fact that the peripheral equipment does not respond to the current data in time is avoided.
In the specific implementation, since the storage space of the bus is limited, when the bus signal is excessive, the pending queue can only store part of the signal.
Therefore, on the basis of the above embodiment, in this embodiment, before the step of associating the reduced address of each peripheral device with the corresponding data signal and storing the reduced addresses in the queue to be processed in sequence, the method further includes:
judging whether the queue to be processed is full;
if not, the simplified address of each peripheral device is associated with the corresponding data signal, and the simplified addresses are stored in the queue to be processed in sequence;
if yes, the analysis of the bus signal is stopped.
According to the communication method based on the AXI bus, the analysis of the bus signals is stopped when the queue to be processed is full according to the storage space of the queue to be processed, and system breakdown caused by excessive data is avoided.
Pending queues have a memory space limit, and similarly, nonresponsive queues have a memory space limit.
Therefore, on the basis of the foregoing embodiment, in this embodiment, before the step of storing the reduced address of the peripheral device and the corresponding data signal into the unresponsive queue, the method further includes:
judging whether the non-response queue is not full and the queue to be processed is not empty;
if yes, the step of storing the simplified address of the peripheral equipment and the corresponding data signal into the unresponsive queue is carried out.
It can be understood that, in this embodiment, when the peripheral device corresponding to the current data of the queue to be processed is not in an idle state, the current data is stored in the unresponsive queue, before the current data is stored, it is required to determine whether the unresponsive queue has a storage space, and the current data may be stored when the unresponsive queue is not full. And if no other data signal needs to be processed in the queue to be processed, the current data does not need to be stored in the unresponsive queue. Of course, in other embodiments, if the peripheral device cannot return to the idle state for a later time, the current data may also be stored in the unresponsive queue in order to avoid affecting the processing speed of subsequent newly added data signals.
According to the communication method based on the AXI bus, when the unresponsive queue is not full and the queue to be processed is not empty, the current data of the queue to be processed is transferred and stored into the unresponsive queue, and the transfer is not performed under other conditions, so that the data processing amount is reduced.
In addition to the above embodiments, in this embodiment, if the data signal is a read signal, after the step of notifying each peripheral device to execute the corresponding action, the method further includes:
and converting the data returned by the peripheral equipment into the read data path format of the AXI bus and outputting the data to the processor.
It can be understood that when the bus signal is a write channel signal, the bus signal is resolved into a RAM interface signal as a write signal, and the processor controls the peripheral device according to the write signal. When the bus signal is a read channel signal, the bus signal is analyzed into an RAM interface signal as a read signal, the processor realizes the control of peripheral equipment according to the read signal and obtains read data from the peripheral equipment, and the data can be returned to the processor through the AXI bus after being converted into a read data access format of the AXI bus.
In the above embodiments, the communication method based on the AXI bus is described in detail, and the present application also provides embodiments corresponding to the communication device based on the AXI bus. It should be noted that the present application describes the embodiments of the apparatus portion from two perspectives, one from the perspective of the function module and the other from the perspective of the hardware.
Fig. 2 is a structural diagram of an AXI bus-based communication device according to an embodiment of the present application, and as shown in fig. 2, the device includes:
a receiving module 10, configured to receive bus signals of an AXI bus, where the bus signals include address channel signals and data channel signals;
the analysis module 11 is used for analyzing the bus signal and converting the bus signal into an RAM interface signal, wherein the RAM interface signal comprises an address signal and a data signal;
a conversion module 12, configured to convert an address signal in the RAM interface signal into a reduced address adapted to each peripheral device according to an address of each peripheral device;
and the scheduling module 13 is configured to notify each peripheral device to execute a corresponding action according to the reduced address of each peripheral device and the corresponding data signal.
Since the embodiments of the apparatus portion and the method portion correspond to each other, please refer to the description of the embodiments of the method portion for the embodiments of the apparatus portion, which is not repeated here.
According to the communication device based on the AXI bus, the bus signals are received through the AXI bus, the bus signals comprise address channel signals and data channel signals, then the bus signals are analyzed, the bus signals are converted into RAM interface signals, the RAM interface signals comprise address signals and data signals, the address signals in the RAM interface signals are converted into simplified addresses adaptive to the peripheral devices according to the addresses of the peripheral devices, and finally the peripheral devices are informed to execute corresponding actions according to the simplified addresses of the peripheral devices and the corresponding data signals. Compared with the prior art, the AXI bus interface needs to be additionally developed on the peripheral equipment, which causes waste of resources. By adopting the technical scheme, after the bus signals of the AXI bus are received, the bus signals are converted into the RAM interface signals suitable for the RAM interface, so that more peripheral equipment can realize the communication with the processor through the AXI bus without additionally developing the AXI bus interface, and the waste of resources is reduced. And the total address signal is converted into a simplified address adapted to each peripheral device according to the address of each peripheral device, so that the address signal is optimized, the size of the signal is reduced, data can be stored quickly, and the release speed of the bus authority is improved.
Fig. 3 is a structural diagram of another AXI bus-based communication device according to an embodiment of the present application, and as shown in fig. 3, the device includes:
a memory 20 for storing a computer program;
the processor 21 is configured to implement the steps of the AXI bus-based communication method according to the above-described embodiment when executing the computer program.
The AXI bus-based communication device provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, or the like.
The processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The Processor 21 may be implemented in hardware using at least one of a Digital Signal Processor (DSP), a Field-Programmable Gate Array (FPGA), and a Programmable Logic Array (PLA). The processor 21 may also include a main processor and a coprocessor, where the main processor is a processor for Processing data in an awake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 21 may be integrated with a Graphics Processing Unit (GPU) which is responsible for rendering and drawing the content required to be displayed by the display screen. In some embodiments, the processor 21 may further include an Artificial Intelligence (AI) processor for processing computational operations related to machine learning.
The memory 20 may include one or more computer-readable storage media, which may be non-transitory. Memory 20 may also include high speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 20 is at least used for storing the following computer program 201, wherein after being loaded and executed by the processor 21, the computer program can implement the relevant steps of the AXI bus-based communication method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202, data 203, and the like, and the storage manner may be a transient storage manner or a permanent storage manner. Operating system 202 may include, among others, Windows, Unix, Linux, and the like. Data 203 may include, but is not limited to, address signals, data signals, reduced addresses, and the like.
In some embodiments, the AXI bus based communication device may further include a display 22, an input/output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.
Those skilled in the art will appreciate that the configuration shown in fig. 3 is not limiting to AXI bus based communication devices and may include more or fewer components than those shown.
The communication device based on the AXI bus provided by the embodiment of the application comprises a memory and a processor, wherein when the processor executes a program stored in the memory, the following method can be realized: receiving bus signals of an AXI bus, wherein the bus signals comprise address channel signals and data channel signals; analyzing the bus signal, and converting the bus signal into an RAM interface signal, wherein the RAM interface signal comprises an address signal and a data signal; according to the address of each peripheral device, converting the address signal in the RAM interface signal into a simplified address adapted to each peripheral device; and informing the peripheral equipment to execute corresponding actions according to the reduced address of the peripheral equipment and the corresponding data signal.
According to the communication device based on the AXI bus, the bus signals are received through the AXI bus, the bus signals comprise address channel signals and data channel signals, then the bus signals are analyzed, the bus signals are converted into RAM interface signals, the RAM interface signals comprise address signals and data signals, the address signals in the RAM interface signals are converted into simplified addresses adaptive to the peripheral devices according to the addresses of the peripheral devices, and finally the peripheral devices are informed to execute corresponding actions according to the simplified addresses of the peripheral devices and the corresponding data signals. Compared with the prior art, the AXI bus interface needs to be additionally developed on the peripheral equipment, which causes waste of resources. By adopting the technical scheme, after the bus signals of the AXI bus are received, the bus signals are converted into the RAM interface signals suitable for the RAM interface, so that more peripheral equipment can realize the communication with the processor through the AXI bus without additionally developing the AXI bus interface, and the waste of resources is reduced. And the total address signal is converted into a simplified address adapted to each peripheral device according to the address of each peripheral device, so that the address signal is optimized, the size of the signal is reduced, data can be stored quickly, and the release speed of the bus authority is improved.
Finally, the application also provides a corresponding embodiment of the computer readable storage medium. The computer-readable storage medium has stored thereon a computer program which, when being executed by a processor, carries out the steps as set forth in the above-mentioned method embodiments.
It is to be understood that if the method in the above embodiments is implemented in the form of software functional units and sold or used as a stand-alone product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium and executes all or part of the steps of the methods described in the embodiments of the present application, or all or part of the technical solutions. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The computer-readable storage medium provided in the embodiment of the present application receives a bus signal through an AXI bus, where the bus signal includes an address channel signal and a data channel signal, then parses the bus signal, converts the bus signal into an RAM interface signal, where the RAM interface signal includes an address signal and a data signal, converts the address signal in the RAM interface signal into a reduced address adapted to each peripheral device according to an address of each peripheral device, and finally notifies each peripheral device to execute a corresponding action according to the reduced address of each peripheral device and the corresponding data signal. Compared with the prior art, the AXI bus interface needs to be additionally developed on the peripheral equipment, which causes waste of resources. By adopting the technical scheme, after the bus signals of the AXI bus are received, the bus signals are converted into the RAM interface signals suitable for the RAM interface, so that more peripheral equipment can realize the communication with the processor through the AXI bus without additionally developing the AXI bus interface, and the waste of resources is reduced. And the total address signal is converted into a simplified address adapted to each peripheral device according to the address of each peripheral device, so that the address signal is optimized, the size of the signal is reduced, data can be stored quickly, and the release speed of the bus authority is improved.
The method, the apparatus, and the medium for communication based on the AXI bus provided in the present application are described in detail above. The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. An AXI bus-based communication method, comprising:
receiving bus signals of an AXI bus, wherein the bus signals comprise address channel signals and data channel signals;
analyzing the bus signal, and converting the bus signal into an RAM interface signal, wherein the RAM interface signal comprises an address signal and a data signal;
converting the address signal in the RAM interface signal into a reduced address adapted to each peripheral device according to the address of each peripheral device;
and notifying each peripheral device to perform a corresponding action according to the reduced address of each peripheral device and the corresponding data signal.
2. The AXI bus based communication method of claim 1, further comprising, after the step of converting the address signal into the reduced address:
associating the simplified addresses of the peripheral equipment with the corresponding data signals, and storing the simplified addresses in a queue to be processed in sequence;
further, the notifying each peripheral device of performing the corresponding action according to the reduced address of each peripheral device and the corresponding data signal includes:
and informing each peripheral device to execute corresponding actions according to the simplified addresses and the sequence of the corresponding data signals in the queue to be processed.
3. The AXI bus-based communication method of claim 2, further comprising, before the step of notifying each of the peripheral devices to perform the corresponding action according to the reduced address and the corresponding data signal in the order of the pending queue:
judging whether the peripheral equipment corresponding to the current data of the queue to be processed is in an idle state;
if yes, the step of informing the peripheral equipment to execute corresponding actions according to the simplified addresses and the sequence of the corresponding data signals in the queue to be processed is carried out;
if not, storing the simplified address of the peripheral equipment and the corresponding data signal into an unresponsive queue.
4. The AXI bus-based communication method of claim 3, further comprising:
and if the peripheral equipment corresponding to the simplified address and the corresponding data signal in the unresponsive queue is detected to be in an idle state, preferentially executing the simplified address and the corresponding data signal in the unresponsive queue.
5. The AXI bus-based communication method of claim 2, wherein, before the step of associating the reduced address of each peripheral device with the corresponding data signal and storing the reduced addresses in the queue to be processed in sequence, the method further comprises:
judging whether the queue to be processed is full;
if not, the step of associating the simplified address of each peripheral device with the corresponding data signal and storing the simplified addresses in a queue to be processed in sequence is carried out;
and if so, stopping the analysis of the bus signal.
6. The AXI bus-based communication method of claim 3, wherein before the step of storing the reduced address of the peripheral device and the corresponding data signal in an unresponsive queue, the method further comprises:
judging whether the non-response queue is not full and the queue to be processed is not empty;
if yes, entering the step of storing the simplified address of the peripheral equipment and the corresponding data signal into an unresponsive queue.
7. The AXI bus-based communication method as claimed in any one of claims 1 to 6, wherein if the data signal is a read signal, after the step of notifying each of the peripheral devices to perform the corresponding action, the method further comprises:
and converting the data returned by the peripheral equipment into a read data path format of the AXI bus and outputting the read data path format to a processor.
8. An AXI bus-based communication device, comprising:
a receiving module, configured to receive bus signals of an AXI bus, where the bus signals include address channel signals and data channel signals;
the analysis module is used for analyzing the bus signals and converting the bus signals into RAM interface signals, and the RAM interface signals comprise address signals and data signals;
the conversion module is used for converting the address signal in the RAM interface signal into a simplified address which is adapted to each peripheral device according to the address of each peripheral device;
and the scheduling module is used for notifying each peripheral device to execute corresponding actions according to the simplified address of each peripheral device and the corresponding data signal.
9. An AXI bus based communication device comprising a memory for storing a computer program;
a processor for implementing the steps of the AXI bus based communication method according to any of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, having stored thereon a computer program which, when being executed by a processor, implements the steps of the AXI bus-based communication method according to any one of claims 1 to 7.
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