CN113821465A - SRAM-based AXI (advanced extensible interface) control method and device and computer equipment - Google Patents

SRAM-based AXI (advanced extensible interface) control method and device and computer equipment Download PDF

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Publication number
CN113821465A
CN113821465A CN202111109780.XA CN202111109780A CN113821465A CN 113821465 A CN113821465 A CN 113821465A CN 202111109780 A CN202111109780 A CN 202111109780A CN 113821465 A CN113821465 A CN 113821465A
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China
Prior art keywords
interface
axi
sram
conversion module
data
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CN202111109780.XA
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Chinese (zh)
Inventor
李湘锦
张鹏
王伟良
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Shenzhen Union Memory Information System Co Ltd
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Shenzhen Union Memory Information System Co Ltd
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Priority to CN202111109780.XA priority Critical patent/CN113821465A/en
Publication of CN113821465A publication Critical patent/CN113821465A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

Abstract

The application relates to an AXI interface control method, device, computer equipment and storage medium based on SRAM, wherein the device comprises: the first interface conversion module is used for converting an AXI interface to obtain a corresponding SRAM control signal; the second interface conversion module is used for converting the quick interface to obtain a corresponding SRAM control signal; a first cache module to cache write data, write addresses, and read addresses from an AXI interface; the second cache module is used for caching data and write response from the SRAM; the interface selection module is used for selecting the interface conversion module, and the priority of the second interface conversion module is higher than that of the first interface conversion module. The invention adds a quick interface to the application scene of sensitive delay, and the delay of accessing the SRAM can be effectively reduced by adopting the quick interface.

Description

SRAM-based AXI (advanced extensible interface) control method and device and computer equipment
Technical Field
The invention relates to the technical field of solid state disks, in particular to an AXI interface control method and device based on an SRAM, a computer device and a storage medium.
Background
Computer equipment has become the most powerful practical tool for people to generate, Solid State disks are more and more popular with the price drop of the Solid State disks, NVMe SSD (Solid State Disk or Solid State Drive) is developed rapidly with the superior performance, and all computer manufacturers make the hard disks in the computer equipment into the SSD.
At present, in an SOC chip of a solid state disk, a multi-core CPU is generally used to greatly improve performance, an SRAM (Static Random-Access Memory) is shared on the multi-core CPU, and an AXI (Advanced extensible Interface) is generally used to be hung on a system bus to ensure Access of multiple masters. The AXI bus structure has strong expansibility and flexibility, but the AXI latency is large, and for an application scene emphasizing latency, if an AXI interface is adopted, the read-write performance of the solid state disk is influenced.
Disclosure of Invention
In view of the foregoing, it is desirable to provide an AXI interface control method and apparatus, a computer device, and a storage medium based on SRAM.
An SRAM-based AXI interface control apparatus, the apparatus comprising:
the first interface conversion module is used for converting an AXI interface to obtain a corresponding SRAM control signal;
the second interface conversion module is used for converting the quick interface to obtain a corresponding SRAM control signal;
a first cache module to cache write data, write addresses, and read addresses from an AXI interface;
the second cache module is used for caching data and write response from the SRAM;
the interface selection module is used for selecting the interface conversion module, and the priority of the second interface conversion module is higher than that of the first interface conversion module.
In one embodiment, the interface selection module is further configured to:
and if the transmitted data volume is small, preferentially selecting the fast interface to transmit data, and if the transmitted data volume is large, transmitting the data through the AXI interface.
In one embodiment, the interface selection module is further configured to:
and when a second interface conversion module is selected, the transmission of an AXI interface is blocked, and the transmission is continued through the AXI interface after the transmission of the fast interface is finished.
In one embodiment, the AXI interface comprises: a write data channel, a write address channel, a read data channel, and a write response channel.
An AXI interface control method based on SRAM, which is applied to any one of the AXI interface control apparatuses based on SRAM, comprising:
acquiring a data read-write request sent by a host;
selecting a corresponding interface conversion module according to the data volume of the data read-write request, wherein the priority of the second interface conversion module is higher than that of the first interface conversion module; the first interface conversion module is used for converting an AXI interface to obtain a corresponding SRAM control signal; the second interface conversion module is used for converting the quick interface to obtain a corresponding SRAM control signal;
caching write data, a write address and a read address from an AXI (advanced extensible interface) through a first cache module;
and the second cache module is used for caching data and write response from the SRAM.
In one embodiment, the step of selecting the corresponding interface conversion module according to the data size of the data read-write request, where the priority of the second interface conversion module is higher than that of the first interface conversion module, further includes:
and if the transmitted data volume is small, preferentially selecting the fast interface to transmit data, and if the transmitted data volume is large, transmitting the data through the AXI interface.
In one embodiment, the method further comprises:
and when a second interface conversion module is selected, the transmission of an AXI interface is blocked, and the transmission is continued through the AXI interface after the transmission of the fast interface is finished.
In one embodiment, the AXI interface comprises: a write data channel, a write address channel, a read data channel, and a write response channel.
A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of any of the above methods when executing the computer program.
A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of any of the methods described above.
In the method, the device, the computer equipment and the storage medium for controlling the AXI interface based on the SRAM, the priority of the second interface conversion module is higher than that of the first interface conversion module by selecting the corresponding interface conversion module according to the data volume of the data read-write request; the first interface conversion module is used for converting an AXI interface to obtain a corresponding SRAM control signal; the second interface conversion module is used for converting the fast interface to obtain a corresponding SRAM control signal. The invention adds a quick interface to the sensitive delay application scene on the basis of the original architecture, realizes high performance and low delay through the design scheme of the two interfaces, and can effectively reduce the delay of accessing the SRAM by adopting the quick interface for the sensitive delay application scene.
Drawings
FIG. 1 is a block diagram of an SRAM-based AXI interface control apparatus in one embodiment;
FIG. 2 is a diagram illustrating the transmission of SRAM-based AXI interface control signals in one embodiment;
FIG. 3 is a flow diagram illustrating an SRAM-based AXI interface control method in one embodiment;
FIG. 4 is a diagram illustrating an internal structure of a computer device according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In an SOC chip of a solid state disk, a multi-core CPU is generally used to greatly improve performance, an SRAM (Static Random-Access Memory) is shared on the multi-core CPU, and an AXI (Advanced extensible Interface) is generally used to be hung on a system bus to ensure Access of multiple masters. The AXI bus structure has strong expansibility and flexibility, but the AXI latency is large, and for an application scene emphasizing latency, if an AXI interface is adopted, the read-write performance of the solid state disk is influenced.
Based on the method, the invention provides the SRAM-based AXI interface control method, aiming at the defect of access delay time of the AXI SRAM, and a quick interface is added in an application scene of sensitive delay. Such an SRAM design will include two interfaces, AXI and a simple fast interface to achieve high performance and low latency, and for sensitive latency application scenarios, the latency of accessing the SRAM may be reduced by using the fast interface.
In one embodiment, as shown in fig. 1, there is provided an SRAM-based AXI interface control apparatus, the apparatus comprising:
a first interface conversion module 101, configured to convert an AXI interface to obtain a corresponding SRAM control signal;
a second interface conversion module 102, configured to convert the fast interface to obtain a corresponding SRAM control signal;
a first cache module 103 for caching write data, write addresses, and read addresses from an AXI interface;
a second cache module 104 for caching data from the SRAM and write responses;
and the interface selection module 105 is used for selecting an interface conversion module, and the priority of the second interface conversion module is higher than that of the first interface conversion module.
Specifically, referring to a schematic transmission diagram of the AXI interface control signal based on the SRAM shown in fig. 2, in the present solution, a fast _ to _ user _ logic module is added on the basis of the conventional design, and the fast interface is converted by the fast _ to _ user _ logic module to obtain the control signal of the SRAM. The following describes the respective blocks and signals shown in fig. 2 as follows:
in one embodiment, the AXI interface includes: a write data channel, a write address channel, a read data channel, and a write response channel.
Specifically, the AXI interface has 5 channels in total: wdata (write data channel), awaddr (write address channel), araddr (read address channel), rddata (read data channel), bresp (write response channel).
The axi _ to _ user _ logic module is used for converting an axi interface to obtain an SRAM control signal.
The fast _ to _ user _ logic module is used for converting the fast interface to obtain the control signal of the SRAM.
The cmd fifo module is used to cache write data/write addresses, or read addresses, from the AXI.
The resp fifo module is used for caching data from the SRAM and writing response.
real SRAM: a real SRAM.
In one embodiment, the interface selection module is further to: and if the transmitted data volume is small, preferentially selecting the fast interface to transmit data, and if the transmitted data volume is large, transmitting the data through the AXI interface.
In one embodiment, the interface selection module is further to: and when a second interface conversion module is selected, the transmission of an AXI interface is blocked, and the transmission is continued through the AXI interface after the transmission of the fast interface is finished.
The arbit module shown in fig. 2 may be referred to, specifically, the arbit module selects whether the AXI or the fast interface is selected, the fast interface has the highest priority, the AXI is blocked for transmission, and the AXI continues to complete transmission after the fast interface is transmitted. Because fast interfaces are typically used for low latency, small data volume transfers, AXI transfers are used if the data volume is large.
Further, the signals in fig. 2 are illustrated as follows:
AXI docks signal m of SRAM (signal with up being accelerated).
mdata/mdata _ up: writing data; mstrb: a write select signal; maddr: a write address; msize: the write data valid bit width.
mburst/mburst _ up: whether to write continuously; mlen: the length is written continuously.
svalid/sdata/srep/svalid _ up/sdata _ up/srep _ up: data returned from the SRAM, and a valid signal.
fast _ ram is a control signal of the fast interface.
f _ ram: and after obtaining the control right grasping signal returned by the arbit module, generating a related read-write SRAM signal.
f _ control _ right the fast interface gets access to the SRAM.
a _ control _ right: the AXI interface gets access to the SRAM.
and abt _ ram, cmd or write data after passing through the arbit module, and read data from the SRAM.
In the above embodiment, the priority of the second interface conversion module is higher than that of the first interface conversion module by selecting the corresponding interface conversion module according to the data size of the data read-write request; the first interface conversion module is used for converting an AXI interface to obtain a corresponding SRAM control signal; the second interface conversion module is used for converting the fast interface to obtain a corresponding SRAM control signal. According to the scheme, on the basis of an original framework, a quick interface is added in a sensitive delay application scene, high performance and low delay are achieved through the design scheme of the two interfaces, and the delay of accessing the SRAM can be effectively reduced by adopting the quick interface in the sensitive delay application scene.
In one embodiment, as shown in fig. 3, an SRAM-based AXI interface control method is provided, which is applicable to the SRAM-based AXI interface control apparatus, and includes:
step 302, acquiring a data read-write request sent by a host;
step 304, selecting a corresponding interface conversion module according to the data size of the data read-write request, wherein the priority of the second interface conversion module is higher than that of the first interface conversion module;
step 306, the first interface conversion module is used for converting the AXI interface to obtain a corresponding SRAM control signal;
308, the second interface conversion module is used for converting the fast interface to obtain a corresponding SRAM control signal;
step 310, caching write data, a write address and a read address from an AXI interface through a first cache module;
step 312, the second cache module is used for caching the data from the SRAM and the write response.
In one embodiment, the AXI interface includes: a write data channel, a write address channel, a read data channel, and a write response channel.
In one embodiment, the step of selecting the corresponding interface conversion module according to the data size of the data read-write request, where the priority of the second interface conversion module is higher than that of the first interface conversion module further includes: and if the transmitted data volume is small, preferentially selecting the fast interface to transmit data, and if the transmitted data volume is large, transmitting the data through the AXI interface.
In one embodiment, the method further comprises: and when a second interface conversion module is selected, the transmission of an AXI interface is blocked, and the transmission is continued through the AXI interface after the transmission of the fast interface is finished.
Specifically, with reference to the schematic transmission diagram of the AXI interface control signal based on the SRAM shown in fig. 2, the read-write process under different conditions is described as follows:
first, in case of AXI-only read-write (always get operational authority):
writing: through axi _ to _ user _ logic module, the data and command are merged to go through cmd fifo module (write OK into resp fifo at the same time), and then through the arbit module, write into real SRAM.
Reading: the read command passes through the AXI _ to _ user _ logic module, the cmd fifo module is read, then the arbit module is used for sending the read command to the real SRAM, the read data is output, then the read command passes through the arbit module and is written into the resp fifo module, and finally the read command is output through the AXI data reading channel.
Second, in case of fast interface read-write only (operational authority is always obtained):
writing: and writing the write command and the write data into the real SRAM through the arbit module by the fast _ to _ user _ logic module.
Reading: after passing through the axi _ to _ user _ logic module, the read command passes through the arbit module, the read command is sent to the real SRAM, after the read data is output, the read command passes through the arbit module and is output through the fast data reading channel.
Third, in the case of AXI/express interface hybrids:
the fast interface has the highest priority, block transmission of the AXI is stopped, and the AXI continues to finish transmission after the fast interface is transmitted. The fast interface is generally used for low-latency and small-data-volume transmission, and if the data volume is large, AXI transmission is adopted.
It should be understood that although the various steps in the flow charts of fig. 1-3 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 1-3 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternating with other steps or at least some of the sub-steps or stages of other steps.
In one embodiment, a computer device is provided, the internal structure of which may be as shown in FIG. 4. The computer apparatus includes a processor, a memory, and a network interface connected by a device bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The nonvolatile storage medium stores an operating device, a computer program, and a database. The internal memory provides an environment for the operation device in the nonvolatile storage medium and the execution of the computer program. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement an SRAM-based AXI interface control method.
Those skilled in the art will appreciate that the architecture shown in fig. 4 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided, comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the above method embodiments when executing the computer program.
In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the above respective method embodiments.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. An SRAM-based AXI interface control apparatus, the apparatus comprising:
the first interface conversion module is used for converting an AXI interface to obtain a corresponding SRAM control signal;
the second interface conversion module is used for converting the quick interface to obtain a corresponding SRAM control signal;
a first cache module to cache write data, write addresses, and read addresses from an AXI interface;
the second cache module is used for caching data and write response from the SRAM;
the interface selection module is used for selecting the interface conversion module, and the priority of the second interface conversion module is higher than that of the first interface conversion module.
2. The SRAM-based AXI interface control apparatus of claim 1, wherein the interface selection module is further to:
and if the transmitted data volume is small, preferentially selecting the fast interface to transmit data, and if the transmitted data volume is large, transmitting the data through the AXI interface.
3. The SRAM-based AXI interface control apparatus of claim 2, wherein the interface selection module is further to:
and when a second interface conversion module is selected, the transmission of an AXI interface is blocked, and the transmission is continued through the AXI interface after the transmission of the fast interface is finished.
4. The SRAM-based AXI interface control apparatus of claim 1, wherein the AXI interface comprises: a write data channel, a write address channel, a read data channel, and a write response channel.
5. An SRAM-based AXI interface control method applied to the SRAM-based AXI interface control apparatus according to any one of claims 1 to 4, comprising:
acquiring a data read-write request sent by a host;
selecting a corresponding interface conversion module according to the data volume of the data read-write request, wherein the priority of the second interface conversion module is higher than that of the first interface conversion module; the first interface conversion module is used for converting an AXI interface to obtain a corresponding SRAM control signal; the second interface conversion module is used for converting the quick interface to obtain a corresponding SRAM control signal;
caching write data, a write address and a read address from an AXI (advanced extensible interface) through a first cache module;
and the second cache module is used for caching data and write response from the SRAM.
6. The method of claim 5, wherein the selecting the corresponding interface conversion module according to the data size of the data read/write request, the second interface conversion module having a higher priority than the first interface conversion module further comprises:
and if the transmitted data volume is small, preferentially selecting the fast interface to transmit data, and if the transmitted data volume is large, transmitting the data through the AXI interface.
7. The SRAM-based AXI interface control method of claim 6, further comprising:
and when a second interface conversion module is selected, the transmission of an AXI interface is blocked, and the transmission is continued through the AXI interface after the transmission of the fast interface is finished.
8. The SRAM-based AXI interface control method of claim 5, wherein the AXI interface comprises: a write data channel, a write address channel, a read data channel, and a write response channel.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps of the method according to any of claims 5 to 8 are implemented by the processor when executing the computer program.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 5 to 8.
CN202111109780.XA 2021-09-18 2021-09-18 SRAM-based AXI (advanced extensible interface) control method and device and computer equipment Pending CN113821465A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114328350A (en) * 2021-12-23 2022-04-12 山东云海国创云计算装备产业创新中心有限公司 Communication method, device and medium based on AXI bus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114328350A (en) * 2021-12-23 2022-04-12 山东云海国创云计算装备产业创新中心有限公司 Communication method, device and medium based on AXI bus

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