JP3425885B2 - Memory access processor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access device, and more particularly, it relates to a memory access device preferably used for data transfer between nodes.

[0002]

2. Description of the Related Art In a node having a plurality of processors and a shared memory, since the instruction processing performance in the node is high, high data transfer performance is required even in the data transfer between the nodes.

The data transfer performance between the nodes can be improved by increasing the transfer rate by the machine cycle and expanding the data width of the transfer data to increase the amount of data that can be transferred at one time. When the transfer data width is expanded to improve the data transfer performance between the nodes, it is necessary to improve the memory transfer performance within the node as well as the transfer data width between the nodes.

An example of a data transfer method between such nodes is disclosed in Japanese Patent Laid-Open No. 5-108581. This publication describes a device in which a distributed memory of a multiprocessor system is used as one node. Here, when the inter-node data transfer control unit provided in the processor accesses the distributed memory owned by the processor, the sub-array data that is a part of the two-dimensional array data can be issued by one transfer instruction. I try to access it. That is, the transfer start address (B), the first
Element distance (D1) and second element distance (D2)
With respect to the sub-array data defined by, the memory address is sequentially generated for each element forming the sub-array data, and the memory access request is issued to transfer the data.

[0005]

However, in this transfer method, the transfer order may not be guaranteed when the data width is large, for example, when a plurality of elements are transferred in parallel in a memory by 2-distance transfer.

That is, when there are a plurality of elements having the same address in one memory request, the access order is not guaranteed between these elements, and the preceding memory access element overtakes the memory access element issued later. There is. When such overtaking occurs between elements having the same address, the element preceding the address where the following element should have been originally written will be overwritten, and the memory operation expected by the software will not be performed. There is a problem.

The present invention solves this problem and guarantees a transfer order between a plurality of elements having the same address when a plurality of elements are memory-accessed in parallel in a node-to-node transfer so that the memory operation is correct. The present invention provides a memory access processing device adapted to be performed.

[0008]

In order to solve the above-mentioned problems, a memory access processing device of the present invention is a memory access processing device for performing memory access to transfer data composed of a plurality of data elements by one transfer instruction. In the above, the processing device is provided with an order assurance means for performing memory access for a plurality of transfer data elements existing in one memory access request and having the same address in a predetermined order.

As described above, the memory access processing device of the present invention guarantees the order of transfer data elements existing in one memory access request and having the same address, and the succeeding element precedes these elements. By not accessing the memory prior to the element, the memory operation expected by the software can be realized accurately.

Further, the memory access device of the present invention divides the transfer data into data blocks consisting of a plurality of transfer data elements, performs a memory access for each data block, and transfers among the transfer data elements having the same address. The order guarantee is performed by waiting for the end of the memory access of the data block including the preceding data element and performing the memory access of the data block including the subsequent data element.

By performing the transfer for each block, it is possible to improve the data transfer performance, wait for the memory access end of the data block including the preceding element of the transfer data elements having the same address, and wait for the subsequent data. By performing the memory access of the data block including the element, the order guarantee between the data can be preferably performed.

Further, in the memory access device of the present invention, the transfer of the data is performed by the transfer start address (B) of the transfer data.
, A first distance between elements (D1), a second distance between elements (D2), a first number of elements (L1), and a second distance transfer defined by a second number of elements (L2) The data block is composed of transfer data elements determined by the first inter-element distance and the first number of elements.

By setting the transfer format to be two-distance transfer, data can be transferred more efficiently.

Also, the memory access device of the present invention comprises the same address detection means for detecting whether or not there are a plurality of data transfer elements having the same address in one memory access request, and the same address detection means. Is to guarantee the order only when it detects the presence of a plurality of data transfer elements having the same address during one memory access.

If the order guarantee is performed for all memory requests, the memory transfer performance is deteriorated. Therefore, in the preferred embodiment of the present invention, the same address exists between the elements of the data to be transferred in one memory request. It is determined whether or not to perform the order guarantee only when the presence of the same address is detected.

Further, in the memory access device of the present invention, the same address detecting means is provided with the first inter-element distance and the second inter-element distance.
(1) The first inter-element distance is smaller than the second inter-element distance (| D1 | <| D2 |), and D1 × (L1-1) is realized. The second inter-element distance (D2) is smaller than the area to be defined; (2) the first inter-element distance is larger than the second inter-element distance (| D1 |> | D2 |), D2 × ( L2-1) the first inter-element distance (D1) is smaller than the area realized; or (3) the first inter-element distance is equal to the second inter-element distance (| D1 | = | D2 |) case; is characterized in that the order guarantee is performed.

In this way, by detecting the same address approximately by area comparison, the amount of hardware required for detecting the same address can be suppressed.

Further, it is preferable that the order guarantee is performed only during a store operation to prevent deterioration of processing functions. This is because the same data is read even if overtaking occurs between elements at the time of load access, so order guarantee is not necessary.

Further, the memory access processing device of the present invention is such that a memory access issue management unit for issuing memory access for an element to be transferred and a memory access issued by the issue management unit by monitoring the memory access state of transfer data. A memory access state management unit that detects the end of the memory access and notifies the issuance management unit, and when the order guarantee is performed, the memory access state management of the end of the memory access of the data block including the preceding element is performed. After confirming by the section, the memory access issue management section issues the memory access of the data block including the subsequent element.

With such a configuration, it is possible to preferably realize an access processing device in which overtaking between elements does not occur and the memory access function is not deteriorated.

[0021]

1 is a diagram showing a configuration of an information processing apparatus to which a memory access processing apparatus according to the present invention can be suitably applied. The information processing device 1 includes a plurality of nodes 22-0 to 22-n and an internode crossbar switch 21 that connects these nodes to each other.

Each node 22 has a plurality of processors 23,
Inter-node control unit (RCU) 24 that processes data transfer between these nodes, and shared memory 25 connected to all processors 23 and inter-node control unit (RCU) 24
And with.

When a data transfer request is sent from any processor 23 in any node to the RCU 24 in that node, data transfer between the nodes is activated. For example, the shared memory 25-0 of the node 22-0
To transfer the data in the shared memory 25-0 of the node 22-n, the RCU 24-0 receives the data transfer request from the processor 23, reads the data to be transferred from the shared memory 25-0, and then sends the data to the crossbar switch. 21.

The crossbar switch 21 switches the crossbar according to the destination node (node 22-n) of the transferred data, and transfers the data to the transfer destination node 22-n. In the node 22-n, the transfer data sent from the crossbar switch 21 is received by the RCU 24-n and written in the shared memory 25-n, whereby the data transfer between the nodes is realized.

FIG. 2 is a diagram showing a detailed configuration of the inter-node control unit RCU24. As described above, when performing inter-node transfer, the transfer performance deteriorates unless the transfer speed between the nodes is the same as the transfer data write speed or the memory read speed. Therefore, usually, the data transfer performance between nodes is improved by expanding the data width of the data transferred at one time. In the example shown in FIG. 2, 8 bytes is set as one element, and data having a data width of 4 elements is accessed at one time.

As shown in FIG. 2, the RCU 24 provided in each node receives a transfer request sent from another node via the crossbar switch 21 and controls transfer. The RCU 24 includes a transfer control unit 31, a memory access control unit 32, a data reception buffer 33, a memory address / store data crossbar 34, a load data crossbar 35, and a data transmission buffer 36.

When receiving the inter-node transfer data, the transfer control unit 31 receives a transfer request from another node via the crossbar switch 21, issues a memory access request, and sends it to the memory access control unit 32. The memory access control unit 32 generates a memory address based on this, and sends it to the memory address / store data crossbar 34.

On the other hand, the data reception buffer 33 temporarily stores the data transferred from another node via the internode crossbar switch 31. Here, a plurality of elements (in this example, four transfer width elements) can be stored simultaneously. The data stored in the data reception buffer 33 is sent to the memory address / store crossbar 34.

Memory address / store data crossbar 3
In 4, the data (4 elements) sent from another node via the data reception buffer 33 and the memory addresses corresponding to these 4 elements sent from the memory access control unit 32 are connected to the shared memory 25 by the crossbar. Forward to port. The connection port is interleaved with the memory address indicated by each element, and is connected to a predetermined memory position of the shared memory 25. The transfer by the crossbar is controlled by the memory access control unit 32.

The shared memory 25 stores the inter-node received data by writing the data in the address position sent from the memory address / store crossbar 34.

When transmitting data to another node, the inter-node data transfer control unit 31 receives a data transmission request from any one of the processors 23 in the node 22 and sends a memory access control unit 32 a memory. Issue a load request. Memory access control unit 32
Generates a load address for four elements from this memory load request to generate a memory address / store crossbar 3
Send to 4. The memory address / store crossbar 34 sends this address to a port connected to a predetermined position of the shared memory 25, the shared memory 25 reads data from the memory in accordance with the sent address, and the read address is stored in the load data crossbar 35. Send to connection port.

The load data crossbar 35 sends this data to the data transmission buffer 36 under the control of the memory access control unit 32, and the data transmission buffer 36 receives this data under the control of the internode data transfer control unit 31. Is transmitted to the crossbar switch 21 between nodes. The data transmission is completed by the crossbar switch 21 transferring this data to the designated transfer destination node.

FIG. 3 is a diagram showing a detailed configuration of the memory access control unit 32 and the memory address / store data crossbar 34.

As shown in FIG. 3, the memory access controller 32 includes the same address detector 41 and the issue manager 42.
And address generation units 43a to 43d, a memory access state monitoring unit 45, and a contention arbitration unit 46. on the other hand,
The memory address / data crossbar 34 includes a first register 51a to 51d, a selection circuit 52a to 52d, and a second register.
And registers 53a to 53d.

The same address detection unit 41 receives the memory access information 61 from the inter-node data transfer control unit 31, and by area comparison described later, there is a plurality of data elements accessing the same address in one memory request. It is detected whether or not to do.

The memory access information 61 includes a transfer start address (B) of transfer data, a first inter-element distance (D1),
It comprises a second inter-element distance (D2), a first element number (L1) and a second element number (L2).

When the same address detection unit 41 detects that there are a plurality of elements that access the same address in one request, the same address detection unit 41 notifies the issue management unit 42 of the same address signal. The issue management unit 42 issues a memory access instruction in block units, with an element group represented by the first inter-element distance D1 and the first element number L1 as one block. The same address detection unit 41 detects that the same address exists for a plurality of elements, and the issue management unit 4
4 is notified, the issue management unit 44 does not perform the memory access of the next block and waits until the memory access of all the issued elements is completed every time the memory access of one block is completed.

The memory access state monitoring unit 45 monitors whether or not all the memory accesses issued to the shared memory 25 are completed by receiving the access end signal 62 from the memory 25, and the memory access status of all the elements is changed. Memory access end signal 6 when access is completed
2 is notified to the issue management unit 42.

When the issuance management unit 42 confirms that there are a plurality of elements that access the same address in one request, the succeeding blocks are notified until the memory access end signal 62 for one block is notified. Since the memory access is not performed, the following element does not pass the preceding element among the plurality of elements accessing the same address and the memory access order is guaranteed. Note that if the same address is not detected in one request, there is no problem even if there is an overtaking between elements. Therefore, memory access is issued sequentially without waiting until the memory access of the preceding block is completed. I am trying to improve.

The issue management unit 42 includes an address generation circuit 43.
a is the base address (B ') of each element, 43b is the inter-element distance (D), 43c is the inter-element distance x 2 (2D),
The inter-element distance x3 (3D) is sent to 43d, and each address generation circuit 43a to 43d generates addresses of four elements that access the memory at one time based on this information and transfers them to the memory address / store data crossbar 34. To do.

Here, in the case of a store request, the addresses generated here from the address generation circuits 43a to 43d and the data of each element from the data reception buffer 33 via the signal lines 81 to 84 are memory addresses. /
It is sent to the store data crossbar 34, and these addresses and data are stored in the first registers 51a and 51b. The stored address and data are stored in the contention arbitration circuit 46.
Is arbitrated by the second register 53a-5 and transferred to the port selected by the port selection circuit 52a-52d.
It is stored in 3d. The address and data stored in the second register are sent to the shared memory 25 via the signal lines 91 to 94 for each port, and the data is written in the corresponding address position.

In the case of a load request, no data is sent, only the address is sent to the shared memory 25, the data at this address position is read and sent to the load data crossbar 35.

Overtaking between elements occurs because the memory address / store data crossbar 34 is processing a plurality of elements in parallel. That is, since the path for memory access differs for each element depending on the input port of the crossbar 34, there is a case where the element issued later overtakes the memory access than the preceding memory access element.
Therefore, if the memory access of the first block and the second block is continuously performed, the subsequent element may access the memory first among the elements configuring these blocks. When an element overtaking occurs between elements having the same address, the element of the preceding block is overwritten at the address where the element of the subsequent block is originally supposed to be written, and the expected memory access operation is not performed.

In order to solve this problem, in the present embodiment, when it is confirmed that the same address exists between blocks, the memory access of the preceding block is waited for and the memory access of the succeeding block is performed. Ensures the order of memory access. As described above, if the same address is not detected between the blocks, the memory access command for the first block is issued and the memory access commands for the second block are issued consecutively without performing this waiting operation. By doing so, the processing efficiency is improved.

Next, a memory access waiting operation in the embodiment of the present invention will be described by taking a 2-distance transfer as an example. FIG. 4 and FIG. 5 are diagrams showing examples of data blocks transferred by 2-distance transfer. In the example shown in FIG. 4, the transfer data includes the transfer start address (B) of the transfer data, the first inter-element distance (D1: 8 bytes in this example), and the number of elements to be transferred according to the first inter-element distance ( L1: 4 elements in this example), second inter-element distance (D
2: 64 bytes in this example) and the number of elements to be transferred according to the second inter-element distance (L2: 4 elements in this example), and these are all defined by B, D1, D2, L1, and L2. Elements are transferred in a batch. Here, the address range indicated by the first distance between elements and the first number of elements is 1
The second inter-element distance D2 is the distance between the head elements of each block, and the number of elements transferred by the second inter-element distance is the number of blocks transferred by this second inter-element distance. Is. In FIG. 4, B, D1,
The range of the data transferred by D2, L1, and L2 is the element surrounded by the bold line.

In this example, the transfer data is D1 and L1.
Block indicated by, ie, e00, e01, e0
The first block consisting of four elements 2, d03, e04,
a second block consisting of elements e05, e06, e07,
It is composed of four blocks, a third block composed of elements e08, e09, e10, and e11, and a fourth block composed of elements e12, e13, e14, and e15, unless D1 is 0. Each element never accesses the same address. Therefore, with this setting, memory access can be performed without being aware of the above-mentioned overtaking between elements.

On the other hand, in the example shown in FIG. 5A, the first inter-element distance D1 (8 bytes) and the second inter-element distance D2 (1
6 bytes), the first number of elements L1 (4 elements), and the second number of elements L2 (5 blocks) are set, and 2-distance transfer is performed. Here, as shown in FIG. 5B, the element 02
And element 04, element 03 and element 05, element 04 and element 0
6. ． ． The element 15 and the element 17 have the same address.

When transfer data including a plurality of elements having the same address is stored in the memory by using, for example, a crossbar capable of simultaneously processing four elements, the elements 02 and 04 having the same address are input. Different signal lines are input (input timings are different), but at the time of output, the elements 02 and 04 are output to the same output port. At this time, for example, when the memory is bank busy, the element 02 and the element 04 try to output to the same output port at the same timing. In this case,
Normally, the elements to be arbitrated and output are decided,
When the priority order is determined using round robin control or the like to increase the transfer throughput, the element 04 may be output to the memory before the element 02. In such a case, since the memory access is not performed in the order of the element numbers, the data of the element 04 having a large element number should originally remain in the memory, but the data of the element 02 overtaken by the element 04 remains in the memory. Therefore, the memory operation expected by the software is not executed.

Thus, the settings shown in FIG. 5 (first inter-element distance D1: 8 bytes, second inter-element distance D2: 16 bytes, first element number L1: 4 elements, second element number L2: 5 blocks) 2), the same address exists in one memory access, and overtaking occurs between elements having the same address. In this embodiment, in order to prevent the occurrence of this overtaking, the memory access of the subsequent block is performed after waiting for the end of the memory access of the preceding block.

That is, in the example shown in FIG. 5, element 00-
03, element 04-07, element 08-11, element 12-1
5, the element 16-19 and the element group (block) delimited by the second inter-element distance D2 are used as a processing unit for waiting, and the first group (element 00-03) is first memory-accessed to The memory access instruction of the second group (element 04-07) is issued after the end of access (the same applies to the third, fourth, and fifth groups below). By performing this waiting, the memory access processing of the element 02 of the first group is not overtaken by the memory access processing of the element 04 of the second group (hereinafter, the same applies to the third, fourth, and fifth groups), Order guarantees can be made.

However, if this queuing process is performed, the memory access of the next block is not performed until the memory access of the preceding block is completed, which is disadvantageous in terms of memory access performance. Therefore, in the device of the present invention,
It is detected whether a plurality of elements among the elements transferred at the same time have the same address, and the above-mentioned waiting process is performed only when there is an element having the same address.

FIG. 6 is a diagram for explaining the same address detecting operation in the same address detecting circuit 41 shown in FIG. When performing 2-distance data transfer, the transfer start address B, the first inter-element distance D1, the second inter-element distance D2, and the first element number L from the inter-node data transfer control unit 31.
The memory access request 61 in which the first and second element numbers L2 are set is sent to the same address detection circuit 41.
The same address detection circuit 41 compares the absolute values of the first inter-element distance D1 and the second inter-element distance D2, and further performs the following area comparison to determine whether or not there is an element having the same address. It is detecting.

Here, in the case of | D1 | <| D2 |, D is larger than the area realized by D1 × (L1-1).
If 2 is large, multiple elements will not access the same address. In this case, the same address detection unit 41
Sends a request to the issue management unit 42 without the same address. In response to this, the issue management unit 42 sequentially issues memory accesses without performing the order guarantee operation for each block during data transfer.

In the case of | D1 | <| D2 |, and if D2 is smaller than the area realized by D1 × (L1-1), there is a possibility that a plurality of elements may address the same address. The same address detection circuit 41 reports to the issue management unit 42 that the same address exists. In response to this report, the issue management unit 42 waits for the processing end signal of the state monitoring unit 16 for each block and issues a request for the subsequent block to guarantee the order.

Similarly, in the case of | D1 | <| D2 |, D is larger than the area realized by D2 × (L2-1).
When 1 is large, a plurality of elements do not access the same address, and when | D1 | <| D2 |, D is larger than the area realized by D2 × (L2-1).
If 1 is small, the same address may be accessed. Therefore, according to the size of D1 with respect to the area realized by D2 × (L2-1), the issue management unit 1012 is notified of the presence or absence of the same address.

If | D1 | = | D2 |, the same address is accessed, so the issue management unit 42 is notified that the same address is present.

As described above, by detecting the same address approximately by area comparison, the amount of hardware required for the detection can be reduced.

In the load access, the same data is read even if there is an overtaking among the elements and no problem occurs. Therefore, in this example, the order guarantee operation is performed only during the store operation to the shared memory. I have to.
The issue management unit 42 determines whether the operation is a load operation or a store operation, and controls whether or not to guarantee the order.

As described above, by performing the order guarantee only during the memory store, it is possible to minimize the deterioration of the memory transfer performance due to the order guarantee operation.

[0060]

As described above, in the memory access processing device of the present invention, the order of memory access is guaranteed for transfer data elements as necessary.
Even when there are a plurality of elements having the same address in one memory access request, the expected memory operation can be correctly performed. In addition, since it is detected whether or not there are a plurality of elements having the same address and the order guarantee is performed even when such an element exists, the data transfer performance is significantly deteriorated. There is no. Furthermore, since the area comparison is used to approximately detect whether or not there are a plurality of elements having the same address, the amount of hardware required to guarantee the order can be suppressed.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an information processing device to which a memory access processing device of the present invention is applied.

FIG. 2 is a diagram showing a detailed configuration of an internode control unit of the information processing apparatus shown in FIG.

3 is a diagram showing a detailed configuration of a memory access control unit and a memory address / data crossbar of the information processing apparatus shown in FIG.

FIG. 4 is a diagram showing an example of a data configuration transferred by 2-distance transfer.

FIG. 5 is a diagram showing another example of a data structure to be transferred by 2-distance transfer.

FIG. 6 is a diagram for explaining detection of the same address in the device of the present invention.

[Explanation of symbols]

1 Information processing equipment 21 Crossbar switch 22 nodes 23 processors Control unit between 24 nodes 25 shared memory 31 Transfer control unit 32 memory access controller 33 data receive buffer 34 Memory address / store data crossbar 35 Load Data Crossbar 36 data transmission buffer 41 Same address detector 42 Issue Management Department 43a to 43d Address generation unit 45 Memory access status monitor 46 Competitive Mediation Department 51, 53 register 52 selection circuit 61 Memory access information 62 Memory access end signal

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Claims (4)

(57) [Claims] 1. Transfer data consists of multiple transfer data elements.
Divided into data blocks, and make a memo for each data block.
In the memory access processing device that performs re-access , data transfer is performed by using a transfer start address (B) of transfer data,
The first inter-element distance (D1) and the second inter-element distance (D
2), the first number of elements (L1), and the second number of elements (L1)
2) Performed by 2 distance transfer specified in and
The data block includes the first inter-element distance and the first element.
It is composed of transfer data elements that are determined by the number and the memory access processing device.
Need multiple data transfers with the same address during the quest
Identical address detecting means for detecting whether or not a prime exists
And the same address detection means is accessing one memory
The existence of multiple data transfer elements with the same address
Transfer data having the same address when detected
A data block containing the preceding data element of the elements
Waits for the end of the memory access of the
And a sequence assurance means for controlling to perform lock memory access , wherein the same address detecting means detects the same address.
The memory access device is characterized in that the above is approximately performed by area comparison . In the memory access device according to claim 1, wherein the same address detecting means compares the absolute value of the distance between the first element between the distance and the second element, (1) the first When the inter-element distance of 1 is smaller than the second inter-element distance (| D1 | <| D2 |) and the second inter-element distance (D2) is smaller than the area realized by D1 × (L1-1) (2) The first inter-element distance is larger than the second inter-element distance (| D1 |> | D2 |), and the first inter-element distance from the area realized by D2 × (L2-1) ( D1) is small; or (3) when the first inter-element distance and the second inter-element distance are equal (| D1 | = | D2 |); the same address is set in one memory access request. All memory, wherein a plurality of transfer data with is determined to exist Scan apparatus. 3. The memory access processing device according to claim 1 or 2, wherein the order guarantee operation is performed only during a store operation. 4. The memory access processing device according to claim 1, wherein the device further issues a memory access issue management unit that issues memory access for an element to be transferred, and memory access for transfer data. A memory access state management unit that monitors the state and detects that the memory access issued by the issuance management unit has ended, and notifies the issuance management unit of the preceding, and in order to guarantee the order, Memory access characterized in that the memory access issue management unit issues a memory access of a data block including a subsequent element after the memory access state management unit confirms the end of the memory access of the included data block. Processing equipment.