JP2000267927A - Memory access processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory access processor capable of guaranteeing the order of transfer among plural elements having the same address in the case of accessing the memories of plural elements in parallel. SOLUTION: The memory access processor for accessing the memories of transfer data constituted of plural data elements by a transfer instruction is provided with order guarantee means (41, 42, 45) capable of executing the memory access of plural transfer data elements included in a memory access request and having the same address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory access device, and more particularly, to a memory access device suitably used for data transfer between nodes.

[0002]

2. Description of the Related Art A node having a plurality of processors and a shared memory has a high instruction processing performance in the node, so that a high data transfer performance is also required in data transfer between nodes.

[0003] The data transfer performance between nodes can be improved by increasing the transfer speed by machine cycles and by increasing the data width of the transfer data to increase the amount of data that can be transferred at one time. When the transfer data width is increased to improve the data transfer performance between nodes, it is necessary to increase the transfer data width between nodes and also to improve the memory transfer performance in the node.

An example of such a data transfer method between nodes is disclosed in Japanese Patent Laid-Open No. Hei 5-108581. This publication describes an apparatus in which a distributed memory of a multiprocessor system is used as one node. Here, when the inter-node data transfer control unit provided in the processor accesses the distributed memory owned by the processor, the sub-array data that is a part of the two-dimensional array data is issued by issuing one transfer instruction. I have access. That is, the transfer start address (B), the first
Element distance (D1) and second element distance (D2)
With respect to the sub-array data defined by the above, a memory address is sequentially generated for each element constituting the sub-array data, and a memory access request is issued to transfer the data.

[0005]

However, in this transfer method, when the data width is large, for example, when a plurality of elements are transferred in parallel in memory by two-distance transfer, the transfer order may not be guaranteed.

That is, when there are a plurality of elements having the same address in one memory request, the order of access is not guaranteed among these elements, and when a memory access element that precedes a memory access element issued earlier passes a memory access element. There is. If such an overtaking occurs between elements having the same address, the element preceding the address at which the subsequent element should have been written is overwritten, and the memory operation expected by software is not performed. There is a problem.

The present invention solves this problem, and when a plurality of elements are accessed in parallel in memory transfer between nodes, the transfer order is guaranteed between a plurality of elements having the same address so that the memory operation can be correctly performed. It is intended to provide a memory access processing device to be performed.

[0008]

In order to solve the above-mentioned problems, a memory access processing device according to the present invention provides a memory access processing device for performing memory access to transfer data composed of a plurality of data elements by a single transfer instruction. Wherein the processing device includes an order assurance means for performing a memory access for a plurality of transfer data elements having the same address in one memory access request in a predetermined order.

As described above, the memory access processing device of the present invention guarantees the order of transfer data elements which are present in one memory access request and have the same address, and a succeeding element precedes these elements. By preventing memory access prior to the element, the memory operation expected by the software can be accurately realized.

Further, the memory access device of the present invention divides the transfer data into data blocks composed of a plurality of transfer data elements, performs a memory access for each of the data blocks, and selects one of the transfer data elements having the same address. The sequence guarantee is performed by waiting for the end of the memory access of the data block including the preceding data element and performing the memory access of the data block including the subsequent data element.

By performing the transfer for each block, the transfer performance of the data can be improved. The transfer of the data block including the preceding element among the transfer data elements having the same address is awaited, and the subsequent data is transferred. By performing the memory access of the data block including the element, it is possible to preferably guarantee the order between the data.

Further, in the memory access device according to the present invention, the data transfer is performed by using a transfer start address (B) of the transfer data.
, A first element distance (D1), a second element distance (D2), a first element number (L1), and a second element number (L2). Wherein the data block is constituted by transfer data elements determined by the first inter-element distance and the first number of elements.

By setting the transfer format to two-distance transfer, data can be transferred more efficiently.

Further, the memory access device of the present invention comprises an identical address detecting means for detecting whether or not a plurality of data transfer elements having the same address exist in one memory access request. Performs the order guarantee only when the presence of a plurality of data transfer elements having the same address during one memory access is detected.

If the order guarantee is performed for all the memory requests, the memory transfer performance is degraded. Therefore, in the preferred embodiment of the present invention, the same address exists between the elements of the data to be transferred in one memory request. The above sequence assurance is performed only when the presence of the same address is detected.

Further, in the memory access device according to the present invention, the same address detecting means may determine that the first element distance and the second element distance are equal to each other.
(1) The first element distance is smaller than the second element distance (| D1 | <| D2 |), and is realized by D1 × (L1-1). (2) the first inter-element distance is larger than the second inter-element distance (| D1 |> | D2 |), D2 × ( L1) when the first inter-element distance (D1) is smaller than the area realized by L2-1); or (3) the first inter-element distance is equal to the second inter-element distance (| D1 | = | D2 |), the order is guaranteed in

As described above, by detecting the same address approximately by comparing areas, the amount of hardware required for detecting the same address can be reduced.

It is preferable that the order guarantee is performed only during the store operation to prevent the processing function from deteriorating. This is because the same data is read out even if the overtaking occurs between the elements during the load access, so that it is not necessary to guarantee the order.

Further, the memory access processing device according to the present invention includes a memory access issue management unit for issuing a memory access for an element to be transferred, a memory access state monitoring unit for monitoring a memory access state of transfer data, and issuing the memory access issued by the issue management unit. And a memory access state management unit for detecting the end of the data access and notifying the issuance management unit, and when performing the order assurance, the memory access state management unit notifies the end of memory access of a data block including a preceding element. After confirming by the section, the memory access issue management section issues the memory access of the data block including the subsequent element.

With this configuration, it is possible to suitably realize an access processing device that does not cause overtaking between elements and does not cause deterioration of the memory access function.

[0021]

FIG. 1 is a diagram showing the configuration of an information processing apparatus to which a memory access processing device according to the present invention can be suitably applied. The information processing apparatus 1 includes a plurality of nodes 22-0 to 22-n and an inter-node crossbar switch 21 connecting these nodes to each other.

Each node 22 includes a plurality of processors 23,
An inter-node control unit (RCU) 24 for processing data transfer between these nodes, and a shared memory 25 connected to all the processors 23 and the inter-node control units (RCU) 24
And

When a data transfer request is sent from any of the processors 23 in any of the nodes to the RCU 24 in that node, data transfer between the nodes is started. For example, the shared memory 25-0 of the node 22-0
Transfer the data in the node 22-n to the shared memory 25-0 of the node 22-n, the RCU 24-0 receives a data transfer request from the processor 23, reads out the data to be transferred from the shared memory 25-0, and transmits it to the crossbar switch. Transfer to 21.

The crossbar switch 21 switches the crossbar according to the destination node (node 22-n) of the transferred data, and transfers the data to the destination node 22-n. The node 22-n receives the transfer data sent from the crossbar switch 21 by the RCU 24-n, and writes it in the shared memory 25-n, thereby realizing data transfer between the nodes.

FIG. 2 is a diagram showing a detailed configuration of the inter-node control unit RCU 24. As described above, when performing transfer between nodes, transfer performance deteriorates unless the transfer speed between nodes is the same as the speed at which transfer data is written to or read from the memory. For this reason, the data transfer performance between nodes is usually improved by enlarging the data width of the data transferred at one time. In the example shown in FIG. 2, eight bytes are regarded as one element, and data having a data width of four elements is accessed at a time.

As shown in FIG. 2, the RCU 24 provided at each node receives a transfer request sent from another node via the crossbar switch 21 and performs transfer control. The RCU 24 includes a transfer control unit 31, a memory access control unit 32, a data reception buffer 33, a memory address / store data crossbar 34, a load data crossbar 35, and a data transmission buffer 36.

When receiving transfer data between nodes, the transfer control unit 31 receives a transfer request from another node via the crossbar switch 21, issues a memory access request, and sends it to the memory access control unit 32. The memory access control unit 32 generates a memory address based on this, and sends it to the memory address / store data crossbar.

On the other hand, the data reception buffer 33 temporarily stores data transferred from another node via the crossbar switch 31 between nodes. Here, a plurality of elements (in this example, four transfer widths) can be stored simultaneously. The data stored in the data reception buffer 33 is sent to the memory address / store crossbar 34.

Memory address / store data crossbar 3
4, the data (four elements) transmitted from the other nodes via the data reception buffer 33 and the memory addresses corresponding to the four elements transmitted from the memory access control unit 32 are connected to the shared memory 25 by the crossbar. Forward to port. This connection port is interleaved by the memory address indicated by each element, and is connected to a predetermined memory location of the shared memory 25. The transfer by the crossbar is controlled by the memory access control unit 32.

The shared memory 25 stores received data between nodes by writing data to the address position transmitted from the memory address / store crossbar 34.

When transmitting data to another node, the inter-node data transfer control unit 31 receives a data transmission request from any of the processors 23 in the node 22 and sends a data transmission request to the memory access control unit 32. Issue a load request. Memory access control unit 32
Generates a load address for four elements from the memory load request and generates a memory address / store crossbar 3
Send to 4. The memory address / store crossbar 34 sends this address to a port connected to a predetermined position of the shared memory 25, and the shared memory 25 reads data from the memory according to the sent address, and sends it to the load data crossbar 35. Send to connection port.

The load data crossbar 35 sends this data to the data transmission buffer 36 under the control of the memory access control unit 32, and the data transmission buffer 36 transmits this data under the control of the inter-node data transfer control unit 31. Is transmitted to the crossbar switch 21 between nodes. The data transmission ends when the crossbar switch 21 transfers the data to the designated transfer destination node.

FIG. 3 is a diagram showing a detailed configuration of the memory access control unit 32 and the memory address / store data crossbar 34.

As shown in FIG. 3, the memory access control unit 32 includes an identical address detection unit 41 and an issue management unit 42.
, An address generation unit 43a to 43d, a memory access state monitoring unit 45, and a contention arbitration unit 46. on the other hand,
The memory address / data crossbar 34 includes first registers 51a to 51d, selection circuits 52a to 52d,
Registers 53a to 53d.

The same address detection unit 41 receives the memory access information 61 from the inter-node data transfer control unit 31 and, based on an area comparison described later, there is a plurality of data elements accessing the same address in one memory request. Detect whether or not to do.

The memory access information 61 includes a transfer start address (B) of transfer data, a first inter-element distance (D1),
It comprises a second inter-element distance (D2), a first number of elements (L1), and a second number of elements (L2).

When detecting that there are a plurality of elements accessing the same address in one request, the same address detection unit 41 notifies the issue management unit 42 of the same address signal. The issuance management unit 42 issues a memory access instruction in block units, with the element group represented by the first inter-element distance D1 and the first element number L1 as one block. The same address detection unit 41 detects that the same address exists for a plurality of elements, and the issue management unit 4
4 is notified, the issuance management unit 44 waits without performing memory access for the next block until memory access for all issued elements is completed each time memory access for one block is completed.

The memory access status monitor 45 monitors whether or not all the memory accesses issued to the shared memory 25 have been completed by receiving an access end signal 62 from the memory 25. When access ends, memory access end signal 6
2 is notified to the issuance management unit 42.

When the issuance management unit 42 confirms that there are a plurality of elements accessing the same address in one request, the issuance management unit 42 continues until the memory access end signal 62 for one block is notified. Is not performed, a subsequent element does not overtake a preceding element among a plurality of elements accessing the same address, and a memory access order is guaranteed in an element order. If the same address is not detected in one request, there is no problem even if there is an overtaking between elements. To improve.

The issuance management unit 42 includes an address generation circuit 43
a represents the base address (B ′) of each element, 43b represents the distance between elements (D), 43c represents the distance between elements × 2 (2D),
Element address 43 × 3 (3D) is sent to 43d, and each address generation circuit 43a to 43d generates addresses of four elements to be accessed at one time based on this information, and transfers them to memory address / store data crossbar 34. I do.

Here, in the case of a store request, each address generated here from the address generation circuits 43a to 43d and the data of each element from the data reception buffer 33 via the signal lines 81 to 84 are stored as memory addresses. /
The address and data are sent to the store data crossbar 34 and stored in the first registers 51a to 51b. The stored address and data are transferred to the contention arbitration circuit 46.
And transferred to the port selected by the port selection circuits 52a to 52d and transferred to the second registers 53a to 53d.
3d. The address and data stored in the second register are sent to the shared memory 25 via the signal lines 91 to 94 for each port, and data is written to the corresponding address position.

In the case of a load request, no data is sent and only the address is sent to the shared memory 25, and the data at this address position is read and sent to the load data crossbar 35.

Overtaking between elements occurs because a plurality of elements are processed in parallel by the memory address / store data crossbar 34. That is, since the memory access path differs for each element depending on the input port of the crossbar 34, there is a case where a memory access element is issued after a preceding memory access element is passed.
Therefore, if the memory access of the first block and the second block is performed continuously, the subsequent elements may access the memory first among the elements constituting these blocks. If an overtaking occurs between elements having the same address, the address at which the element of the succeeding block is supposed to be written is overwritten with the element of the preceding block, and the expected memory access operation is not performed.

In order to solve this problem, in this embodiment, when it is confirmed that the same address exists between the blocks, the memory access of the preceding block is waited until the memory access is completed, and the memory access of the succeeding block is performed. This ensures the order of memory access. As described above, when the same address is not detected between the blocks, the memory access instruction of the first block is issued without performing the waiting operation, and then the memory access instruction of the second block is issued continuously. To increase the processing efficiency.

Next, a memory access waiting operation according to the embodiment of the present invention will be described by taking a two-distance transfer as an example. FIGS. 4 and 5 are diagrams illustrating examples of data blocks transferred by two-distance transfer. In the example shown in FIG. 4, the transfer data is based on the transfer start address (B) of the transfer data, the first element distance (D1: 8 bytes in this example), and the number of elements to be transferred (first element distance). L1: four elements in this example), the second inter-element distance (D
2: 64 bytes in this example) and the number of elements to be transferred based on the second element-to-element distance (L2: 4 elements in this example), and are all defined by B, D1, D2, L1, and L2. Elements are transferred collectively. Here, the address range indicated by the first inter-element distance and the first number of elements is 1
The second inter-element distance D2 is the distance between the head elements of each block, and the number of elements transferred by the second inter-element distance is the number of blocks transferred at the second inter-element distance. It is. In FIG. 4, the above B, D1,
The range of data transferred in D2, L1, and L2 is an element surrounded by a thick line.

In this example, the transfer data is D1 and L1
, Ie, e00, e01, e0
2, a first block composed of four elements of d03, e04,
a second block consisting of elements e05, e06, e07,
It is composed of four blocks, a third block composed of elements e08, e09, e10 and e11, and a fourth block composed of elements e12, e13, e14 and e15, unless D1 is 0. No element accesses the same address. Therefore, in this setting, memory access can be performed without being aware of the above-mentioned overtaking between elements.

On the other hand, in the example shown in FIG. 5A, the first element distance D1 (8 bytes) and the second element distance D2 (1
6 distances), a first element number L1 (four elements), and a second element number L2 (five blocks) are set to perform two-distance transfer. Here, as shown in FIG.
And element 04, element 03 and element 05, element 04 and element 0
6. . . Element 15 and element 17 each have the same address.

When such transfer data including a plurality of elements having the same address is stored in a memory using, for example, a crossbar capable of processing four elements at the same time, when input, the elements 02 and 04 having the same address become Although different signal lines are input (different input timings), elements 02 and 04 are output to the same output port at the time of output. At this time, for example, if bank busy occurs in the memory, the element 02 and the element 04 try to output to the same output port at the same timing. In such a case,
Normally, the elements to be output after arbitration are determined.
If the priority is determined using round robin control or the like in order to increase the transfer throughput, the element 04 may be output to the memory before the element 02. In such a case, since the memory access is not performed in the order of the element numbers, the data of the element 04 having the larger element number should originally remain in the memory. However, the data of the element 02 overtaken by the element 04 remains in the memory. As a result, the memory operation expected by the software is not performed.

As described above, the settings shown in FIG. 5 (first element distance D1: 8 bytes, second element distance D2: 16 bytes, first element number L1: 4 elements, second element number L2: 5 blocks 2), the same address is present in one memory access, and an overtaking occurs between elements having the same address. In this embodiment, in order to prevent the overtaking, the memory access of the succeeding block is performed while waiting for the end of the memory access of the preceding block.

That is, in the example shown in FIG.
03, element 04-07, element 08-11, element 12-1
5. The first group (element 00-03) is first accessed as a unit of processing to wait for an element group (block) delimited by the element 16-19 and the second element distance D2, and this memory is accessed. Waiting for the end of the access, a memory access instruction of the second group (element 04-07) is issued (the same applies to the third, fourth and fifth groups). By performing this waiting, the memory access processing of the element 04 of the second group does not overtake the memory access processing of the element 02 of the first group (the same applies to the third, fourth, and fifth groups). Order guarantee can be made.

However, if this waiting process is performed, the memory access of the next block is not performed until the memory access of the preceding block is completed, so that the performance of the memory access is disadvantageous. Therefore, in the device of the present invention,
It is detected whether or not a plurality of elements among the elements to be transferred at one time have the same address, and the above-described waiting process is performed only when there is an element having the same address.

FIG. 6 is a diagram for explaining the same address detection operation in the same address detection circuit 41 shown in FIG. When performing two-distance data transfer, the transfer start address B, the first element distance D1, the second element distance D2, and the first element number L are transmitted from the internode data transfer control unit 31.
1, a memory access request 61 in which the second element number L2 is set is sent to the same address detection circuit 41.
The same address detection circuit 41 compares the absolute values of the first element distance D1 and the second element distance D2, and performs the following area comparison to determine whether elements having the same address exist. Detection is being performed.

Here, in the case of | D1 | <| D2 |, where D is larger than the area realized by D1 × (L1-1).
When 2 is large, a plurality of elements do not access the same address. In this case, the same address detection unit 41
Sends a request to the issuance management unit 42 with no identical address. In response to this, the issue management unit 42 issues memory accesses sequentially without performing the order guarantee operation for each block during data transfer.

When | D1 | <| D2 | and D2 is smaller than the area realized by D1 × (L1-1), a plurality of elements may be addressed to the same address. , The same address detection circuit 41 reports to the issue management unit 42 that the same address exists. In response to the report, the issue management unit 42 waits for a processing end signal of the state monitoring unit 16 for each block, and issues a request for a subsequent block to guarantee the order.

Similarly, in the case of | D1 | <| D2 |, D is larger than the area realized by D2 × (L2-1).
When 1 is large, a plurality of elements do not access the same address, and | D1 | <| D2 |, where D is larger than the area realized by D2 × (L2-1).
If 1 is small, the same address may be accessed. Therefore, a report is made to the issue management unit 1012 that the same address exists or the same address does not exist, according to the size of D1 for the area realized by D2 × (L2-1).

In the case of | D1 | = | D2 |, since the access is to the same address, the issue management unit 42 is notified that the same address exists.

As described above, by performing the detection of the same address approximately by comparing the areas, the amount of hardware required for the detection can be reduced.

At the time of load access, the same data is read even if there is an overtaking between elements, so that there is no problem. Therefore, in this example, this order assurance operation is performed only at the time of the store operation to the shared memory. I have to.
The issue management unit 42 determines whether the operation is a load operation or a store operation, and controls whether or not to guarantee the order.

As described above, by guaranteeing the order only at the time of memory store, deterioration of the memory transfer performance due to the order guarantee operation can be minimized.

[0060]

As described above, in the memory access processing device of the present invention, the order of memory access is guaranteed for transfer data elements as necessary.
Even when a plurality of elements having the same address exist in one memory access request, the expected memory operation can be performed correctly. In addition, since it is detected whether or not there are a plurality of elements having the same address, and the order is guaranteed even when such elements exist, the data transfer performance is significantly deteriorated. There is no. Further, since the detection of whether or not there are a plurality of elements having the same address is performed approximately by using the area comparison, the amount of hardware required for guaranteeing the order can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of an information processing apparatus to which a memory access processing device according to the present invention is applied;

FIG. 2 is a diagram illustrating a detailed configuration of an inter-node control unit of the information processing apparatus illustrated in FIG. 1;

FIG. 3 is a diagram illustrating a detailed configuration of a memory access control unit and a memory address / data crossbar of the information processing apparatus illustrated in FIG. 1;

FIG. 4 is a diagram illustrating an example of a data configuration transferred by two-distance transfer;

FIG. 5 is a diagram illustrating another example of a data configuration transferred by two-distance transfer;

FIG. 6 is a diagram for explaining detection of the same address in the device of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Information processing apparatus 21 Crossbar switch 22 Node 23 Processor 24 Inter-node control unit 25 Shared memory 31 Transfer control unit 32 Memory access control unit 33 Data reception buffer 34 Memory address / store data crossbar 35 Load data crossbar 36 Data transmission buffer 41 Same address Detection unit 42 issue management unit 43a to 43d address generation unit 45 memory access state monitoring unit 46 contention arbitration unit 51, 53 register 52 selection circuit 61 memory access information 62 memory access end signal

Claims (7)

[Claims] 1. A memory access processing device for performing memory access to transfer data composed of a plurality of data elements by a single transfer instruction, wherein the processing device includes a plurality of memory devices having the same address in one memory access request. A memory access device for performing a memory access for the transfer data element in a predetermined order. 2. The memory access device according to claim 1, wherein said transfer data is divided into data blocks each comprising a plurality of transfer data elements, a memory access is performed for each data block, and said transfer data having said same address. A memory access device for performing the above-mentioned order guarantee by waiting for completion of memory access of a data block including a preceding data element among the elements and performing memory access of a data block including a subsequent data element. 3. The memory access device according to claim 2, wherein the data transfer is performed using a transfer start address (B) of a transfer data, a first inter-element distance (D1), and a second inter-element distance (D). D2), two-distance transfer defined by a first element number (L1), and a second element number (L2), and the data block is divided into the first inter-element distance and the first element. A memory access device comprising a transfer data element determined by a number. 4. The memory access device according to claim 1, wherein the processing device detects whether a plurality of data transfer elements having the same address exist in one memory access request. A memory access device comprising the same address detection means for performing the above-mentioned order guarantee only when the same address detection means detects the presence of a plurality of data transfer elements having the same address during one memory access. 5. The memory access device according to claim 3, wherein said same address detecting means is provided with said first address.
(1) the first inter-element distance is smaller than the second inter-element distance (| D1 | <| D2 |), and D1 × (2) when the second inter-element distance (D2) is smaller than the area realized by (L1-1); (2) the first inter-element distance is larger than the second inter-element distance (| D1 |> | D2 |), where the first inter-element distance (D1) is smaller than the area realized by D2 × (L2-1); or (3) the first inter-element distance and the second inter-element distance are different. In the case of equality (| D1 | = | D2 |), a memory access device is characterized in that the order is guaranteed as a plurality of transfer data having the same address in one memory access request. 6. The memory access processing device according to claim 1, wherein said order assurance operation is performed only during a store operation. 7. The memory access processing device according to claim 1, wherein said device further comprises: a memory access issue management unit for issuing a memory access for an element to be transferred; and a memory access for transfer data. A memory access state management unit that monitors the state and detects that the memory access issued by the issue management unit has ended, and notifies the issue management unit of the termination. A memory access issuance management unit that issues a memory access to a data block including a subsequent element after the memory access state management unit confirms completion of memory access of the data block including the memory block. Processing equipment.