JP2504528B2 - Bus control system between main memory controllers - Google Patents

Description

The present invention relates to a bus control method for controlling transfer timings of data, addresses, and commands transferred via a bus connected between main memory control devices, and effective use of the bus. For the purpose, in the bus control method between main storage controllers that transfers data, addresses, and commands between multiple main storage controllers via the bus, the priority is determined for the request from each unit and the priority is acquired. A transfer unit that transfers the address, data, and command of the unit that has been transferred to the main storage control device of another system via the bus; and if the transferred command indicates store data transfer that is larger than the bus width, a plurality of Within the transfer period of the store data transferred in unit time, the period after the end of transfer of the address and command related to the store data And a control means for determining the priority of only the fetch-related requests of other units by the transfer means, and permitting the use of the address bus and the command bus in the bus. It is configured to be provided in each.

[Industrial applications]

The present invention relates to a bus control system between main storage controllers, and more particularly to a bus control system for controlling transfer timings of data, addresses, and commands transferred via a bus connected between main storage controllers.

FIG. 4 shows the configuration of an information processing system to which the present invention can be applied. In the figure, 1a and 1b are main memory control units (MCU), 2a and 2b
Is a main memory unit (MSU), 3a, 3b is a central processing unit (CPU), 4a,
4b is a channel processor (CHP). One or two or more CPUs 3a and 3b for performing arithmetic operations and program execution processing are provided, and a plurality of CHPs 4a and 4b for controlling input / output devices are provided respectively.

The MCUs 1a and 1b are composed of their own MSU access control units 5a and 5b and other system access control units 6a and 6b, respectively, and other system access control units 6a and 6b.
Are connected to each other via buses 7a and 7b. Further, the own system access control unit 5a and the other system access control unit 6a are respectively connected to the CPU 3
a, CHP4a, and similarly, own system access control unit 5
b and the other system access control unit 6b are connected to the CPU 3b and CHP 4b, respectively.

Also, each of the buses 7a and 7b is a data bus, an address bus,
It consists of a command bus, and the bus 7a is another system access control unit 6a.
From the other system access control unit 6b to the transfer of data etc., the bus 7b is used from the other system access control unit 6b to the other system access control unit 6a to transfer the data etc.

The MCUs 1a, 1b respond to the requests from the CPUs 3a, 3b, CHP4a, 4b for the MSUs 2a, 2b, and the MCUs 1b, 1a of other systems as appropriate to the MSU2.
Access control a and 2b. The data read from the MSUs 2a, 2b is transferred to the other system's MCUs 1b, 1a via the buses 7a, 7b as necessary.
Transferred to

In the information processing system having such a configuration, the buses 7a, 7b
There is a limit to the bit length (bus width) of the data transferred via the bus.
It is necessary to use b effectively in time.

[Conventional technology]

FIG. 5 shows a conventional sequence for explaining the operation.
For example, the other system access control unit 6a of FIG.
There is a 32-byte store data transfer request (indicated by REQ0 in FIG. 5) larger than the bus width (8 bytes as an example), and in response to this, data transfer is performed using the bus 7a. In this case, REQ0 is shown in FIG. 5 from the data interface register in the other system access control section 6a.
As indicated by -1 to REQ0-4, 32 bytes of data are transferred every 8 times, which is the same as the data width, in four times for each unit time τ. Further, at this time, only the head REQ0 of the address of the store data is transferred from the address interface register in the other system access control section 6a within the unit time τ as shown in FIG. Addresses are not transferred during the data transfer period. This is because the addresses of the store data are continuous, and the remaining 3τ addresses can be generated on the MCU 1b side by transferring only the first address.

After the 32-byte data transfer request REQ0 is completed and the 32-byte data is transferred, the MCU1a responds to the fetch request REQ1 by sending an address or command to the MCU1b using the bus 7a as shown in FIG. Transfer to.

[Problems to be Solved by the Invention]

However, as can be seen from FIG. 5, conventionally, in the case of transferring store data larger than the bus width, a plurality of times (the fifth
In this case, the address must be transferred in four times (in the figure), but the address is sent only during the first 1τ, and the address bus is not used during the remaining 3τ, resulting in poor bus usage efficiency.

The present invention has been made in view of the above points, and an object of the present invention is to provide a bus control system between main memory control devices that can effectively use a bus.

[Means for solving the problem]

FIG. 1 shows the principle configuration of the present invention. In the figure, 10a, 10
Reference numeral b is a main memory control device, 11a and 11b are buses for transferring data, addresses and commands, 12a and 12b are transfer means, and 13a and 13b are control means.

The transfer means 12a, 12b determine the priority order for the request from each unit, and send the address, data, and command of the unit that has acquired the priority right to the main storage control devices 10b, 10a of the other system via the buses 11a, 11b. Transfer to.

Further, the control means 13a, 13b perform the transfer means 12a, 12b within the transfer period of the store data during the transfer of the store data larger than the bus width and after the transfer of the address and the command related to the store data. Then, the priority is determined only for the fetch requests of other units, and the use of the address and command buses in the buses 11a and 11b is permitted.

In the present invention, transfer means 12a, 12b and control means 13a, 13b are provided in each of the plurality of main memory control devices 10a, 10b.

[Action]

When the data transferred from the transfer means 12a (or 12b) to the main memory control device 10b (or 10a) via the bus 11a (or 11b) is store data larger than the bus width, the data is transferred over a plurality of unit times. Is performed.

On the other hand, the transfer of the address and command relating to the store data is completed within one unit time. The present invention pays attention to this point, and the transfer means is controlled by the control means 13a (or 13b).
12a (or 12b) is controlled to transfer the address and command related to the fetch request when there is a fetch request during the remaining store data transfer period after the transfer of the address and command.

Therefore, even if the data bus is busy, the fetch address and command are transferred.

〔Example〕

FIG. 2 shows a block diagram of an embodiment of the main part of the present invention. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals. FIG. 2 shows another system access control unit 6a shown in FIG.
Or 6b, and 12 and 13 respectively indicate the transfer means and control means of either one of the main memory control devices 10a and 10b of FIG.

In FIG. 2, 15 is another MCU priority circuit,
Requests from the above-mentioned CPU and CHP units REQ0-R
When EQm is input and the request is an access request to another system MSU, the priority order is determined, and the command, address, and data from each unit are input.
Controls 16, 17, and 18 to select and output the command, address, and data of the unit that has acquired the priority.

Also, 19, 20 and 21 are interface registers,
The commands, addresses and data selected and output from the selectors 16, 17 and 18 are temporarily stored (set) separately and sent to the command bus, address bus and data bus. The other-system access request is taken out from the other-MCU priority circuit 15 and is sent to the other-system MCU via the dedicated line or the command bus.

Further, 22 supplies a signal line and a transfer command to the other MCU priority circuit 15, and the other MCU is provided only when the command indicates a store data transfer larger than a bus width (8 bytes in this case) which is a data bit length. The priority circuit 15 is provided so as to perform a predetermined operation, and constitutes the control means 13a and 13b.

Next, the operation of this embodiment will be described with reference to FIGS. When the request from the unit that has acquired the priority by the other MCU priority circuit 15 is a transfer request of 32-byte store data as shown by REQ0 in FIG. 3, the other MCU priority circuit 15 determines that the selectors 16, 17 and 18
Command 0, address 0, data 0 from the above unit to be selectively output.
As shown in the figure, the interface register 21 is made to set data REQ0-1 of the first 8 bytes of the 32-byte store data, and the interface registers 19 and 20 are made to set the command and address.

The commands, addresses and data set in the interface registers 19, 20 and 21 are transferred to the other system MCU together with the other system access request via the command bus, address bus and data bus. Further, at this time, the other MCU priority circuit 15 identifies that the data to be transferred is 32-byte store data by a command input from the interface register 19 through the signal line 22.

As a result, the other MCU priority circuit 15 switches the selectors 16 and 17 so as to select the request REQ1 having a higher priority among the fetch-related requests of the other unit within the second unit time τ and switches the interface registers 19 and 20.
Set the command and address to. On the other hand, this 2
Within the second unit time τ, 2 of the 32-byte store data
The 8th byte data is set in the interface register 21, as indicated by REQ0-2 in FIG.

Thereafter, in the same manner as above, the third, fourth 8-byte data of the 32-byte store data are stored in the interface register 21 in each unit time τ in the interface register 21 as REQ0-3, REQ0-4.
While the fetch-related requests REQ2 and REQ3 are sequentially selected, the command and address are sequentially set in the interface registers 19 and 20, respectively, as shown by REQ2 and REQ3 in FIG. .

As described above, according to the present embodiment, the data bus for 4τ for transferring 32-byte store data is used, while the 32
Addresses and commands relating to byte store data are sent out only during the first 1τ period of the above 4τ period, and during the remaining 3τ period, addresses and commands according to fetch system requests are sent out using the address bus and the command bus.

In the MCU on the receiving side, the transmitted data, address and command are input to the port as schematically shown in FIG. 3, and the port control unit detects that the command indicates 32-byte store data. When I did
During the subsequent 3τ period, it recognizes that the rest of the data will be sent, and identifies the address and command as a fetch address and command by a request different from the 32-byte store data request.

〔The invention's effect〕

As described above, according to the present invention, even if the data bus is busy, the fetch address and the command are transferred, so that the bus between the main storage control devices can be used more effectively than in the conventional case. Fetch-type address,
It has features such that commands can be transferred at high speed and throughput can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of a principle configuration of the present invention, FIG. 2 is a block diagram of an embodiment of a main part of the present invention, FIG. 3 is a diagram showing an operation explanation sequence of an embodiment of the present invention, and FIG. Is a system configuration diagram to which the present invention can be applied, and FIG. 5 is a diagram showing a sequence for explaining an operation of a conventional example. In the figure, 10a and 10b are main memory control units (MCUs), 11a and 11b are buses, 12a, 12b and 12 are transfer means, 13a, 13b and 13 are control means, 15 is another MCU priority circuit, and 16 to 18 are Selectors, 19 to 21 are interface registers.

Claims (1)

(57) [Claims] 1. A request from each unit in a bus control system between main memory controllers for transferring data, addresses and commands between a plurality of main memory controllers (10a, 10b) via a bus (11a, 11b). To prioritize,
Transfer means (12a, 12b) for transferring the address, data, and command of the unit that has acquired the priority to the main storage control device of another system via the bus (11a, 11b), and the command to be transferred has a bus width When the storage data transfer is larger than the above, the transfer is performed within the transfer period of the store data that is transferred in a plurality of unit times, and within the period after the transfer of the address and command related to the store data is completed. The transfer means (12a, 12b) is used to determine the priority order only for fetch requests from other units,
Control means (13a, 13b) for permitting the use of the address bus and command bus in the bus (11a, 11b) are provided in each of the plurality of main memory control devices (10a, 10b) Bus control system between main storage controllers characterized by.