JPS5936845A - Controlling device of communication - Google Patents

Abstract

PURPOSE:To process errors in early stage, by inhibiting memory access operation and generating an error interruption request at the time point, when a malfunction or fault exceeding a memory address border is generated during the memory access operation of a circuit connecting part. CONSTITUTION:When one of the circuit connecting parts transmits transmission data to a terminal through the circuit, the circuit connecting part outputs a direct memory access (DMA) request to a common controlling part 11, and when an execution processing part 20 permits the execution of the DMA operation, starts the DAM operation. When detecting that the contents of a memory address storing means in the circuit connecting part outputted to a memory address bus circuit are less than the contents of a memory address border storing means 22 which are previously stored during the DMA operation, the circuit connecting part 1 informs the result to an execution processing controlling means 20 as an error. The execution processing controlling means 20 inhibits the incorrect DMA operation of the circuit connecting part to prevent the transmission of incorrect data.

Description

[Detailed Description of the Invention] [Technical Field to which the Invention Pertains] The present invention relates to a communication control device, and particularly to a communication control device having a memory address error detection control mechanism during direct memory access (hereinafter referred to as DMA) of a communication control unit. Regarding a control device.

[Prior art]

Conventionally, in this type of communication control device, C has an insufficient function of checking the normality of the memory address of the DMA operation of the line connection part, so it may be caused by a malfunction of the DMA control circuit of the line connection part or by the hardware. If a program storage area outside the transmit/receive data buffer area was accessed due to a failure, the impact would be significant. For example, DMA in transmit mode
If the program storage area outside the send/receive data buffer area is accessed during operation, the contents of the program storage area may be sent as send data or the DM in receive mode may be accessed.
If the above program storage area is accessed during operation, the contents of the program storage area may be replaced with received data, so it is possible that a memory address failure as the next cause may cause erroneous data transmission or abnormal program operation. There were drawbacks, such as secondary failures caused by the failure, and the time it took to find the root cause of the failure.

[Purpose of the invention]

An object of the present invention is to prohibit the memory access operation at that point when an erroneous insertion that exceeds the memory address boundary or a failure occurs in the memory address control circuit during the DMA operation of the line connection part, and the requested memory address and Hair bundle line connection unit 1) Generates an error interrupt request at the same time as storing the DMA channel number, and performs error processing at an early stage to solve the above drawbacks and ensure failures caused by malfunction of the line connection unit 1) M A It is an object of the present invention to provide a communication control device that can prevent the spread of secondary failures as much as possible.

The present invention provides a communication control device that has a large number of line connections and performs time-division multiplex control of the lines, including memory address boundary storage means that can be written by a program in a common control unit, and the contents of the memory address storage means and memory addresses. memory address comparison means for comparing the contents of the bus; and error detection by the comparison means when the arbitrary line connection section crosses the memory address boundary and accesses outside the data buffer area in the memory during direct memory access operation. error interrupt request reporting means for inhibiting the memory access operation and simultaneously reporting an error interrupt request to the execution processing control means in the common control unit; and execution processing control means for prohibiting the memory access operation of the error line connection unit; It is constituted by X7 including memory address storage means for storing the memory address of the error line connection section, and direct memory access channel address storage means for storing the direct memory access channel address.

[Explanation of Examples]

Embodiments of the present invention will be described in detail with reference to the drawings. In FIG. 1, line connection section 10-1,...+
10-n connects to the common control unit 11 via the bus Ifj1100.
, the memory 12 , and the host device interface section 13 . Bus line 100 consists of a data line, a memory address bus line, and a DMA channel address bus line.

The common control unit 11 controls the host device interface unit 13 and the line connection unit 1 by a program stored in the memory.
0-1, ゛°----, and 10-n are executed and controlled.

FIG. 2 is a layout diagram of the inside of the memory 12, which is mapped to a diagnostic program storage area, a control program storage area, a control table storage area, and a data buffer storage area. The memory address boundary means the start address of the data buffer storage area.

FIG. 3 is a block diagram showing the configuration of the common control section 11. Execution processing control section 20 and error interrupt request reporting means 21
When the line connection section 10-n is running in the DMA mode, the memory address boundary storage means 22 compares the contents of the memory address boundary storage means 22 with the contents of the memory address line of the bus line 100, and Memory address comparing means for inputting an error interrupt request to the error interrupt request reporting means 21 as an error when the address boundary is exceeded, that is, the contents of the memory address line are smaller than the contents of the memory address boundary storage means 22 23, a memory address storage means 24 for storing the contents of the memory address bus line at that time when the error is detected, and a DMA channel for storing the contents of the DMA channel address bus line at that time when the error is detected as well. Address storage means 2
5, and a priority selection means 26 that accepts DMA requests from a plurality of line connection units and selects the line connection unit with the highest priority (7) and transmits the request to the execution processing control unit 20.

(-1i, t) The above are only the means necessary for understanding the present invention, and the others are omitted.

Now, when one of the line connection units 10-n transmits transmission data to the terminal via the line 2, the line connection unit transmission data buffer address in the data buffer storage area in the memory is stored as a memory address in the line connection unit. A DMA request is output to the common control unit 11, accepted and selected by the priority selection unit 26, and waits for permission from the execution processing control unit 20 to execute the DMA operation. When the execution processing control unit 20 permits the line connection unit to execute a DMA operation, the line connection unit enters the DMA operation. That is,
The contents of the memory address storage means in the line connection unit are output to the memory address bus line, and the transmission data is read from the line connection data buffer in the memory 12 and stored in the transmission data buffer in the line connection unit. The transmission data written in the transmission data buffer is sent bit-serially to the transmission data line of the line by the differential serial conversion means and transmitted to the terminal.

During the DMA operation of the line connection unit, the contents of the memory address storage means in the line connection unit outputted to the memory address bus line are greater than the contents of the memory address boundaries in the memory address boundary storage means 22 stored in advance. If it is smaller, it is reported as an error to the execution processing control means 20 via the error interrupt request reporting means 21. At this time, the contents of the memory address storage means in the line connection unit outputted to the memory address line are stored in the memory address storage means 24, and the contents of the DMA channel address bus line outputted from the execution processing control means 20 are stored in the DMA channel address storage means 25. and keep it as useful information when pursuing obstacles.
Read when the fault handling program is executed. The execution processing control means 2o inhibits the MA operation of the error line connection unit to prevent invalid data from being written into the transmission data buffer of the error line connection unit.

The case where the line connection unit 10-n transmits data to the Duan Song via the line has been described above. The same applies to the case of receiving data from a terminal, in which the memory address comparison means 23 detects a DMA address error and prevents unauthorized writing of the received data, and at the same time, the contents of the memory address where the error occurred is stored in the memory address storage means. 24, the contents of the DMA channel AT1/SU bus line are stored in the DMA channel address storage means 25 & C, respectively. These address information are used during failure processing, and the same contents are maintained unless read out.

〔Effect of the invention〕

As explained above (7), the present invention includes the DMA of the line connection section.
Even if a fault that crosses a memory address boundary occurs in a memory address control circuit during operation, it is configured to prevent secondary faults due to this, and at the same time to be able to log the faulty memory address and faulty line connection channel number. (line connection) section DM A.
A communication control device W is obtained that can prevent the spread of secondary failures as much as possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of a communication control device according to an embodiment of the present invention, FIG. 2 is a memory layout diagram, and FIG. 3 is a diagram showing an example of the configuration of a common control unit thereof. 11...Common control unit, 12...Memory, 13...°°° Host device interface M, 10-
1,...,10-n...line connection part,
20... Execution processing control means, 21...
Error interrupt request reporting means, 22... Memory address boundary storage means, 23... Memory address comparison means, 24... Memory address storage means, 2
5...DMA channel address storage means, 26
...Priority selection means, 100...Bus line.

Claims (1)

[Claims] In a communication control device that has a large number of line connections and performs time-division multiplex control of the lines, a memory address boundary storage means that can be written by a program is provided in a common control unit, the contents of the memory address storage means, and the contents of a memory address bus. and a memory address comparing means for comparing the common memory addresses, and when the arbitrary line connection unit crosses the memory address boundary and accesses outside the data buffer area in the memory during the direct memory access operation, the comparing means detects an error and the common memory address is An error interrupt request reporting means for reporting an error interrupt request to the execution processing control means in the control unit, an execution processing control means for prohibiting memory access operation of the error line connection section, and storing a memory address of the error line connection section. 1. A communication control device comprising memory address storage means and direct memory access channel address storage means for storing a direct memory access channel address.