JPH05298193A - Memory access fault detecting circuit - Google Patents

Abstract

PURPOSE:To enable detection that erroneous data is not written in a memory and to which memory port a fault belongs regarding a device using a shared memory. CONSTITUTION:In a device which uses a shared memory 76 provided with a memory port circuit 77 provided with pulral ports 38 to 39 performing the data transfer between a common bus 9 and a memory 34 and performing the error detection and correctionof transfer data by using error correction codes, and a memory access control circuit 37 to buffer data to be written in the memory 34, and which is provided with a write in means 43 writing in data in shared memory 76 via the common bus 9, an error detection means 40 performing the error check of data to be transmitted to the memory 34 by using the error correction codes and an inhibition means 41 to inhibit the data writing-in for the memory 34 at the time when the error detection means 40 detects the data error of plural bits and notification means 42 notifying the inhibition of the data writing-in to the write in means 43 provided in the constitution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus using a shared memory configured to write data into a memory via a plurality of memory ports connected to a common bus and a memory access control circuit, and more particularly to a memory port. The present invention also relates to a memory access failure detection circuit that can prevent erroneous data from being written in a memory due to a failure of the memory access control circuit and can detect which memory port has a failure.

A device that uses a shared memory connected to a common bus is, for example, a disk control device that is composed of a plurality of functional units that are each controlled by a processor. The disk control device includes a functional unit called a channel adapter that controls data transfer with a host device, a functional unit called a device adapter that controls data transfer with a disk device, and these functional units. It is composed of a functional unit called a resource manager that controls the processing of the above, a functional unit called a service adapter that diagnoses these functional units, and a functional unit called a shared memory that stores transfer data.

By the way, the shared memory passes through a plurality of memory ports and a memory access control circuit as described above,
Since the data is written to the memory, if a failure occurs in this memory port and memory access control circuit, incorrect data will be written to the memory and the data will be destroyed. Needs to be done.

It is desirable to be able to easily select which of the plurality of memory ports has failed.

[0005]

2. Description of the Related Art FIG. 5 is a block diagram for explaining an example of a conventional technique, and FIGS. 6 and 7 are detailed block diagrams of each functional unit.

The disk controller 2 is composed of a plurality of functional units. The channel adapter 4 has a structure as shown in FIG. 6A, and the processor 12 operates by reading a program stored in the control memory 13. Then, through the interface circuit 10, the start I / O command is received from the channel 1 and the data transfer with the channel 1 is performed, and the common bus control circuit 11 is controlled so that another signal is transmitted through the common bus 9. Transfers data to and from the functional unit.

The device adapter 5 has a structure as shown in FIG. 6 (A), and the processor 12 operates by reading the program stored in the control memory 13 to operate the interface circuit 10.
Command is sent to the disk device 3 to transfer data to and from the disk device 3, and the common bus control circuit 11 is controlled to transfer data to and from other functional units via the common bus 9. I do.

The resource manager 6 has a configuration as shown in FIG. 6 (B), and the processor 15 operates by reading the program stored in the control memory 14 to control the common bus control circuit 16 to operate the common bus 9. All the start I / O commands from the channel 1 are received and stored in the RAM 17 via the route, the start I / O commands are centrally managed, and a channel adapter 4 is provided for each start I / O command. The device adapter 5 is instructed to perform data transfer processing.

The control information for each received start I / O command, the control information for each channel path, and the disk device 3
Control information is stored in the RAM 17 and other functional units are RA
This information can be read out by accessing the RAM 17 through the M access control circuit 18, and the information is centrally managed.

The service adapter 8 has a structure as shown in FIG. 6C, and the processor 21 operates by reading the program stored in the control memory 22 to operate.
When the operator gives a diagnosis instruction via 0, the common bus control circuit 23 is controlled to perform the diagnosis of the designated functional unit via the common bus 9, and the result is stored in the RAM 19 and illustrated by the operator's instruction. Display on the omitted operation panel.

The shared memory 7 has a structure as shown in FIG. 7, a memory port circuit 24 is provided with a plurality of ports 27 to 28, a driver 29 and a driver / receiver 30, and a memory access control circuit 25 is provided with registers 31 and 32. Is provided, and the memory circuit 26 includes an instruction analysis circuit 33 and a memory 3.
4 are provided.

At the port 27, an ECC 35 for generating an error correction code and detecting and correcting an error is provided at the port 2.
An ECC 36 for generating an error correction code and for detecting and correcting an error is provided in the reference numeral 8, and a plurality of ports 27 to 28 are provided corresponding to the data transfer capability of the common bus 9.

That is, the data transfer capability of the common bus 9 is 96.
If the data transfer capability of the ports 27 to 28 is 12 Mbytes in M bytes, the number of ports becomes eight. When the channel 1 sends a start I / O command to the channel adapter 4 and instructs to write data to the disk device 3, for example, the channel adapter 4 requests the resource manager 6 for the right to use the common bus 9 and is granted. The cylinder address, head address, and sector address are stored in the RAM 17 of the resource manager 6.

The channel adapter 4 is the channel 1
Write the data sent by the. That is, one of the ports 27 to 28, for example, the port 27
After setting the address of the write data to, the write command and the number of transfer words are issued, and the writing of the data transmitted by the channel 1 is instructed.

Therefore, the port 27 writes the write command and the address to the register 31 via the driver 29, the register 31 separates the write command and the address, and sends the command and the address to the command analysis circuit 33.

The ports 27 to 28 add the error correction code created by the ECCs 35 to 36 to the data transferred via the common bus 9 and send it to the memory 34 via the driver / receiver 30, and the memory 34 analyzes the instruction. Based on the control signal of the circuit 33, data is sequentially written from the designated address.

The device adapter 5 reads a cylinder address, a head address and a sector address stored in the RAM 17 of the resource manager 6 according to an instruction from the resource manager 6, controls the disk device 3 and positions the head at a designated cylinder. Then, after setting the address of the read data in the port 27, the read command and the number of transfer words are issued, and the reading of the data from the memory 34 is instructed.

That is, similarly to the above, the data read from the memory 34 is written in the register 32 by the command and address given from the register 31 to the instruction analysis circuit 33, and transferred to the ports 27 to 28 via the driver / receiver 30. Then, the error detection and correction are performed by the ECCs 35 to 36, and the data is transferred to the device adapter 5 via the common bus 9.

Therefore, the device adapter 5 sends the transferred data to the designated head, and causes the designated sector to sequentially write the data.

[0020]

As described above, the conventional E
An error correction code is added to the data written in the memory 34 by the CCs 35 to 36, and the ECC 35 to 36 detects whether or not the data read from the memory 34 is erroneous.

If a 1-bit error is corrected, it will be used, but if it is a multi-bit error, an error will be reported as uncorrectable. By the way, the driver / receiver 30 and the register 32 exist between the memory 34 and the ports 27 to 28, and the ports 27 to 28 and the register 32 are provided.
If two or more faults occur in the pins or data lines of the LSi configuring the memory, data with a multi-bit error is written in the memory 34, and the error is detected during reading. There is a problem that the written data is destroyed.

Further, when the service adapter 8 diagnoses the shared memory 7, even if the data in the memory 34 is read through any of the ports 27 to 28, the memory 34 is read.
Since the error is detected, it is impossible to detect which port of the shared memory 7 has the failure.

In view of such a problem, the present invention makes it possible to detect a faulty port among the plurality of ports 27 to 28 and prevent the memory 34 from writing error data. The purpose is to do so.

[0024]

FIG. 1 is a block diagram for explaining the principle of the present invention. In FIG. 1 (A), the device is connected to a memory 34 for storing transfer data and a common bus 9 for transferring data between the common bus 9 and the memory 34, and using an error correction code. A memory port circuit 77 having a plurality of ports 38 to 39 each having an ECC function for error detection and correction of transfer data, controlling access to the memory 34, and buffering data to be written in the memory 34. The shared memory 76 including the memory access control circuit 37 is used, and the writing means 43 for writing data into the shared memory 76 via the common bus 9 is provided.

Then, the error detection means 40 performs error checking of the data buffered by the memory access control circuit 37 and sent to the memory 34 using the error correction code, and the error detection means 40 has a plurality of bits. When a data error is detected, a prohibiting unit 41 for prohibiting data writing to the memory 34 and a notifying unit 42 for notifying the write prohibition of the data to the writing unit 43 via the memory port circuit 77 are provided.

Further, in FIG. 1B, the device is connected to a memory 34 for storing transfer data and a common bus 9 so as to perform data transfer between the common bus 9 and the memory 34 and to make an error. A memory port circuit 45 having a plurality of ports 47 to 48 each having an ECC function for detecting and correcting an error in the transfer data using a correction code;
4 is controlled, and the memory 34
Using a shared memory 44 having a memory access control circuit 46 for buffering the data to be written in, the writing means 43 for writing the data in the shared memory 44 via the common bus 9 and the shared memory 44 The diagnostic means 54 which diagnoses is provided.

Each of the ports 47 to 48 of the memory port circuit 45 is provided with address transmitting means 49 to 50 for transmitting its own port address when transmitting the data to be transferred to the memory 34. The memory access control circuit 46 includes an error detecting means 40 for performing an error check on the data buffered by the memory access control circuit 46 and sent to the memory 34 using the error correction code, and the error detecting means 40. When a data error of a plurality of bits is detected, the storage means 51 for storing the port address transmitted by the address transmission means 49 to 50 separately for each port, and the port address stored in the storage means 51 for each port 47. Read-out means 52 for distinguishing and reading out for every 48 to 48, and the error detection means 40 has a plurality of bits of data. The detection of the error is provided to a notification unit 53 for notifying the diagnosis means 54.

When the notifying means 53 notifies the diagnosing means 54 of the detection of a data error of a plurality of bits via the memory port circuit 45, the diagnosing means 54 controls the reading means 52 via the memory port circuit 45. Then, the address of the faulty port stored in the storage means 51 is read.

[0029]

With the above arrangement, the prohibiting means 41 prohibits the writing of data at the time when the error detecting means 40 detects a data error of a plurality of bits.
Writing of data to 4 is stopped. Therefore, the data in the memory 34 is prevented from being destroyed.

Then, the writing means 43 can recognize that the writing of data has been stopped by the notification from the notifying means 42. Further, the storage means 51 stores the address of one port which has transmitted the port address among the address transmission means 49 to 50 when the error detection means 40 detects a data error of a plurality of bits.

That is, among the ports 47 to 48, the address of the port which is transferring the data block in which the data error of a plurality of bits has occurred is stored. Then, the diagnostic means 54
Since the notification means 53 notifies the occurrence of a data error, the reading means 52 is controlled to read the port address stored in the storage means 51.

Since this port address indicates the faulty port, the faulty port can be easily recognized.

[0033]

2 is a block diagram of a circuit showing an embodiment of the present invention, FIG. 3 is a detailed block diagram of a memory access control circuit, and FIG. 4 is a time chart for explaining the operation of FIG.

In FIG. 2, the same reference numerals as those in FIG. 4 indicate the same functions. Ports 47 to 4 of the memory port circuit 45
8 is a port 27 to 28 shown in FIG. 6 to which address sending circuits 55 to 56 are added, respectively, and when sending a write or read command and an address to the memory access control circuit 78 via the driver 29, the address sending circuit 55 adds the address of the port 47 and sends it out, and the address sending circuit 56 adds the address of the port 48 and sends it out.

The memory access control circuit 78 has a configuration as shown in FIG. 3, and the address, the instruction and the port address transmitted by the driver 29 of the memory port circuit 45 via the clock distribution as shown in FIG. It is received by registers 57 and 58 which operate in a time division manner by the circuit.

That is, the register 57 receives the address and the instruction, and the port address to be subsequently transmitted is registered in the register 58.
To receive. Then, the address and the instruction received in the register 57 are sent to the multiplexer 59 following the address as indicated by the output 57 in FIG. 4, and through the multiplexer 59, the instruction is continued following the address as shown in FIG. Are sent to the instruction analysis circuit 33 of the memory circuit 26, respectively, as described in FIG.

Then, the port address received by the register 58 is registered in the registers 65 to 65 as shown at 58 output in FIG.
Sent to 66. The data transmitted by the channel adapter 4 or the device adapter 5 enters the ports 47 to 48, and ECC check codes are added by the ECCs 35 to 36. Then, as shown in FIG. 4, the receiver 73 enters, and a register 74, which operates in a time division manner by a clock distribution circuit (not shown), separates the data, and the register 75 separates the ECC check code added to the data. Is stored.

Then, the data is sent to the ECC error detection circuit 62 and then sent to the memory 34 as shown at 74 output in FIG. 4, and the ECC check code is sent to the ECC error detection circuit as shown at 75 output in FIG. The data is sent to the circuit 62 and then to the memory 34, and written to the designated addresses of the memory 34, respectively.

At this time, the ECC error detection circuit 62 performs an error check using this data and the ECC check code, and if there is no error, the logic "0" is still sent to the AND circuit 60, so that the multiplexer 59. Sends the address and instruction sent from the register 57 to the instruction analysis circuit 33 of the memory circuit 26 as described above.

If the ECC error detection circuit 62 detects an error of a plurality of bits as indicated by 62 error detection in FIG. 4, a logic "1" is sent to the AND circuit 60 and the decoder 61 also decodes the instruction. Logic "1" is AND circuit 6
To send to 0, AND circuit 60 sends a logic "1" to multiplexer 59.

Therefore, the multiplexer 59 has the register 5
Instead of the command sent by 7, the operation stop command given from is sent to the command analysis circuit 33 at the command sending timing shown in FIG.

Therefore, the instruction analysis circuit 33 instructs the memory 34 to stop the data writing operation, so that the writing of the data in which the error has occurred is stopped. In the flip-flop 63, the ECC error detection circuit 62 has a logic "1".
To be sent, as shown in FIG.
After that, an error occurrence signal is sent to the ports 47 to 48, and the ports 47 to 48 notify the resource manager 6 of the error occurrence.

Therefore, the resource manager 6 notifies the channel adapter 4 or the device adapter 5 that the writing of data due to an error has occurred. As described above, the port address received in the register 58 is 65-66 in FIG.
As shown in FIG.
The address of the port 47 is stored in the register 65, and the address of the port 48 is stored in the register 66, respectively.

When the ECC error detection circuit 62 detects an error of a plurality of bits, the logic "1" is sent to the counter 68 as described above. The counter 68 repeats counting up at a timing such that the port address of the port 47 is stored in the register 65 and the port address of the port 48 is stored in the register 66 by the clock, and when a logical "1" is input, the counter 68 of FIG. As shown in 68,
The count value at that time is sent to the decoder 67.

The decoder 67 enables one of the registers 65 to 66 corresponding to this count value to store the port address transmitted by the register 58. When the service manager 8 is notified of the error occurrence by the resource manager 6, the service adapter 8 starts diagnosis via the ports 47 to 48, sends an instruction to the decoder 61 via the register 57,
The count value of the counter 71 is sent to the decoder 70.

The counter 71 sends out a count value that circulates so as to sequentially read the contents of the registers 65 to 66, and the OR circuit 72 enables the driver 69 by the signal sent out by the decoder 70 which decodes this count value. Therefore, the multiplexer 64 sequentially reads the contents of the registers 65 to 66, sends them to the ports 47 to 48 via the driver 69.

The service adapter 8 has ports 47 to 48.
When the port address at the time of error occurrence is recognized from the contents of the registers 65 to 66 sent via the above, the control information stored in the RAM 17 of the resource manager 6 is updated and the use of the faulty port is prohibited.

When data is read from the memory 34,
Read data enters through the multiplexer 64,
Since the read signal enters the OR circuit 72 via the, the multiplexer 64 sends the read data to the driver 69,
The read data is sent to the ports 47 to 48 via the driver 69 enabled by the read signal.

[0049]

As described above, according to the present invention, it is possible to prevent the destruction of data caused by writing error data in which a plurality of bits are erroneous into a memory, and it is possible to recognize the occurrence of an error in a plurality of bits.

Further, it becomes possible to detect a faulty port among a plurality of ports, and it is possible to determine whether or not a fault is in a common part such as a driver or a register, which facilitates maintenance. Can be done.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention.

FIG. 3 is a detailed block diagram of a memory access control circuit.

FIG. 4 is a time chart explaining the operation of FIG.

FIG. 5 is a block diagram illustrating an example of a conventional technique.

FIG. 6 is a detailed block diagram of each functional unit (No. 1)

FIG. 7 is a detailed block diagram of each functional unit (No. 2)

[Explanation of symbols]

 1 channel 2 disk controller 3 disk device 4 channel adapter 5 device adapter 6 resource manager 7,44,76 shared memory 8 service adapter 9 common bus 10,20 interface circuit 11,16,23 common bus control circuit 12,15,21 Processor 13, 14, 22 Control memory 17, 19 RAM 18 RAM access control circuit 24, 45, 77 Memory port circuit 25, 37, 46, 78 Memory access control circuit 26 Memory circuit 27, 28, 38, 39, 47, 48 Port 29, 69 Driver 30 Driver / Receiver 31, 32, 57, 58, 65, 66, 74, 75 Register 33 Instruction analysis circuit 34 Memory 35, 36 ECC 40 Error detection means 41 Inhibition means 42, 53 Notification means 43 Writing means 49, 50 Address sending means 51 Storage means 52 Reading means 54 Diagnostic means 55, 56 Address sending circuit 59, 64 Multiplexer 60 AND circuit 61, 67, 70 Decoder 62 ECC Error detecting circuit 63 flip-flops 68 and 71 the counter 72 OR circuit 73 Receiver

Claims (2)

[Claims] 1. A memory (34) for storing transfer data, and a common bus (9) connected to the common bus (9) and the memory (34).
Memory port circuit (77) including a plurality of ports (38) to (39) each having an ECC function of performing data transfer between ) And a memory access control circuit (37) for controlling access to the memory (34) and buffering data to be written in the memory (34), the common memory (76) is used. In a device having a writing means (43) for writing data to the shared memory (76) via a bus (9), the memory access control circuit using the error correction code
An error detecting means (40) for buffering the data sent by the (37) to the memory (34), and an error detecting means (40) when the error detecting means (40) detects a multi-bit data error. Memory access failure detection, characterized in that a prohibiting means (41) for prohibiting data writing to the memory (34) and a notifying means (42) for notifying the write means (43) of data write prohibition are provided. circuit. 2. A memory (34) for storing transfer data and a common bus (9) connected to the common bus (9) and the memory (34).
And a memory port circuit (45) having a plurality of ports (47) to (48) each having an ECC function of performing error detection and correction of the transferred data by using an error correction code. ) And a memory access control circuit (46) for controlling access to the memory (34) and buffering data to be written in the memory (34). A device comprising a writing means (43) for writing data to the shared memory (44) via a bus (9) and a diagnostic means (54) for diagnosing the shared memory (44), For each port (47) to (48) of the port circuit (45),
When sending data to be transferred to the memory (34), each is provided with address sending means (49) to (50) for sending its own port address, and the memory access control circuit (46) is provided with the error correction code. An error detecting means (40) for buffering the data by the memory access control circuit (46) and sending it to the memory (34) for error checking, and a data error of a plurality of bits by the error detecting means (40). Storage means (51) for storing the port addresses transmitted by the address transmission means (49) to (50) separately for each port at the time of detecting
The port address stored in (51) is assigned to each port (47) to (48).
A reading means (52) for distinguishing and reading for each, and the error detecting means
(40) is provided with a notifying means (53) for notifying the diagnosing means (54) that a multi-bit data error has been detected, and the notifying means (53) provides the diagnosing means (54) with multi-bit data. A memory access failure detection circuit, wherein the diagnostic means (54) controls the read means (52) to read the address of the failed port when the error detection is notified.