JPH0520200A - Error processing system for address conversion buffer - Google Patents

Abstract

PURPOSE:To prevent the deterioration of the working ratio by carrying on the error processing without isolating the suspected trouble areas nor performing any degenerating operation as long as an address conversion buffer has the intermittent reading errors. CONSTITUTION:A data check circuit 320 or 330 checks the read data on an address conversion buffer device 100 which contains the address conversion buffers 120 and 130 of different levels. Then the information which checks whether the error information obtained from the data checking operations is identical with the hitherto error information or not is given to an error control information holding circuit 600. The circuit 600 generates a real address to the first error to carry on the due processing and then performs a degenerating operation to the second error to generate a real address for continuation of the due processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address translation buffer error processing system, and more particularly to an address translation buffer of an address translation buffer controller for translating a virtual address created by a virtual computer into a real address of a real computer in a computer system having virtual memory. Error handling method.

[0002]

2. Description of the Related Art Conventionally, this kind of address translation buffer error processing system has been designed so that when a parity error is detected in the data read from the address translation buffer, the system is stopped even when it is not desired to stop the system, and the system is promptly operated. The suspected obstacle is replaced, or the address translation buffers are provided for a plurality of levels, and when an error is detected, the suspected obstacle is reported to the diagnostic device and separated, and the degenerate operation is performed. Also, when an error is detected, the translation pair of the virtual address and the real address is not registered in the address translation buffer (generally called a mishit), and a new translation pair of the virtual address and the real address is created. Registered in the address translation buffer.

[0003]

The above-mentioned conventional error processing method of the address translation buffer deteriorates the performance of the system by stopping the system or performing the degenerate operation even if the address translation buffer has an intermittent failure. It has the drawback of

[0004]

According to the error processing method of the address translation buffer of the present invention, the contents of the replace memory are updated every time the address translation buffer for translating a virtual address into a real address is accessed. It records that the data was accessed most recently, and if the required data does not exist in the address translation buffer, it is unregistered and a new real address is created for the virtual address and the address is based on the contents of the replace memory. In the address translation buffer error processing method of the address translation buffer device for registering at the position where the translation buffer has been added, an address translation buffer of a plurality of levels, a check circuit for checking the read data of this address translation buffer, and a check circuit from this check circuit Error information storage that holds the error information of If there is no error at the same position by comparing the circuit, the error information comparison circuit that compares the error information from the check circuit with the error information already held in the error information holding circuit, and this error information comparison circuit Has a control circuit for continuing the processing as an unregistered virtual address, and disconnecting the address translation buffer in which the error occurred and performing degenerate operation to continue the processing when an error occurs at the same position.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a virtual address register 110, two-level address translation buffers 120 and 130 for holding virtual address information and corresponding real address information in pairs, and an address translation buffer 1
Replace control circuit 140 for registering a new entry in 20 or 130, LRU (Least Recentr) holding information for the replacement algorithm
y Used) memory 150, virtual address register 1
Comparing circuit 2 for comparing a part of 10 with the virtual address of the read data from the address translation buffers 120, 130
20 and 230, a multi-level address translation buffer device 100 including a selector 240 that selects read data from the address translation buffers 120 and 130, and a data check circuit 320 that checks the respective read data from the address translation buffers 120 and 130. , 3
30, error information holding circuits 420 and 430, error information comparison circuits 520 and 530, error control information holding circuit 600 that holds operation control information and error information at the time of error detection, and performs control at the time of error detection, real address generation Circuit 7
00 and a diagnostic control circuit 800.

In the above configuration, when a request for translation from a virtual address to a real address is issued by the host device, the virtual address is fetched into the virtual address register 110 and the address translation buffers 120 and 130 are indexed. Although the embodiment of FIG. 1 has a 2-level address translation buffer, it may have an address translation buffer of any level as long as the access time and HW allow. The address translation buffers 120 and 130 are indexed to check if a virtual / real address translation pair is registered. If there is no error detected by the data check circuit 320 or 330, the obtained real address is used as it is. Then, the next operation is performed. Whether the virtual / real address translation pair is registered is determined by reading the virtual address part LA using a part of the virtual address register 110 as an address of the address translation buffers 120 and 130 and reading the read data and another virtual address register 110. And the comparison circuits 220 and 23
It is compared with 0, and if they match, it is determined to be registered, and if they do not match, it is determined to be unregistered. It is judged that the virtual / real address translation pair is always registered in one level or is in an unregistered state. Address translation buffer 120 having two levels
The LRU method which is determined by the replacement control circuit 140 and the read data of the LRU memory 150 holding the information for the replacement algorithm is used to determine which level of (1) and (130) is to be registered. If the virtual / real address translation pair has not been registered, the address translation buffer device 100 sends a real address generation request to the real address generation circuit 70.
The signal line 101 notifies 0. When the real address generation circuit 700 receives the real address generation request, it fetches data from the virtual address register 110, and refers to the address conversion table of the main memory several times if there is no cancel signal 601 from the error control information holding circuit 600. And get the real address. When the real address is obtained, the fact that the real address is obtained is notified to the address translation buffer device 100 via the signal line 701. Upon receiving this notification, the address translation buffer device 100 takes in the data from the real address generation circuit 700 via the signal line 702,
The virtual / real address translation pair is written in one of the two address translation buffers 120 and 130, and the address translation buffers 120 and 130 are indexed again. This time, since the virtual / real address translation pair is surely registered,
With the obtained real address, the data of the level at which the match is detected by the selector 340 is selected, the data of the real address is passed to the requested device, and the operation proceeds to the next operation.

By the way, the real address generation circuit 700 obtains the real address, and the address translation buffers 120 and 130 are obtained.
It is usual to add a parity bit for data integrity when writing a virtual / real address translation pair, or when initializing the address translation buffers 120 and 130. Although not particularly shown in this embodiment, the address translation buffers 120 and 130 or other registers,
A parity bit is also added to the memory for writing in bytes, and the address translation buffers 120 and 130 are also written.
At the time of indexing, the read data is taken into the data check circuits 320 and 330 at the same time, and the parity check is performed in byte units. When no error is detected here, the operation is performed as described above. Data check circuit 3
If an error is detected in 20, 330, the comparison circuit 220,
230 and the error control information holding circuit 600 are informed that an error has been detected. Upon receiving the error detection signal, the comparison circuits 220 and 230 output a non-coincidence signal and determine that the virtual / real address translation pair is not registered. If an error is detected by the data check circuits 320 and 330,
Subsequently, the error information holding circuits 420 and 430 already hold the error information for each byte unit and the error information detected this time in the comparing circuits 520 and 530, respectively,
When no error is detected at the same byte position, the error information holding circuits 420 and 430 hold error information for each byte position. Data check circuit 320, 330
Error detection and error information holding circuit 420, 43
The error information of 0 is stored in the address translation buffer 120,
As a result of indexing 130, it may be performed only when a translation pair of virtual / real addresses is registered, but in the present embodiment, when the address translation buffer is indexed, a check is always performed and error information is held. ..

The error control information holding circuit 600 holds the operation control information and the error information when the address translation buffer device 100 detects an error as described above, and the operation control information can be set by the diagnostic control circuit 800. is there. The operation control information includes degenerate operation information and error detection operation continuation information. The degenerate operation information is used to determine whether or not the degenerate operation of the address translation buffers 120 and 130 having multiple levels is possible. The error detection operation continuation information is used to determine whether or not the continuation operation is possible when the read error of the address translation buffers 120 and 130 is detected.

The error control information holding circuit 600 receives the error detection signals from the data check circuits 320 and 330, and outputs the error information for each byte held by the error information holding circuits 420 and 430 from the comparison circuits 520 and 530. If the error information detected this time is compared and a report that no error has been detected at the same byte position is received, if the error detection operation continuation information is confirmed and continuous operation is possible, the diagnostic control circuit 800 has an error. To report that. On the other hand, if the continuous operation is not possible, a cancel signal is sent to the real address generation circuit 700, and the diagnosis control circuit 800 is notified that there is an error. In parallel with these operations, the address translation buffer device 100 determines that the virtual / real address translation pair has not been registered due to the error detection by the data check circuits 320 and 330. Therefore, a real address generation request is issued to the real address generation circuit 700. Is informed. The subsequent operation of the real address generation circuit 700 and the address translation buffer device 100 is as described above.

Further, the error control information holding circuit 600 detects the error again by the check circuits 320 and 330, and the error information for each byte held in the error information holding circuits 420 and 430 and the error information detected this time. As a result of the comparison between the comparison circuits 520 and 530, if an error is detected at the same byte position, the degeneration operation information is confirmed, and if degeneration operation is possible, the replacement control circuit 140 is checked for the level at which the same error is detected. A degenerate operation instruction is sent to disconnect the address translation buffer 120 or 130, and the diagnostic control circuit 800 is notified that an error has occurred. At this time also, since the address translation buffer device 100 detects that the virtual / real address translation pair is not registered, the real address generation request is notified to the real address generation circuit 700. Real address generation circuit 70
0, the subsequent operation of the address translation buffer device 100 is as described above. On the other hand, if the degenerate movement is not permitted, a cancel signal is sent to the real address generation circuit 700.

Furthermore, the error control information holding circuit 60
0 is an address translation buffer 12 that can be used after detecting an error at the same byte position again during degenerate operation and disconnecting it.
If there is no 0 or 130, the real address generation circuit 70
A cancel signal is sent to 0, and the diagnostic control circuit 80
Report error to 0.

[0013]

As described above, according to the present invention, the address conversion buffer having a plurality of levels, the read data check circuit of the address conversion buffer, the error information holding circuit, the error information comparison circuit, the error control information holding circuit, and the real address are provided. By having a generation circuit, even if an error is detected during the reading of the address translation buffer, if it is not the same fault, the system can be stopped immediately or the performance can be reduced without degrading the performance by degenerate operation. There is.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

[Explanation of symbols]

 100 address conversion buffer device 110 virtual address register 120, 130 address conversion buffer 140 replacement control circuit 150 LRU memory 220, 230 comparison circuit 240 selector 320, 330 data check circuit 420, 430 error information holding circuit 520, 530 error information comparison circuit 600 Error control information holding circuit 700 Real address generation circuit 800 Diagnostic control circuit

Claims (1)

Claim: What is claimed is: 1. Whenever an address translation buffer for translating a virtual address into a real address is accessed, the contents of the replace memory are updated to record that the accessed data has been accessed most recently. However, if the required data does not exist in the address translation buffer, it is unregistered and a new real address for the virtual address is newly created and registered in the displaced position of the address translation buffer based on the contents of the replace memory. In an address translation buffer error processing system of an address translation buffer device, an address translation buffer of a plurality of levels, a check circuit for checking read data of the address translation buffer, and an error information holding circuit for holding error information from the check circuit And error information from the check circuit If there is no error at the same position in the comparison between the error information comparison circuit that compares the error information already stored in the error information storage circuit and this error information comparison circuit, continue processing as an unregistered virtual address. An address translation buffer error processing method, comprising: a control circuit for disconnecting the address translation buffer in which an error has occurred and performing degenerate operation to continue the processing when there is an error at the same position.