JPH10161939A - Memory control unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To use an entire module without being exchanged while keeping high reliability as it is and to prevent the degenerative operation of system even in case of memory down. SOLUTION: When an address to a memory 100 is received from a host system such as CPU or DMA, an address retrieving part 12 retrieves an address area 111 of a buffer 11 for substitution. When the address from the host system is retrieved from the buffer 11 for substitution by this address retrieving part 12, a read/write part 13 performs data read/write to the buffer 11 for substitution.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device that substitutes for a failed part of a memory and a cache memory.

[0002]

2. Description of the Related Art Conventionally, a system equipped with a memory has a SIMM (Single IN-li) as the memory to be mounted.
ne Memory Module), DIMM (Dual In-line Memory)
Module).

A system equipped with this memory has a parity check and an ECC (Er (Er)) in order to improve the reliability of the read / write access to the memory.
ror Checking and Correcting).

As described in Japanese Patent Publication No. 4-145557, there is a system equipped with a memory in which the use of a failed memory is excluded by address conversion.

[0005]

However, in a system equipped with such a conventionally existing memory,
Its memory is SIMM (Single IN-line Memor)
y Module), DIMM (Dual In-line Memory Module)
In the case where the memory is mounted, even if a part of the plurality of memories fails, it is necessary to replace the entire module, resulting in a problem that the cost is too large.

[0006] In a system equipped with such a conventional memory, a parity check and an ECC are required.
(Error Checking and Correcting), even if the failure location is within the range that can be handled by the ECC method, the failed address is not reliable as a data storage location. Because of the decrease, when high reliability is required, there is a problem that it is not possible to cope with the reliability.

[0007] Further, among the systems equipped with such a conventional memory, the system in which the use of the failed memory is excluded by the address translation requires the system to be degraded by the amount of the excluded memory. There was a problem that it had to be done.

Accordingly, the present invention has been made in view of the above-described problems, so that even if a memory fails, the entire module can be used with high reliability without being replaced as it is, and the system is not degraded. It is an object of the present invention to provide a memory control device having the above configuration.

[0009]

In order to achieve the above-mentioned object, the invention according to claim 1 comprises an alternative storage means for alternately storing data of a failed part in a memory.

According to a second aspect of the present invention, in the first aspect of the present invention, the alternative storage means is stored in an address area for storing an address of a fault location of the memory and in an address of the fault location of the memory. And a data area for alternately storing data to be stored.

[0011] The invention according to claim 3 is the invention according to claim 1 or 2.
In the invention described above, when an address for the memory is received from an upper system such as a CPU or a DMA, an address search means for searching the alternative storage means, and the address from the upper system is stored by the address search means. And read / write means for reading / writing data from / to the alternative storage means when the data is retrieved from the storage means.

The invention according to claim 4 is the invention according to claim 1 or 3.
In the invention described above, the remaining area in which the substitute storage means stores the data of the failed part in the memory is a write buffer area.

According to a fifth aspect of the present invention, in the fourth aspect of the present invention, the alternative storage means includes an address area for storing a failed address in the memory and an address as the write buffer; A data area for storing the data to be stored at the address of the location and the data of the write buffer, and the data stored in the data area being replacement data when the memory fails or data of the write buffer. And a status area for storing a status flag indicating whether the

According to a sixth aspect of the present invention, there is provided an address area for storing an address of a faulty location of a memory and a relocation address area for storing an address for alternately storing data of the faulty location of the memory in a predetermined location on the memory. And relocation address storage means having the following.

According to a seventh aspect of the present invention, in the invention of the sixth aspect, when an address for the memory is received from a host system such as a CPU or a DMA, the address retrieving means retrieves the relocation address storage means. When the address from the upper system is searched from the relocation address storage means by the address search means,
And a relocation address reading means for reading a relocation address replacing the failed address from the relocation address storage means.

According to an eighth aspect of the present invention, when an address from a CPU is received by a substitute storage means provided in a cache memory for substituting and storing data of a failed portion in the memory, the substitute storage means is provided. Address search means for searching for means, and the CPU
And read / write means for reading / writing data from / to the alternative storage means when the address from is retrieved from the alternative storage means.

According to a ninth aspect of the present invention, in the system according to the eighth aspect, in a system in which a DMA controller and a plurality of CPUs perform parallel processing, the DMA controller and a plurality of CPUs are provided as a pair with a cache memory at a location adjacent to each CPU. .

According to a tenth aspect of the present invention, there is provided an alternative storage means for alternately storing a failed part in a memory;
When an address for the memory is received from an upper system such as A, an address search means for searching the alternative storage means, and when an address from the upper system is searched from the alternative storage means by the address search means, The memory includes read / write means for reading / writing data from / to the alternative storage means, and memory test means for testing a failed portion in the memory stored in the alternative storage means.

According to an eleventh aspect of the present invention, in the invention of the tenth aspect, the memory test means generates a test address for the memory, and a location of the test address in the memory. Test data generating means for generating test data to be written into the memory, and data comparing means for comparing test data generated by the test data generating means with data read from the test data written at the test address in the memory. If the data comparing means determines that the data read from the test data written at the test address in the memory is different from the test data generated by the test data generating means, Test address writing means for writing a test address to the storage means

According to a twelfth aspect of the present invention, in the invention of the eleventh aspect, the address generating means sequentially outputs the addresses from address 0 to the maximum address.

According to a thirteenth aspect of the present invention, in the tenth or eleventh aspect, the memory test means comprises:
A data storage device has a save buffer, and saves data stored at the test address location in the memory to the save buffer before writing to the test address location in the memory.

According to a fourteenth aspect of the present invention, an alternative storage means for alternately storing a failed part in a memory;
When an address for the memory is received from an upper system such as A, an address search means for searching the alternative storage means, and when an address from the upper system is searched from the alternative storage means by the address search means, A read / write unit for reading / writing data from / to the alternative storage unit and an address line disconnection inspection unit for inspecting a disconnection of an address bus connecting the memories.

According to a fifteenth aspect of the present invention, in the invention of the fourteenth aspect, the address line disconnection inspecting means generates a test address for the memory, and the test address in the memory. Test data generating means for generating test data to be written to the location, and data for comparing test data generated by the test data generating means with data read from the test data written at the test address location in the memory. The comparing means, based on a comparison result between the data read from the test data written at the test address location in the memory and the test data generated by the test data generating means, compared by the data comparing means, A disconnection determination method for determining whether there is a disconnection in the address bus connecting the memories. With the door.

According to a sixteenth aspect of the present invention, in the invention according to the fifteenth aspect, when the test address generating means tests the address line A0, it generates test addresses of addresses 0 and 1. The address line Ai (i
= 1, 2, 3, 4, when inspecting ···· n-1) generates a test address at address 0 and ^{A i} address.

According to a seventeenth aspect of the present invention, in the invention according to the fifteenth aspect, when the disconnection determining means receives the coincidence state of the test data for the address 0 and the address 1 from the data comparing means, Only when the information that address 1 and address 1 match is received, it is determined that there is no disconnection in address line A0. On the other hand, information that any one of address 0 and address 1 does not match is determined. If received, it is determined that there is a break in the address line A0,
Further, the address 0 and 2i (i
= 1, 2, 4,..., N-1) When receiving the coincidence state of the test data for the address, only when the information indicating that the address 0 and the address 2i coincide with each other is received,
While it is determined that there is no disconnection in the address line Ai, if information indicating that any one of the addresses 0 and 2i does not match is received, it is determined that there is a disconnection in the address line Ai.

According to an eighteenth aspect of the present invention, in the invention according to the fourteenth or seventeenth aspect, if the test data is configured such that one word of the memory is composed of n bits, all the test data to be written to the address 0 is all Is stored in the bits of 2i (i = 0, 1, 2,.
In the case of the address at 3, 3,..., N-1),
"1" is stored, and "0" is stored in the other bits.

According to a nineteenth aspect of the present invention, in the invention of the fourteenth aspect, the address line disconnection inspection means has an evacuation buffer, and the address line disconnection inspection means is configured to write the address line break before writing to the test address location in the memory. The data stored at the test address in the memory is saved in the save buffer.

According to a twentieth aspect of the present invention, in the invention according to the fourteenth aspect, the address bus between the memories is checked by the address line disconnection inspection means before the faulty address in the memory is replaced by the alternative storage means. Disconnection is detected.

According to a twenty-first aspect of the present invention, there is provided an alternative storage means for alternately storing a failed part in a memory, and a CPU, a DM,
When an address for the memory is received from an upper system such as A, an address search means for searching the alternative storage means, and when an address from the upper system is searched from the alternative storage means by the address search means, A read / write means for reading / writing data from / to the alternative storage means and an address line short-circuit check means for checking a short-circuit of an address bus connecting the memories.

According to a twenty-second aspect of the present invention, in the invention of the twenty-first aspect, the address line short-circuit inspection means comprises:
Clear address generating means for generating a clear address for the memory, test address generating means for generating a test address for the memory, and clear data generating for generating clear data to be written to the location of the clear address in the memory Means, test data generating means for generating test data to be written to a test address location in the memory, and data obtained by reading clear data written to the clear address location in the memory;
Data comparison means for comparing the test data generated by the test data generation means with the data obtained by reading the clear data written at the location of the clear address in the memory and compared by the data comparison means And short-circuit judging means for judging whether or not the address bus connecting the memories is short-circuited based on the above.

According to a twenty-third aspect of the present invention, in the twenty-second aspect of the present invention, the clear address generating means generates addresses 0, 1, 2, 4,... And 2n-1 in the memory. Then, the test address generator generates the address line Ai (i = 0, 1, 2, 3,..., N-1).
Is checked to see if it is short-circuited with another address line k (k ≠ i), the address of the address 2i in the memory is generated.

According to a twenty-fourth aspect of the present invention, in the twenty-second aspect of the present invention, the short-circuit determination means determines that the address line Ai (i = 0, 1, 2, 3,... When it is determined whether or not the line Ak (k と i) is short-circuited, the bit bi constituting the data read from the address 2k of the memory is not “0” but “1”.
When it is determined that the address line Ai and the address line Ak are short-circuited.

According to a twenty-fifth aspect of the present invention, in the invention of the twenty-second aspect, all bits of the clear data are "0", and all bits of the test data are "1".

According to a twenty-sixth aspect of the present invention, in the invention of the twenty-first aspect, the address line short-circuit inspection means comprises:
It has an evacuation buffer for short-circuit inspection, and saves data stored in the memory to the evacuation buffer before short-circuit inspection. .

According to a twenty-seventh aspect of the present invention, in the invention according to the twenty-first aspect, the address bus between the memories is addressed by the address line short-circuit inspection means before the faulty address in the memory is alternately processed using the alternative storage means. Disconnection is detected.

According to a twenty-eighth aspect of the present invention, an alternative storage means for alternately storing a failed part in a memory;
When an address for the memory is received from an upper system such as A, an address search means for searching the alternative storage means, and when an address from the upper system is searched from the alternative storage means by the address search means, Read / write means for reading / writing data from / to the alternative storage means; and verify means for comparing the data with the data read after writing the data when writing the memory data. Is provided.

According to a twenty-ninth aspect, in the twenty-eighth aspect of the present invention, the verifying means stores an address area for storing an address of data to be written to the memory, a data area for storing data to be written to the memory, and Is written in the memory, and the data storage means is a verify data area for storing the read verify data again, and data data to be written in the memory stored in the data area of the data storage means.
Comparing means for comparing the verify data stored in the verify data area; and comparing the data data written to the memory with the verify data stored in the verify data area,
When the write data and the verify data do not match, an address writing means for writing an address of the write data to the memory as a failed portion in the memory to the alternative storage means.

According to a thirtieth aspect of the present invention, there is provided an alternative storage means for alternately storing data of a fault location occurring in a block unit in a memory.

According to a thirty-first aspect of the present invention, in the thirty-first aspect of the present invention, the substitute storage means stores a reference position area for storing a reference position indicating a position of a failed block in the memory, It has a status area for storing a status indicating the state of the reference position of the block, and a data area for alternately storing data to be stored in the failed block in the memory.

According to a thirty-second aspect of the present invention, in the thirty-first aspect of the present invention, the reference position is a position of a central axis of an area obtained by dividing the storage area of the memory by a predetermined width in the vertical and horizontal directions.

According to a thirty-third aspect of the present invention, in the thirty-second aspect of the present invention, when the faulty block in the memory is within a division range which is a predetermined central axis, the range for alternately storing the faulty block is defined as The division range is the central axis.

According to a thirty-fourth aspect of the present invention, a reference position area for storing a reference position of a failed block in a memory and a range for alternately storing data of the failed block in the memory at a predetermined location in the memory are designated. A relocation address storage unit having a relocation range designation area.

According to the present invention, the substitute buffer as the substitute storage means stores data of a failed part in the memory in place of the data, so that it can be used even if the memory fails.

In particular, when an address for accessing the memory is received from a host system such as a CPU or a DMA, an alternative buffer is searched. If the address is found, data is read from the alternative buffer.・ Write.

Further, when the remaining area where the replacement buffer stores the data of the failed part in the memory is set as a write buffer area, it can be used as a write buffer.

Further, since the memory test means is provided, a failed portion in the memory stored in the substitute buffer can be tested in advance.

Further, in addition to the provision of the substitute buffer, the address line disconnection inspecting unit inspects the disconnection of the address bus connecting the memories.

Further, in addition to the provision of the substitute buffer, the address line short-circuit inspecting means inspects a short circuit between the address buses connecting the memories.

[0049]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a memory control device according to the present invention will be described below with reference to the drawings.

<First Embodiment> FIG. 1 is a schematic explanatory view of a first embodiment of a memory control device according to the present invention.
FIG. 2 is a block diagram showing the configuration of the first embodiment of the memory control device according to the present invention.

The memory control device 1 according to this embodiment has a structure shown in FIG.
As shown in FIG. 7, a replacement buffer 11 for replacing data of a failed portion (address N) in the memory 100 and storing the data.
(Alternative storage means).

Then, the memory control device 1 of this embodiment
When a read / write access occurs to a failed address of the memory 100 from a host system (hereinafter, simply referred to as a host system) such as a CPU or a DMA controller, the corresponding buffer 11 is used instead of the host system. Read / write access is made to the location.

The memory control device 1 of this embodiment is different from that of FIG.
As shown in (1), it is configured to include the above-mentioned replacement buffer 11, an address search unit 12, a read / write unit 13, and an address buffer 14.

The substitute buffer 11 has a TLB (Translat
ion Look ahead Buffer) is used as a storage medium, and has an address area 111 for storing the address of a fault location in the memory 100 and a data area 112 for alternately storing data to be stored at the address of the fault location. It is.

Here, of the addresses and data stored in the address area 111 and the data area 112, each address and one of data corresponding to this address are stored.
The set is called an entry.

Upon receiving an address for the memory 100 from the upper system (hereinafter referred to as the upper system address), the address search unit 12 searches the address area 11 in the substitute buffer 11 using the received upper system address as a key. It is configured.

When the address search unit 12 searches using the upper system address as a key and finds that the address as this key exists in the substitute buffer 11,
Substitution buffer 1 for storing the upper system address
1 is output to the read / write unit 13, while if no address is detected, the upper system address temporarily stored in the address buffer 14 is output to the memory 100. The instruction is output to the address buffer 14.

When the read / write unit 13 receives the address of the substitute buffer 11 storing the upper system address from the address search unit 12, the read / write unit 13 reads / writes data from the received address of the substitute buffer 11.
It is configured to perform a write process.

The address buffer 14 temporarily stores an address for reading / writing from the host system to the memory 100. The address buffer 14 outputs the stored address to the memory 100 in accordance with an instruction from the address search unit 12. It is configured.

Next, the operation of the memory control device 1 of this embodiment will be described.

The memory 100 from the host system such as the CPU
When the address search unit 12 receives an upper system address for read / write access to the address, the address search unit 12 searches the address area 111 of the substitute buffer 11 using the upper system address as a key.

When the address search unit 12 finds a higher system address in the address area 111 as a result of the search, the address search unit 12 outputs to the read / write unit 13 the address of the substitute buffer 11 that stores the higher system address. .

When the read / write unit 13 receives an address of the substitute buffer 11 for storing the upper system address from the address search unit 12, the read / write unit 13 stores the address in the data area 112 of the address when performing the read access. The data on the data bus 32
In the case of a write access, data from the upper system received via the data bus 32 is written to the address area 112.

On the other hand, if the address search unit 12 does not detect a higher system address in the address area 111, it outputs the higher system address temporarily stored in the buffer 14 to the memory 100. And give instructions.

When receiving an instruction from the address search unit 12, the address buffer 14 outputs the temporarily stored address to the memory 100.

When receiving the upper address temporarily stored in the address buffer 14, the memory 100 reads and writes the data stored at this address.

The control signal for reading / writing is not shown, but it goes without saying that it is output from the host system every time reading / writing is performed.

According to the memory control device 1 of this embodiment, the replacement buffer 11 stores data of a failed part in the memory 100 in place of the failed buffer.
It is not necessary to replace 00, so that repair costs can be reduced, and the reliability of the system is not reduced.

<Second Embodiment> FIG. 3 is a block diagram showing a configuration of a substitute buffer in a second embodiment of the memory control device according to the present invention.

The memory control device of the second embodiment has the same configuration as that of the memory control device of the first embodiment except for the substitute buffer 11.

Accordingly, detailed description of the same components as those of the memory control device of the first embodiment will be omitted, and only the substitute buffer 21 will be described.

The substitute buffer 21 uses a TLB as a storage medium, and as shown in FIG.
Address area 211 for storing a failed address in address 0 and an address as a write buffer;
A data area 212 for storing data to be stored at the address of the failure location of 0 and other data to be stored as a memory (write buffer), and data stored in this data area when the memory 100 fails. Status area 2 for storing a status flag indicating whether it is replacement data or write buffer data
13 are provided.

Here, among the addresses, status flags, and data stored in the address area 211, status area 213, and data area 212, a set of each address, status flag, and data is called an entry.

According to the memory control device of this embodiment,
Since the substitute buffer 21 has the status area 213, the substitute buffer 21 can be used as a write buffer if necessary.

<Third Embodiment> FIG. 4 is a schematic explanatory view of a third embodiment of the memory control device according to the present invention.
FIG. 5 is a block diagram showing the configuration of the third embodiment of the memory control device according to the present invention.

The memory control device 1 of this embodiment is different from that of FIG.
As shown in FIG. 7, an address area 331 for storing the address of a failure location (address N) of the memory 100,
And a relocation address table 332 (relocation address storage means) having a relocation address area 332 for storing the address of the relocation area 101 on the memory 100 for alternately storing the data of the fault location.

Then, the memory control device 1 of this embodiment
When a read / write access occurs to a failed address of the memory 100 from the host system, the address of the memory 100 is read / written based on the relocation address table 33.

The memory control device 1 of this embodiment is different from that of FIG.
As shown in FIG. 2, the buffer 11 includes the above-described buffer 11, the address search unit 12, the above-described relocation address table 33, the address reading unit 34, and the address buffer 14.

Here, among the components of the memory control device according to this embodiment, the same components as those of the first embodiment are denoted by the same reference numerals, and hereinafter, these components will be described. A detailed description of is omitted.

When the address reading unit 34 receives from the address search unit 12 an instruction that the address specified by the upper system is stored in the relocation address table 33, the address reading unit 34 reads from the address relocation table 33 from the upper system. It is configured to read a relocation address for relocating the address to the relocation area 101 in the memory 100.

When the address read unit 34 reads the arrangement address from the relocation address table 33 as described above, it outputs this to the address buffer 14 and instructs the memory 100 to output this relocation address. Is output to the address buffer 14.

Next, the operation of the memory control device 1 of this embodiment will be described.

When the address search unit 12 receives an upper system address for reading / writing from / to the memory 100 from the upper system, the address search unit 12 searches the address area 331 of the relocation address table 33, and It detects whether the address is stored.

When the address is detected from the address area 331 as a result of the search, the address search unit 12 outputs the detected address of the relocation address table 33 to the address reading unit 34.

When receiving the relevant address of the relocation address table 33 from the address search unit 12, the address reading unit 34 reads the relocation address of the memory 100 stored in the relocation address area 332, and stores it in the address buffer. 14 and stored in the address buffer 14.

Thereafter, the address reading section 34 stores the rearranged address stored in the address buffer 14 in the memory 10.
Output an instruction to output 0.

When receiving an instruction from the address reading unit 34, the address buffer 14 outputs the temporarily stored relocation address to the memory 100.

When receiving the relocation address from the address buffer 14, the memory 100 performs read / write processing based on this address.

In this embodiment, too, it goes without saying that a control signal for reading / writing is output from the host system every time reading / writing is performed, although not shown.

According to the memory control device of this embodiment,
The replacement buffer constituting the memory control device according to the first or second embodiment is provided as the relocation area 101 in the memory 100 itself.
0 in the relocation area 1 of the memory 100
Since the rearrangement is performed at the predetermined address 01, the required circuits can be reduced as compared with the memory control devices of the first and second embodiments, and the configuration of the memory control device is simplified.

Therefore, an unnecessary portion can be used for adding an address entry, and the number of faults that can be handled can be increased.

<Fourth Embodiment> FIG. 6 shows a sixth embodiment according to the present invention.
FIG. 7 is a layout diagram of a memory control device according to the embodiment, FIG. 7 is a configuration diagram of a substitute buffer, and FIG. 8 is a block diagram illustrating a configuration of a memory control device of a sixth embodiment according to the present invention.

The memory control device 1 of this embodiment is different from that of FIG.
As shown in (1), when a failure occurs in the memory 100, the address of the failed memory is not accessed, and the replacement buffer 120 for storing the address of the failure location of the memory 100 in the cache memory 110 is provided. It is intended to be performed.

As shown in FIG. 7, the replacement buffer 120 has an address area 121 for storing the address of the read instruction on the memory 100 and a failure of the address of the read instruction on the memory 100. Status area 122 for storing a status flag indicating whether or not there is an instruction, and an instruction area 1 for storing an instruction read from the memory 100.
23.

The memory control device 1 of this embodiment is different from that of FIG.
As shown in (1), it has a configuration similar to that of the memory control device of the first and second embodiments, and therefore, detailed description thereof is omitted.

The memory control device 1 of this embodiment
When the replacement buffer 120 of the cache memory 110 is full and replacement is required, the entry data of the failed memory is stored in the cache memory 110 by referring to the status flag stored in the status area 122. Not to be swept away from

The memory control device 1 of this embodiment
Similarly, when performing copyback, referring to the status flag stored in the status area 122,
Copyback to the cache memory 110 is not performed for the entry corresponding to the failed memory address.

As shown in FIG. 8, for example, in a system configured by the DMA controller 5 and a plurality of CPUs 2 to perform parallel processing, the memory control device 1 and the cache memory 110 form a set and are arranged adjacent to the CPU 1. Each memory control device 1 executes the above-described processing. The memory controller 4 has a memory 100 (DR
AM) to perform refresh processing.

<Fifth Embodiment> FIG. 10 is a schematic diagram for explaining the processing of a memory control device according to a fifth embodiment of the present invention, and FIG. 11 is a schematic diagram of the memory control device of the fifth embodiment according to the present invention. FIG. 3 is a block diagram illustrating a configuration.

The memory control device 1 of this embodiment is different from that of FIG.
As shown in FIG. 2, the memory test unit 5 includes a memory test unit 5 which performs a replacement process on a faulty address in the memory 100 using a replacement buffer.
A failure address in the medium is found and stored in a substitute buffer.

That is, the memory test unit 5
From 0, the data stored at the address to be tested is read and saved in a save buffer to be described later. Then, after the test data is written to this address, the written test data is read again, and the test data and the memory 1 are read.
By comparing with the test data read from 00,
It is designed to test whether the corresponding address of the memory 100 has failed.

Then, the memory test section 5 compares the two in the above-described manner, and then returns the save data stored in the save buffer to the original address of the memory 100 again.

If the memory test section 5 reads the data at the same address immediately after writing the test data to the memory 100, the data remaining on the data bus may be read. Until you have access to it.

The memory control device 1 of this embodiment is different from the memory control device shown in FIG.
As shown in FIG. 1, the system includes an alternative buffer 11, an address search unit 12, a read / write unit 13, an address buffer 14, and the memory test unit 5 described above.

Here, among the components of the memory control device according to this embodiment, the same reference numerals are given to the same components as those of the first embodiment. A detailed description of is omitted.

The memory test section 5 includes an access control section 51 for controlling each component, a test address generation section 52, a save buffer 53, a test data generation section 54, a data comparison section 55, and an address writing section 56. ing.

The test address generator 52 is provided in the memory 10
Addresses from address 0 to the maximum address of 0 (hereinafter referred to as a test address) are sequentially generated, and the generated test address is output to the address bus 31 and the fact that this test address has been output is output to the access control unit 52. It is configured to be.

When receiving an instruction from the access control unit 52 that the save data has been stored in the save buffer 53, the test address generation unit 52 writes the test data generated by the test data generation unit 54, so The address of the saved data is generated, and the generated address is output to the address bus 31 and the fact is output to the test data generating unit 54.

Further, the test address generator 52 is configured to generate the address and output it to the address bus 31 in order to read the test data written in the memory 100 from the access controller 52.

Further, test address generating section 52
Generates an address for returning the saved data saved in the save buffer 53 to the original address of the memory 100 when the memory test is completed, and outputs the address to the address bus 31 and performs access control to that effect. Part 52
Is configured to be output.

The save buffer 53 stores the save data obtained as described above and its address in the memory 100.

Upon receiving an instruction from test address generation section 52 to output an address for writing test data to memory 100 (an address included in save data), test data generation section 54 converts the test data using random numbers. The generated test data is output to the access control unit 52 and is output to the data comparison unit 55.

The data comparing section 55 compares the test data from the test data generating section 54 with the data (hereinafter referred to as test read data) written in the memory 100 and reading the written test data again. ,
As a result, when both data match, an instruction is issued to the test address generation unit 52 to return the saved data saved in the save buffer 53 to the original address of the memory 100. If both data do not match, the address is written to the address writing unit 54.
Is configured to be output.

When receiving an instruction indicating that the two data do not match, the address writing unit 54 reads out the address where the saved data is stored from the saved address buffer 53, and reads the address in the substitute buffer 11 The save data saved in the save buffer 53 is written to the area 111 and sent to the test address generator 52.
It is configured to issue an instruction to return to the original address of the memory 100.

Next, the operation of the memory control device according to the fifth embodiment will be described.

The description of the similar operation of the memory control device of the first embodiment, that is, the alternative operation for the data of the failed address in the memory 100 is omitted, and the operation for testing the failure of the memory 100 will be described. I do.

When the memory control device 1 receives an instruction from the host system to execute a memory test of the memory 100, the test address generator 52 first starts address 0 of the memory 100 based on the instruction of the access controller 51. To read the stored data, 0
The address of the address is generated, the generated test address is output to the address bus 31, and the address is output to the access control unit 52.

Thereafter, when the data stored at the address 0 of the memory 100 is received, this data and the address where the data is stored, that is, the address 0, are stored in the save buffer 53.

Next, the test address generating section 52 stores the test data at the address 0 of the memory 100 in which the save data is stored, based on the instruction of the access control section 51, so that the address consisting of the address 0 is again stored. This is output to the address bus 31, and the fact is output to the access control unit 52.

Then, the test data generator 54 generates test data using random numbers according to the instruction of the access controller 51, outputs the generated test data to the data comparator 55, and outputs the test data to the memory 100 via the data bus 32. The received data is written to the address 0.

Next, the test address generator 52 generates the address of address 0 again in order to read the test data written to the address 0 of the memory 100 in accordance with the instruction of the access controller 51, and transfers this to the address bus 31. To the access control unit 52.

After that, the data comparing section 55
Upon receiving the data read from the test data written at the address 0, the read data is compared with the test data.

As a result, if both data match, the data comparison unit 55 outputs the fact to the access control unit 51. If both data do not match, the two compare. The information to the effect that no match has been made is output to the address writing unit 56.

If both data match, the test address generator 52 stores the data saved in the save buffer 53 based on the instruction from the access controller 51 at the address (address 0) of the original memory 100. Outputs the address for returning to. Thereafter, the save data stored in the save buffer 53 is written to the original address 0 of the memory 100 via the data bus 32.

On the other hand, if the two data do not match, the address writing unit 56 reads the address 0 of the memory 100 from the save buffer 53 based on the instruction of the access control unit 51, The data is written to the address area 111, and the fact is output to the access control unit 51.

The test address generator 52 outputs an address for returning the saved data saved in the save buffer 53 to the original address (address 0) of the memory 100, based on the instruction of the access controller 51, as described above. After that, the save data stored in the save buffer 53 becomes
It is written to address 0 of the original memory 100.

Thereafter, the access control unit 51 issues an instruction to output the next test address (address 1), and thereafter, tests the memory 100 for a failure up to the maximum address of the memory 100 in the same manner.

In the memory control device 1 of this embodiment, the data comparing section 55 uses the test data generated by the test data generating section 54 and the memory 10 in which the test data is written.
0 by comparing the data read from the memory 1
00 fault locations can be tested in hardware.

Therefore, the memory control device 1 of this embodiment
By executing this memory test before the execution of the program, it is possible to quickly detect a memory failure and switch to the substitute buffer 11.

Further, in the memory control device 1 of this embodiment, since the memory test is performed by hardware as described above, when the memory is tested in the background by the OS, the memory control device 1 is not limited to the version upgrade of the OS. This eliminates the case where the generated memory test is not executed.

Further, the memory control device 1 of this embodiment
Since virtual memory is not used unlike the case where the memory is tested in the background by the OS, it is possible to easily grasp which part of the memory is actually being tested.

Furthermore, in the memory control device 1 of this embodiment, if this memory test is run between normal program executions, the original program execution is not hindered.

Further, in the memory control device 1 of this embodiment, since the memory test is performed by hardware as described above, exception processing such as error processing is performed as in the case where the memory is tested by the OS in the background. Occurs, there is no restriction that the exception processing must be prioritized over the memory test, so that there is no problem such as a response.

<Sixth Embodiment> FIG. 12 is a schematic explanatory view of a memory control device according to a sixth embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a memory control device according to a sixth embodiment of the present invention.

The memory control device 1 of this embodiment is different from that of FIG.
As shown in FIG. 2, an address line disconnection inspection unit 6 is provided, and a failed address in the memory 100 is stored in the replacement buffer 1.
Before performing the substitution processing using the address line 1, the address line disconnection inspection unit 6
Detect the disconnection of the address lines (A0, A1, A2,... An-1) constituting the address bus 31 between the memories 100.

In other words, the address line disconnection inspection section 6 writes different test data in the memory 100 at addresses 0 and 1 respectively for the disconnection inspection of the address line A0, and then reads these data again. Are both the same as the test data,
It detects that the address line A0 is not disconnected.

Similarly, for the address line A1, the address line disconnection inspection unit 6 writes different test data in the memory 100 at addresses 0 and 2, respectively, and then reads these data again. , If both are the same as the test data, the address line A
1 is detected so as not to be disconnected.

[0138] The address lines Ai, the address line break detecting section 6, similar, that different test data with each other, after writing the memory 100 to it that address 0 and 2 ⁱ address, read these data again again However, when both are the same as the test data, it is detected that the address line Ai is not disconnected.

As shown in FIG. 13, the control device of this embodiment includes an alternative buffer 11, an address search unit 12,
It comprises a read / write section 13, an address buffer 14, and an address line disconnection inspection section 6.

Here, among the components of the memory control device according to this embodiment, the same reference numerals are given to the same components as those of the first embodiment. A detailed description of is omitted.

The address line disconnection inspection unit 6 includes an access control unit 61 for controlling each component and a test address generation unit 6
2, a save buffer 63, and a test data generator 64
, A data comparing section 65 and a disconnection determining section 66.

The test address generator 62 is provided in the memory 10
Address 0 or 2 ⁱ (i = 1, 2, 3,..., N−
1) When writing test data, which will be described later, to any location of the address, a read address is read to save the data stored in this location to the save buffer 63, and to write to the original location after the test is completed. Is generated.

Further, the test address generator 62 outputs the address 0 or 2 ⁱ (i = 1, 2, 3,...) Of the memory 100.
(N-1) A write address for writing test data is generated at any location of the address, and a read address for reading the written test data is generated.

The save buffer 63 saves data stored in the memory 100 in order to prevent the test data from being written to the memory 100 and lost.

The test data generator 64 is provided in the memory 100
The test data to be written to addresses 0 and 2 ⁱ (i = 1, 2, 3,..., N−1) are generated as data as shown in FIG.

In the test data shown in FIG. 14, if one word of the memory 100 is composed of n bits, the test data to be written to the address 0 has "0" stored in all bits. And 2 ⁱ (i = 0, 1, 2,
In the case of the address at 3, 3,..., N-1),
"1" is stored, and "0" is stored in the other bits.

The test data comparing section 65 is provided in the memory 100
The test data written in the predetermined location is compared again with the test data to determine whether or not the test data matches, and the result is output to the disconnection determination unit.

The disconnection judging section 66 sends the address 0 and 2 ⁱ (i = 1, 2, 4,...) Of the memory 100 from the data comparing section 65.
When ··· n-1) receives a matching status of the test data for address, only when receiving the information of the that both match the address 0 and 2 ⁱ address, the address lines Ai is not broken determining, while outputting the determination result to the host system, of the address 0 and 2 ⁱ address, if one has been received the information that no match, the address lines Ai is broken Judgment is made and this result is output to the host system.

Next, the operation of the memory control device according to the sixth embodiment will be described.

The description of the same operation of the memory control device of the first embodiment, that is, the alternative operation to the data of the failed address in the memory 100 is omitted, and the disconnection inspection of the address bus 31 between the memories 100 is omitted. The processing will be described.

Upon receiving an instruction from the host system to check the disconnection of the address bus 31 between the memories 100, the test address generator 62 first reads data stored at address 0 of the memory 100 and saves the data. Memory 1
00 address is generated, and the generated 0 address is output to the address bus 31.
The address is output to the access control unit 61.

Thereafter, the access control unit 62 stores the memory 1
When the data stored at the address 0 of 00 is received, the received data and the address 0 at which the data is stored are saved in the save buffer 63, and the fact is sent to the test address generator 62. Output.

Then, the test address generator 62 generates an address having the address 0 again to store the test data at the address 0 of the memory 100 in which the saved data is stored, and transfers the address to the address bus 31. At the same time, the information is output to the access control unit 61.

Then, the test data generating section 64 generates the above-described test data based on the instruction to the access control section 61, outputs this to the address 0 of the memory 100 via the data bus 32, and Comparison section 65
Output to

Next, based on the instruction from the access control unit 61, the test address generation unit 62 generates the address of the address 0 again to read the test data written at the address 0 of the memory 100, and transfers it to the address bus. 31 and to the access control unit 61 to that effect.

Thereafter, based on the instruction from the access control section 61, the data comparison section 65 compares the data read from the test data written at the address 0 of the memory 100 with the test data.

As a result, when both data match, the data comparing unit 65 outputs information indicating that both match to the disconnection determining unit 66, but both data do not match. In this case, information indicating that they do not match is output to the disconnection determination unit 66.

After that, the test address generator 62 sends an address for returning the saved data saved in the save buffer 63 to the original location of the memory 100 (address 0) based on the instruction of the access controller 61. 31. Thereafter, the data stored in the save buffer 63 is written to the original memory 100 at the address 0.

Thereafter, the test address generating section 62 generates an address of the first address to save the data stored at the first address of the memory 100 based on the instruction of the access control section 61, and outputs the address to the address bus 31. Output.

After that, the access control section 61 saves the data stored at the address 1 in the memory 100 in the save buffer 63 in the same manner as described above, and outputs the fact to the test address generating section 62. .

Then, the test address generator 62 generates the address 1 again to write the test data to the address 1 of the memory 100 and outputs this to the address bus 31.

Subsequently, the test data generating section 64 generates the above-described test data (data for the first address) based on the instruction of the access control section 61, outputs the test data to the data bus 32, and outputs the test data. Write to address 1 of memory 100.

Next, the test address generator 62 generates the address of the address 1 again to read out the test data written at the address 1 of the memory 100, outputs this address to the address bus 31, and indicates that. Is output to the access control unit 61.

After that, the data comparison section 65
When receiving the data read from the test data written at the address 0, the data read from the test data written at the address 1 in the memory 100 is compared with the test data.

As a result, when both data match, the data comparing unit 65 outputs information indicating that both match to the disconnection judging unit 66, and sends the information to the test address generating unit 62. Then, while outputting an instruction for returning the evacuation data saved in the evacuation buffer 63 to the address 1 of the memory 100, if they do not match, the information indicating that they do not match is determined as a disconnection. Part 6
6 is output.

Thereafter, as described above, the data stored in the save buffer 63 is restored to the original memory 10 again.
Write to address 0.

When the disconnection judging section 66 receives from the data comparing section 65 the coincidence of the test data for the addresses 0 and 1 of the memory 100, the disconnection judging section 66 receives the information that both the addresses 0 and 1 match. Only in this case, it is determined that the address line A0 is not disconnected, and the result of this determination is output to the system, and the fact is output to the address generator 62.

On the other hand, the disconnection judging section 66 calculates the addresses 0 and 1
If information indicating that any one of the addresses does not match is received, it is determined that the address line A0 is disconnected, and this result is output to the above system, and the fact is notified to the address generation unit. 62.

The disconnection inspection for the address line 0 has been completed as described above. Thereafter, (address 0, address 1), (address 0, 2
(Address 0), (address 0, address 4), ... (address 0, 2
By performing the same processing as described above in the order of ( ^n-1 ), disconnection inspection of the address line A1, the address line A2, the address line A4,..., the address line An-1 is sequentially performed.

In the memory control device 1 of this embodiment, since the replacement memory 11 is provided for the failed memory and the address line disconnection inspection unit 6 is further provided, the failure of the memory 100 occurs due to the failure of the address line. It is possible to detect whether the error has occurred or the memory 100 itself has failed.

<Seventh Embodiment> FIG. 15 is a schematic explanatory view of a memory control device according to a seventh embodiment of the present invention.
FIG. 6 is a block diagram showing a configuration of a memory control device according to a seventh embodiment of the present invention.

The memory control device 1 of this embodiment is different from the memory control device shown in FIG.
As shown in FIG. 5, the address line short-circuit inspection unit 7 has an address line short-circuit inspection unit 7 before the faulty address in the memory 100 is subjected to the substitution process using the substitution buffer 11. A short circuit between address lines (A0, A1, A2,..., An-1) constituting the bus 31 is detected.

As shown in FIG. 16, the control device 1 of this embodiment includes an alternative buffer 11 and an address search unit 12.
, Read / write unit 13 and address buffer 14
And an address line short inspection section 7.

Here, among the components of the memory control device according to this embodiment, the same reference numerals are given to the same components as those of the first embodiment. A detailed description of is omitted.

The address line shorting inspection section 7 includes an access control section 71 for controlling each component, a test address generation section 72, a save buffer 73, a clear / test data generation section 74, and a data comparison section 75. , And a short determination unit 76.

The test address generating section 72 is provided to save the stored data, restore the saved data, write clear data to be described later, and read the clear data in the short check. , 0, 1, 2, 4,... And 2 in the memory 100
^{In order} to read data from address ^n-1 (hereinafter referred to as “inspection address”) and write data in these locations, the address of the inspection address is output to the address bus 31.

The test address generator 72 writes test data, which will be described later, into one of the test use addresses (hereinafter referred to as “test use address”), and reads data from that location. The address of the test address is output.

The save buffer 73 stores the data stored at the test use address in order to avoid clear data being written and the data stored at the test use address disappearing.

If one word of the memory 100 is composed of n bits, the test / clear data generating unit 74 clears the test use address of the memory 100 when performing the short test. As shown in a), clear data in which all bits are "0" is output.

The clear / test data generating section 74
As shown in FIG. 17A, all bits are "
In addition to outputting clear data of "0", FIG.
As shown in (b), test data in which all bits are "1" is output.

The data comparing section 75 compares each data read from the test use address of the memory 100 with the test data, and compares the result with the short determining section 76.
Output.

The short determining section 76 includes a data comparing section 75
Therefore, it is possible to determine whether or not the address bus is short-circuited based on the comparison result between each data read from the test use address of the memory 100 and the test data.

[0183] For example, after writing the test data to the test using the address 2 ^i, among the data read from the test using the address of the memory 100, data read from the 2 ^k address is in FIG. 17 (c) As shown, the bi bit is "
1 ", the address line Ai and the address line Ak
Are determined to be short-circuited.

Next, the processing operation of the memory control device according to the seventh embodiment will be described.

The description of the similar operation of the memory control device of the first embodiment, that is, the alternative operation for the data of the failed address in the memory 100 is omitted, and the short-circuit inspection of the address bus 31 between the memories 100 is omitted. The processing will be described.

When the memory control device 1 of this embodiment receives an instruction for a short test of the address bus 31 between the memories 100 from the host system, the memory control device 1 clears the data stored in the test use address of the memory 100 to clear data or A process of saving these data so as not to be erased by the test data (data saving process), a process of writing the above-described clear data in the inspection use address of the memory 100 (clear data writing process), and a test use address of the memory 100 (Test data writing process), a process of judging a short-circuit of an address line from data read from the test use address of the memory 100 and data read from the test use address ( Short judgment processing), save the saved data to the original inspection address Process of ascribed (data return processing) is gradually performed in this order.

Hereinafter, the processing operations of the above-described data saving processing, clear data writing processing, test data writing processing, short determination processing, and data restoration processing will be described separately.

Data Evacuation Processing The access control unit 71 sends the memory 10
When receiving an instruction for a short test of the address bus 31 between 0, the test data generating unit 72 is instructed to output an address for saving the data stored at the test use address to the save buffer 73. .

Upon receiving the above-mentioned instruction from the access control section 71, the test address generating section 72 determines, based on the instruction, address 0, address 1, address 2, address 4,... .., ^2n-1 These addresses are output to the address bus 31 in the order of the addresses. In addition,
Each time these addresses are output, this is output to the access control unit 71.

Thereafter, in the save buffer 73, according to the read address output from the test address generator 72,
Address 0, Address 1, Address 2, Address 4, ..., 2 ^n-1
The data stored in the memory 100 is stored in the order of the addresses, and the data saving process ends.

About Clear Data Writing Process When the above-described data saving process is completed, the access control unit 71 instructs the clear / test data generation unit 74 to generate the above-mentioned clear data.

The clear / test data generating section 74 generates clear data in accordance with an instruction from the access control section 71,
The occurrence is output to the access control unit 71.

Thereafter, the access control unit 71 instructs the test data generation unit 72 to output an address for writing clear data to the test use address of the memory 100.

Upon receiving the instruction from the access control unit 71, the test address generation unit 72 sets the address 0, address 1, address 2, address 4,...
., ^2n-1 These addresses are output to the address bus 31 in the order, and the access control unit 7
Output to 1.

Each time the access control section 71 receives an output of the address from the test address generation section 72,
The clear / test data generation unit 74 is instructed to output the generated clear data to the data bus 32.

The clear / test data generating section 74 transmits the clear data to the data bus 32 in accordance with the access control section 71.
Output to

In this way, addresses 0, 1, 2, 4, 4,...
Clear data is written in the order of 2 ^n-1 addresses, and the clear data writing process ends.

Test Data Writing Process When the above-described clear data writing process is completed, the access control unit 71 instructs the clear / test data generation unit 74 to generate the above-described test data.

The clear / test data generating section 74 generates clear data in accordance with an instruction from the access control section 71,
Outputting the occurrence to the access control unit 71,
The generated test data is output to the data comparison unit 75.

Thereafter, the access control unit 71 instructs the test data generation unit 72 to output an address for writing test data to a test use address of the memory 100.

[0201] test address generator 72 receives the instruction of the access control unit 71, based on this instruction, and outputs the address of the test using the address A ⁱ of the memory 100, and outputs the fact to the access control unit 71 .

Then, the access control unit 71 sets the clear /
It instructs the test data generator 74 to output the generated test data to the data bus 32.

Thereafter, clear / test data generating section 74
Outputs test data to the data bus 32 according to the access control unit 71.

[0204] In this way, the test use the address A ⁱ of the memory 100 to store the clear data, and terminates the test data writing process.

Short-Term Determination Process When the above-described test data writing process is completed, the access control unit 71 writes the test data generation unit 74 to the test data generation unit 72 and writes the test data to the test use address of the memory 100. Clear data, address 0, 1
An instruction is issued to output addresses for reading in the order of address, address 2, address 4,..., Address ^2n-1 .

Upon receiving the instruction from the access control unit 71, the test address generation unit 72, based on the instruction, compares the test use address of the memory 100 with address 0, address 1, address 2, address 4,... , ^2n-1 and outputs these addresses to the address bus 31 in that order, and outputs the fact to the access control unit 71.

Each time the access control unit 71 receives an output of the address from the test address generation unit 72,
It instructs the data comparison unit 75 to compare the clear data read from the test address with the test data.

The data comparing section 75 includes an access control section 71
Is received, the clear data read from the test use address of the memory 100 is compared with the test data based on the instruction, and the result is output to the short determination section 76 and output to the access control section 71. I do.

[0209] Thereafter, the access control section 71 instructs the short determination section 76 to determine whether there is a short based on the comparison result of the received clear data and test data.

[0210] The short determination section 76
It is determined whether or not there is a short circuit based on the instruction of (1).

[0211] In other words, short-circuit determination unit 76, since the test data, which is the case written to test use address A ^i, and it is determined whether or not the address line Ai is short-circuited and the other address line, if, clear data that has been read one inspection using the address a ^k, bit bi constituting the clear data of the test using the address a ^k is "
If it is not "0" but "1", it is determined that the address line Ai and the address Ak (i ≠ k) are short-circuited.

[0212] In this way, the address 0, address 1, address 2, address 4, ..., for the case where the order of 2 ^n-1 address written test data, by performing the same processing, address bus The short-circuit determination process for all the address lines constituting 31 ends.

Data Recovery Processing When the above-described short determination processing is completed, the access control section 71 instructs the test data generation section 72 to read out the data stored in the test use address before the short test from the save buffer 73. To output the address for

Upon receiving the above-mentioned instruction from the access control section 71, the test address generating section 72 determines, based on the instruction, addresses 0, 1, 2, 4,. .., in the order of 2 ^n-1 addresses,
These addresses are output to the address bus 31.

Thereafter, the addresses are read from the save buffer 73 in the order of address 0, address 1, address 2, address 4,..., Address 2 ⁿ⁻¹ according to the address output by the test address generator 72. Then, the data is written to the inspection use address, and the data restoration process ends.

Thereafter, the access control section 71 outputs a message to that effect to the host system, thereby ending the short-circuit inspection processing.

In the memory control device 1 of this embodiment, the replacement buffer 11 is provided for the failed memory, and the memory controller 1 further includes the address line short-circuit check section 7.
It is possible to detect whether the failure of the memory 100 is caused by short-circuiting of the address line or whether the failure of the memory 100 is itself.

<Eighth Embodiment> FIG. 18 is a schematic explanatory view of a memory control device according to an eighth embodiment of the present invention.
FIG. 9 is a block diagram showing a configuration of a memory control device according to an eighth embodiment of the present invention.

[0219] The memory control device 1 of this embodiment is different from the memory control device shown in FIG.
As shown in FIG. 8, before the data is written to the memory 100, the verifying unit 8 is provided as shown in FIG.
After temporarily storing data in a write buffer 83 included in the verifying unit 8, the data is written to the memory 100, and then the written data is read out again. It is designed to be written.

The control device 1 of this embodiment includes a substitute buffer 11, an address search unit 12, a read / write unit 13, an address buffer 18, and a verify unit 8.

Here, among the components of the memory control device according to this embodiment, the same components as those of the first embodiment are denoted by the same reference numerals, and hereinafter, these components will be described. A detailed description of is omitted.

The verify 8 includes an access control section 81 for controlling each component of the verify section 8, a verify address generating section 82, a write buffer 83, a storage area allocating section 84, a data comparing section 85, an address And a writing unit 86.

The verify address generator 82 generates an address to be written to the memory 100 and an address to read data from the memory 100 on the address bus 31.

The write buffer 83 stores an address area 831 for storing the address of write data to be written to the memory 100, a write data area 832 for storing write data to be written to the memory 100, and stores the data in the memory 1
00 and a verify data area 833 for storing read data (verify data) again.

The storage area allocating unit 83 is provided with the data bus 32
Is transferred to the write data area 832 or the verify data area 833 of the write buffer 83.

When the data received from the data bus 32 is write data, the write data is stored in the write data area 832 of the write buffer 83, and the address of the write data is stored in the address area. It has become so.

The data comparing section 85 is provided with the storage area allocating section 8
4 is compared with the data stored in the verify data area 833. If the write data does not match the verify data, the address of the write data is written to the address writing unit 86. Occurs.

Upon receiving the address of the write address from the data comparing section 85, the address writing section 86 writes the address in the address area 111 of the substitute buffer 11.

Next, the operation of the memory control device according to the eighth embodiment will be described.

The description of the similar operation of the memory control device of the first embodiment, that is, the alternative operation for the data of the failed address in the memory 90, is omitted.
The write verify process will be described.

In the memory control device 1 of this embodiment, when the access control unit 81 receives an instruction from the host system that the write data to be written into the memory 100 can be verified, the storage control unit 81 And give instructions to sort.

The storage area distribution unit 84 stores the write data in the write data area 832 based on the access control unit 81.
Then, the address is allocated and stored in the address area 831, and the access control unit 81 generates a notification to that effect.

The access control unit 81 issues an instruction to the verify address forming unit 82 so that the write data is generated by forming an address of the memory 100 to be written, in order to verify the write data.

The verify address generation 82 corresponds to the memory 1
The address to be written to the address 00 is generated on the address bus 31 and the access control unit 81 is informed of that.

The access control unit 81 instructs the storage area distribution unit 84 to generate verify data.

The storage area allocating section 84 generates the write data stored in the write area of the write buffer 83 as the verify data on the data bus 32 based on the instruction of the access control section 84, and notifies the access control section 8 of the fact.
Occurs at 1.

Next, the access control section 81 forms a read address for reading the verify data previously written in the memory 100 to the verify address generating section 82, generates the read address on the address bus 31, and gives an access to that effect. It is generated in the control unit 81.

After that, the storage area allocating section 84 converts the verify data read from the memory 100 into the verify data area 833 based on the instruction of the access control section 81.
To the access control unit 81.

Subsequently, the data comparing section 85 compares the data stored in the write data area 831 of the write buffer 83 with the data stored in the verify data area 832 based on the instruction of the access control section 81. ,
If the write data and the verify data do not match, an address of the write data is generated in the address writing section 86.

The address writing section includes a data comparing section 85
Receives the address of the write address from, the address is written into the address area 111 of the substitute buffer 11, and the same processing is performed on the next write data.

In the memory control device 1 of this embodiment, before the verifying unit 8 writes data to the memory 100,
After temporarily storing the data in the write buffer 84, the data is written into the memory 100, and then the written data is read again, and the two are compared to confirm that they match, and then the data is written. In this way, it is possible to prevent a failure location in the memory from being found in advance, and to prevent data from being lost by erroneous writing.

Further, since the memory control device 1 of this embodiment further has the substitute buffer 11, substitute means can be performed for a failed address.

<Ninth Embodiment> FIG. 20 is a schematic configuration diagram of a memory control device according to a ninth embodiment of the present invention.

Generally, DRAM used as a memory
In consideration of the above configuration, it is assumed that not only a failure at a single address but also a failure occurs in a block unit (see FIG. 22).

The memory control device 1 of this embodiment is different from that of FIG.
As shown in FIG. 0, a fault location occurring in a block unit in the memory 100 is alternately stored, and a faulty buffer 91 for storing data describing the faulty block 102 is provided.

Then, the memory control device 1 of this embodiment
When a read / write access occurs to an address in the faulty block 102 of the memory 100 from a host system such as a CPU or a DMA controller, the corresponding part of the substitution buffer 91 is read / written instead of the host system.
Write access.

The substitute buffer 91 is a BATC (Blok A
ddress Translation Cache), a reference position area 911 for storing a reference position to be described later indicating the failed block 102 in the memory 100, and whether or not the failed block 2 is a "row" or a "column". Status area 91 for storing a status indicating whether or not
2 and a data area 913 for alternately storing data to be stored in the failed block 102.

Here, the reference position, status and substitute data stored in the reference position area 911, status area 912 and data area 913 are referred to as a set of data corresponding to the failed block.

The replacement buffer 91 of the memory control device 1 of the ninth embodiment and the replacement buffer 11 of the memory control device of the first embodiment have different replacement ranges in which the failure occurs.
As described above, since the former is only a block range and the latter is only an address, a description using a block unit showing the configuration of the memory control device 1 of the ninth embodiment will be omitted.

However, how to describe a failed block will be described.

That is, the storage area 150 of the DRAM is
The horizontal axis is divided in a predetermined range, and the center axis is "CA0, CA1, CA2,..., CAn" for the vertical direction, and "RA0, RA1, RA2,.
·, RAm ”.

If RA1 is within the division range with the central axis as in the case of the faulty block 102a, the range in which the faulty block 102a is to be stored is set to A.
RA1 is used as a range, and the range of A is specified.

On the other hand, as in the failed block 102b, C
If A1 is within the division range that is the central axis, the range in which the faulty block 102b is stored alternately is set as the B range,
CA1 is used to specify the range of B.

In this case, as described above, the faulty block considerably smaller than the predetermined division range has a poor substitution efficiency, but the method of setting the division range described above, for example, the vertical and horizontal division ranges described above. Can be further divided to increase the substitution efficiency.

<Tenth Embodiment> FIG. 23 is a schematic configuration diagram of a memory control device according to an eleventh embodiment of the present invention.
The memory control device of this embodiment specifies a reference position area 911 for storing a reference position of a failed block in the memory and a range for alternately storing data of the failed block in the memory in the relocation area 101 on the memory 100. Relocation range designation table 9 having a relocation range designation area 912
5 is provided.

Therefore, the memory control device of this embodiment has a rearrangement range designation area 912 for designating a range for alternately storing data at the location 101 on the memory 100, so that the memory control device of the tenth embodiment is different from the memory control device of the tenth embodiment. , The required circuitry can be reduced.

[0257]

As described above, according to the present invention, since the replacement buffer stores the data of the failed portion in the memory in place of the failed buffer, it can be used even if the memory fails.

In particular, when the memory is mounted as a SIMM or a DIMM, even if the memory fails, it is not necessary to replace the entire module, and waste of cost can be suppressed.

Further, in the case where the parity check or the ECC is performed, even if the failure location is within a range that can be handled by the ECC method, the reliability of the location is reduced as a location for storing data. , Such EC
In the case of a failure point that can be handled by C, the replacement buffer
Since the information is stored instead, high reliability can be obtained.

Further, unlike a system equipped with a conventionally existing memory, the use of a faulty memory is not excluded by address conversion, so that it is not necessary to perform a degenerate operation of the system, so that processing is executed with high efficiency. be able to.

[Brief description of the drawings]

FIG. 1 is a schematic explanatory diagram of a first embodiment of a memory control device according to the present invention.

FIG. 2 is a block diagram showing a configuration of a first embodiment of a memory control device according to the present invention.

FIG. 3 is a block diagram showing a configuration of a substitute buffer provided in a second embodiment of the memory control device according to the present invention.

FIG. 4 is a schematic explanatory diagram of a third embodiment of the memory control device according to the present invention.

FIG. 5 is a block diagram showing a configuration of a third embodiment of the memory control device according to the present invention.

FIG. 6 is a schematic explanatory view of a fourth embodiment of the memory control device according to the present invention.

FIG. 7 is a block diagram showing a configuration of a substitute memory for the cache memory in FIG. 6;

FIG. 8 is a block diagram showing a configuration of a fourth embodiment of the memory control device according to the present invention.

FIG. 9 is an explanatory diagram illustrating one use mode of a memory device according to a fourth embodiment;

FIG. 10 is a schematic explanatory view of a fifth embodiment of the memory control device according to the present invention.

FIG. 11 is a block diagram showing a configuration of a fifth embodiment of the memory control device according to the present invention.

FIG. 12 is a schematic explanatory diagram of a sixth embodiment of the memory control device according to the present invention.

FIG. 13 is a block diagram showing a configuration of a sixth embodiment of the memory control device according to the present invention.

FIG. 14 is an explanatory diagram of test data used in the memory control device according to the embodiment.

FIG. 15 is a schematic explanatory diagram of a seventh embodiment of the memory control device according to the present invention.

FIG. 16 is a block diagram showing the configuration of a seventh embodiment of the memory control device according to the present invention.

FIG. 17 is an explanatory diagram of clear data and test data used in the memory control device of the embodiment.

FIG. 18 is a schematic explanatory view of an eighth embodiment of the memory control device according to the present invention.

FIG. 19 is a block diagram showing a configuration of an eighth embodiment of the memory control device according to the present invention.

FIG. 20 is a schematic explanatory view of a ninth embodiment of the memory control device according to the present invention.

FIG. 21 is a block diagram showing a configuration of an alternative buffer in FIG. 20;

FIG. 22 is a block diagram showing a configuration of a DRAM used alternately by the memory control device of the embodiment.

FIG. 23 is a schematic explanatory view of a tenth embodiment of the memory control device according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory control device 2 CPU 4 Address line short-circuit inspection part 5 Memory test part 51 Access control part 52 Test address generation part 53 Save buffer 54 Test data generation part 55 Data comparison part 56 Address writing part 6 Address line disconnection inspection part 61 Access Control unit 62 Test address generation unit 63 Save buffer 64 Test data generation unit 65 Data comparison unit 66 Disconnection determination unit 7 Address line short inspection unit 71 Access control unit 72 Test address generation unit 73 Save buffer 74 Clear / test data generation unit 75 Data Comparison section 76 Short determination section 8 Verify section 81 Access control section 82 Verify address generation section 83 Write buffer 831 Address area 832 Write data area 833 Verify data area 84 Storage area distribution 85 data comparison unit 86 address writing unit 11 substitution buffer 12 address search unit 13 read / write unit 14 address buffer 33 relocation address table 331 address area 332 relocation address area 101 relocation area 111, 211 address area 112, 212 data Area 213 Status area 31 Address bus 32 Data bus 100 Memory 91 Substitution buffer 102 Fault block 110 Cache memory 120 Substitution buffer 121 Address area 122 Status area 123 Command area 911 Reference position area 912 Status area 913 Data area 95 Relocation range designation Table 951 Reference position area 952 Relocation range designation area A0, A1, A2, A3, A4, An-1 Address line

Claims (34)

[Claims] 1. A memory control device, comprising: a substitute storage unit that substitutes and stores data of a failed part in a memory. 2. The method according to claim 1, wherein the alternative storage means includes an address area for storing an address of a failure location in the memory, and a data area for alternately storing data to be stored in the address of the failure location in the memory. The memory control device according to claim 1, wherein 3. An address retrieving means for retrieving an address for the memory from an upper system such as a CPU or a DMA, and retrieving an address from the upper system by the address retrieving means. If searched from,
3. The memory control device according to claim 1, further comprising read / write means for reading / writing data from / to said alternative storage means. 4. The memory control device according to claim 1, wherein said alternative storage means uses a write buffer area as a remaining area for storing data of a failed part in said memory. 5. The alternative storage means includes: an address area for storing a failed address in the memory and an address as the write buffer; data to be stored in an address of a failed portion of the memory; A data area for storing data, and a status area for storing a status flag indicating whether the data stored in the data area is replacement data when the memory fails or data of the write buffer. 5. The memory control device according to claim 4, comprising: 6. A relocation address having an address area for storing an address of a memory fault location and a relocation address area for storing an address for alternately storing data of the memory fault location in a predetermined location on the memory. A memory control device comprising storage means. 7. When an address for the memory is received from a host system such as a CPU or a DMA, an address search means for searching the relocation address storage means, and the address from the host system is re-read by the address search means. 7. A relocation address reading means for reading out a relocation address in place of a failed address from the relocation address storage means when retrieved from the relocation address storage means.
A memory control device as described. 8. An address search device, provided in a cache memory, for alternately storing data of a failed portion in a memory, when receiving an address from a CPU, searching for the alternative storage device. Means, and read / write means for reading / writing data from / to the alternative storage means when the address from the CPU is searched from the alternative storage means by the address search means. Memory control device. 9. The memory control device according to claim 8, wherein in a system where parallel processing is performed by a DMA controller or a plurality of CPUs, the memory control device is provided in a location adjacent to each CPU in combination with a cache memory. 10. An alternative storage means for alternately storing a failed part in a memory, an address search means for searching for the alternative storage means when an address for the memory is received from a host system such as a CPU or a DMA. Means for retrieving the address from the higher-level system from the alternative storage means,
A memory control comprising: read / write means for reading / writing data from / to said alternative storage means; and memory test means for testing a failed part in said memory stored in said alternative storage means. apparatus. 11. The memory test means includes: a test address generating means for generating a test address for the memory; a test data generating means for generating test data to be written to a location of the test address in the memory; Data comparing means for comparing the data read from the test data written at the test address location in the memory with the test data generated by the test data generating means; A test address writing unit that writes a test address to the alternative storage unit when it is determined that the data read from the test data written at the address location is different from the test data generated by the test data generation unit; 11. The memory control device according to claim 10, wherein: 12. The apparatus according to claim 1, wherein said address generating means sequentially outputs addresses from address 0 to a maximum address.
2. The memory control device according to 1. 13. The memory test means has an evacuation buffer, and writes data stored at the test address location in the memory before writing to the test address location in the memory. 13. The memory control device according to claim 10, wherein the data is saved in the save buffer. 14. An alternative storage means for alternately storing a failed part in a memory; an address search means for searching for the alternative storage means when an address for the memory is received from a host system such as a CPU or a DMA; Means for retrieving the address from the higher-level system from the alternative storage means,
A memory control device comprising: read / write means for reading / writing data from / to said alternative storage means; and address line disconnection inspection means for inspecting disconnection of an address bus connecting said memories. 15. An address line disconnection inspection unit, comprising: a test address generation unit for generating a test address for the memory; and a test data generation unit for generating test data to be written to the test address location in the memory. A data comparing means for comparing data read from the test data written at the test address in the memory with test data generated by the test data generating means; Based on a comparison result between the data read from the test data written at the test address in the test data and the test data generated by the test data generating means, it is determined whether or not there is a disconnection in the address bus connecting the memories. 15. The method according to claim 14, further comprising disconnection determination means for determining. Li inspection apparatus. 16. The test address generating means, when testing the address line A0, generates test addresses of addresses 0 and 1, and generates a test address of the address line Ai.
(I = 1,2,3, ···· n- 1) when examining the memory controller according to claim 15, wherein generating a test address at address 0 and ^{A i} address. 17. The disconnection judging means, when receiving the coincidence status of the test data for the address 0 and the address 1 from the data comparing means, sets the address 0 and the address 1 to each other.
Only when it is determined that the addresses coincide with each other, it is determined that there is no break in the address line A0.
If information indicating that one of the addresses and address 1 does not match is received, it is determined that there is a break in the address line A0, and the addresses 0 and 2 ⁱ ( i = 0, 1, 2, 3, receives the matching status of the test data for ···· n-1) address, when receiving the information that both match the address 0 and ^{2 i} address only, while determining that there is no break in the address line Ai, determines that of the address 0 and 2 ⁱ address, if any one has received the information that no match, there is a break in the address line Ai The memory control device according to claim 15, wherein: 18. In the test data, assuming that one word of a memory is composed of n bits, test data to be written to address 0 has "0" stored in all bits, and 2 ⁱ (i = 0, 1, 2, 3, ... n-
18. The memory control device according to claim 15, wherein at the address 1), "1" is stored in the bi bit and "0" is stored in the other bits. 19. The address line disconnection inspection means has an evacuation buffer, and stores data stored in the test address location in the memory before writing to the test address location in the memory. 15. The memory control device according to claim 14, wherein data is saved in the save buffer. 20. The memory control device according to claim 14, wherein the address line disconnection inspection means detects a disconnection of an address bus between the memories before replacing the faulty address in the memory with the alternative storage means. 21. An alternative storage means for alternately storing a failed portion in a memory, an address search means for searching for the alternative storage means when an address for the memory is received from a host system such as a CPU or a DMA. Means for retrieving the address from the higher-level system from the alternative storage means,
A memory control device comprising: read / write means for reading / writing data from / to said alternative storage means; and address line short-circuit check means for checking a short-circuit of an address bus connecting said memories. 22. The address line shorting inspection means, a clear address generation means for generating a clear address for the memory, a test address generation means for generating a test address for the memory, and the clear in the memory. Clear data generating means for generating clear data to be written to an address location, test data generating means for generating test data to be written to a test address location in the memory, and clear data generating means for writing to the clear address location in the memory Data comparing means for comparing the read data of the clear data with the test data generated by the test data generating means; and comparing the clear data written in the memory at the location of the clear address compared by the data comparing means. Based on the comparison result with the read data, 22. The memory inspection device according to claim 21, further comprising: a short-circuit determination unit configured to determine whether an address bus connecting the cells is short-circuited. 23. The memory according to claim 23, wherein said clear address generating means comprises: 0, ^1, 2, 4,...
The address of the address is generated, and the test address generating means generates an address line Ai (i = 0, 1, 2, 3,..., N-
If the 1) it is checked whether or not short-circuit and the other address line k (k ≠ i) is, 2 ⁱ in the memory
23. The memory control device according to claim 22, wherein an address of the address is generated. 24. The short-circuit judging means, wherein the address line Ai (i = 0, 1, 2, 3,..., N-1)
There is the case to determine whether or not short-circuited with other address lines Ak (k ≠ i), instead of bit bi constituting the data read from the 2 ^k address of the memory is "0""1 23. The memory control device according to claim 22, wherein if "", it is determined that the address line Ai and the address line Ak are short-circuited. 25. The memory control device according to claim 22, wherein all bits of the clear data are "0", and all bits of the test data are "1". 26. The address line short-circuit inspection means,
22. The memory control device according to claim 21, further comprising a save buffer for performing a short-circuit check, wherein the data stored in the memory is saved to the save buffer before the short-circuit check is performed. 27. The memory control device according to claim 21, wherein the address line short-circuit check means detects a disconnection of an address bus between the memories before the faulty address in the memory is replaced by the substitute storage means. 28. An alternative storage means for alternately storing a failed part in a memory, an address search means for searching for the alternative storage means when an address for the memory is received from a host system such as a CPU or a DMA. Means for retrieving the address from the higher-level system from the alternative storage means,
Read / write means for reading / writing data from / to the alternative storage means; and verifying means for comparing the data with the data read after writing the data when writing the memory data. A memory control device comprising: 29. The verifying means, comprising: an address area for storing an address of data to be written to the memory, a data area for storing data to be written to the memory, and verify data read again after the data is written to the memory. Data storage means comprising a verify data area to be stored; data means to be written to the memory stored in the data area of the data storage means; and comparison means for comparing verify data stored in the verify data area; Data written by the comparing means to the memory;
As a result of comparing the verify data stored in the verify data area, if the write data and the verify data do not match, the address of the write data to the memory is replaced with the address of the memory as a failed part in the memory. 29. The memory control device according to claim 28, further comprising address writing means for writing to the storage means. 30. A memory control device, comprising: alternative storage means for alternately storing data of a failure location occurring in a block unit in a memory. 31. A reference position area storing a reference position indicating a position of a failed block in the memory, and a status area storing a status indicating a state of the reference position of the failed block in the memory. 31. The memory control device according to claim 30, further comprising: a data area for alternately storing data to be stored in a failed block in the memory. 32. The memory control device according to claim 31, wherein the reference position is a position of a central axis of an area obtained by dividing the storage area of the memory by a predetermined width in the vertical and horizontal directions. 33. If the faulty block in the memory is within a division range which is a predetermined central axis, the range for alternately storing the faulty block is the division range which becomes this central axis. Item 33. The memory control device according to item 32. 34. A reference position area for storing a reference position of a failed block in a memory, and a relocation range designation area for designating a range for alternately storing data of the failed block in the memory at a predetermined location on the memory. A memory control device comprising a relocation address storage means having the following.