JPH04257044A - Bus parity error generating position detecting system - Google Patents

Abstract

PURPOSE:To specify a local bus on which a fault occurs, in an information processor such as an input and output controller. CONSTITUTION:Parity controlling parts 3a-3c are respectively connected with each local address bus 8a-8c, and local data bus 9a-9c. A parity bit is generated by a parity generating part 2 at the time of the write cycle of a CPU 1, and a parity check is operated by each parity controlling part 3a-3c based on the parity bit. Each parity controlling part 3a-3c stores the generation of a parity error at the time of detecting the parity error, and makes a bus error line 7 to be active. When the bus error line 7 is activated, the CPU 1 outputs the address of each parity controlling part 3a-3c to an address modifier line 6, reads out information from each parity controlling part 3a-3c, and specifies the local bus on which the fault occurs, based on the read information.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting the location of a bus parity error in an information processing device such as an input/output control device.

0002

2. Description of the Related Art In information processing devices such as input/output control devices, buses connected to a CPU include a local bus for the CPU which is directly connected to the CPU, and a local bus to which an input/output line adapter section is connected. , There are functionally divided devices such as a common local bus that connects these local buses. When detecting a fault in such a functionally divided bus, conventionally, a parity bit generation means for generating a parity bit for information outputted to the bus by the CPU is provided, and when a parity error is detected for each local bus, A parity error detection means for activating a bus error line is provided, and when the bus error line becomes active, the CPU determines that a failure has occurred on the bus.

0003

[Problem to be Solved by the Invention] However, in the conventional example described above, although it is possible to detect that a fault has occurred on a bus, there is a problem in that it is not possible to specify which local bus the fault has occurred on. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for detecting the location of a bus parity error that can identify a local bus in which a fault has occurred.

[0005]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a CPU having a bus error line and an address modifier line, and a bus connected to the CPU and composed of a plurality of local buses. The information processing device includes: a parity generation means for generating a parity bit for information outputted by the CPU to the bus during a write cycle of the CPU; and a parity generation means provided for each of the local buses, the parity generation means generating parity control means that performs a parity check based on the parity bit and the information on the corresponding local bus, activates the bus error line by detecting a parity error, and stores that a parity error has occurred; When the bus error line becomes active, the CPU outputs the address assigned to each of the parity control means to the address modifier line to read the contents stored in each of the parity control means. This is to read out and determine the location of the failure based on the read contents.

[0006]

[Operation] During a CPU write cycle, a parity bit for information output by the CPU to the bus is generated by the parity generation means, and the parity control means provided for each local bus is based on the parity bit generated by the parity generation means. A parity check is performed on the information on the corresponding local bus. When each parity control means detects a parity error, it activates the bus error line and stores the fact that a parity error has occurred. When the bus error line becomes active, the CPU outputs the address assigned to each parity control means to the address modifier line, reads out the contents stored in each parity control means, and the read contents indicate when a parity error has occurred. C of the parity control means showing
A faulty local bus is identified based on information read from each bus control means, such as determining that a fault has occurred in the local bus corresponding to the parity control means closest to the PU.

[0007]

Embodiments Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, which includes a CPU 1, a parity generation section 2, parity control sections 3a to 3c, transceivers 4a to 4c, and a device 5a.
, 5c, address modifier line (AM line) 6,
It includes a bus error line (BERR line) 7, local address buses 8a to 8c, local data buses 9a to 9c, address parity lines 10a to 10c, and data parity lines 11a to 11c.

The CPU 1 is a CPU that has an AM line 6 and a BERR line 7, and can execute exception processing when the BERR line 7 becomes active. The parity generation unit 2 generates parity bits for data and addresses that the CPU 1 outputs to the local address bus 8a and local data bus 9a, and generates parity bits for the address parity lines 10a,
It is output to the data parity line 11a.

Address parity line 10a and data parity line 11a are connected to address parity line 10b and data parity line 11b via transceiver 4a, and address parity line 10b and data parity line 11b are connected to address parity line 10b and data parity line 11b via transceiver 4b, respectively. It is connected to the line 10c and the data parity line 11c.

Local address bus 8a and local data bus 9a are local buses for the CPU, local address bus 8c and local data bus 9c are local buses for input/output line adapter section, and local address bus 8b.
, local data bus 9b is a common local bus that connects them. Local address bus 8a and local data bus 9a are connected to local address bus 8b and local data bus 9b via transceiver 4a, and local address bus 8b and local data bus 9b are connected to local address bus 8c and local data bus 9b via transceiver 4b, respectively. It is connected to the local data bus 9c. Further, a device 5a is connected to the local address bus 8a and a local data bus 9a via a parity control unit 3a, and a device 5c is connected to a local address bus 8c and a local data bus 9c via a parity control unit 3c. There is. The device 5a is a device such as a DMA controller that operates as a bus master, and the data 5c is a device that operates as an input/output line adapter section.

The parity control units 3a to 3c have a function of detecting parity errors on the local address buses 8a to 8c and local data buses 9a to 9c, a function of activating the BERR line 7 by detecting a parity error,
A function to store the detection state of parity errors, by adding the own address via the AM line 6, the stored parity error detection state is stored on the local data bus 9a~
It has a function to output to 9c.

FIG. 2 is a block diagram showing an example of the configuration of the parity control section 3a, which includes parity check sections 31, 32,
Parity error storage register 33 and register control unit 3
It is composed of 4.

Parity check section 31 detects a parity error based on the address on local address bus 8a and the parity bit on address parity line 10a. The parity check section 32 is connected to the local data bus 9a.
A parity error is detected based on the above data and the parity bit on the data parity line 11a. The parity error storage register 33 includes the parity check sections 31 and 32.
In addition to memorizing the detection state of parity errors in
By storing information indicating the occurrence of a parity error, a parity error occurrence signal 35 is output. When the parity error occurrence signal 35 is output from the parity error storage register 33, the register control unit 34 outputs BERR.
By activating the line 7 and adding the address assigned to its own parity control unit 3a via the AM line 6, the register control signal 36 is output and the contents of the parity error storage register 33 are output to the local data bus 9a. let Note that the other parity control sections 3b and 3c also have the same configuration as the parity control section 3a.

FIG. 3 is a diagram for explaining the operation of the embodiment.
FIG. 4 is a flowchart showing an example of exception processing executed by the CPU 1, and the operation of this embodiment will be described below with reference to each figure.

When the CPU 1 executes a write cycle to transfer data to the device 5c and outputs addresses and data to the local address bus 8a and the local data bus 9a, the parity generation unit 2 causes the CPU 1 to transfer data to the local address bus 8a and the local data bus 9a. A parity bit is generated for the address and data to be output to the local data bus 9a, and output to the address parity line 10a and data parity line 11a.

Parity check units 31 and 32 in the parity control unit 3a perform parity checks on the address on the local address bus 8a and the data on the local data bus 9a, respectively, and when a parity error is detected, the parity error storage register 33 Stores information indicating the occurrence of a parity error. The register control unit 34 sends a parity error occurrence signal 3 to indicate that information indicating the occurrence of a parity error has been stored in the parity error storage register 33.
5, it activates the BERR line 7. The other parity control units 3b and 3c also perform similar operations.

For example, if a failure occurs in the local address bus 8a and local data bus 9a as shown in FIG. 3, the parity control unit 3a will not detect a parity error and will do nothing. The parity control units 3b and 3c perform the operations described above, store information indicating the occurrence of a parity error in the internal parity error storage register 33, and activate the BERR line 7.

When the BERR line 7 becomes active, the CPU 1 executes the following exception processing.

First, the address assigned to the parity control section 3a is output to the AM line 6. When the register control unit 34 in the parity control unit 3a receives the address assigned to its own parity control unit 3a via the AM line 6, it adds a register control signal 36 to the parity error storage register 33, and outputs a register control signal 36 to the parity error storage register 33. 33 (information indicating whether a parity error has occurred) is output to the local data bus 9a. The CPU 1 reads the information output to the local data bus 9a, and then performs the same processing as described above on the parity control section 3b.

After performing the above-described processing on all parity control units 3a to 3c, the CPU 1 performs the exception processing shown in FIG. 4 to identify the local address bus and local data bus where a parity error has occurred.

First, it is determined whether or not the information read from the parity control section 3a corresponding to the local address bus 8a and local data bus 9a indicates the occurrence of a parity error (S1). If it is determined, it is determined that the local address bus 8a and local data bus 9a are at the location of the failure (S2), and if not, the process of S3 is performed. In S3, it is determined whether the information read from the parity control unit 3b corresponding to the local address bus 8b and the local data bus 9b indicates the occurrence of a parity error, and if it is determined that the information indicates the occurrence of a parity error, the local address bus 8
b. It is determined that the local data bus 9b is at the location where the failure has occurred (S4), and if not, the process of S5 is performed. In S5, it is determined whether the information read from the parity control unit 3c corresponding to the local address bus 8c and local data bus 9c indicates the occurrence of a parity error, and if it is determined that the information indicates the occurrence of a parity error, the local address bus 8c and local data bus 9c are determined to be the location where the failure has occurred (S6), and if not, it is determined that there is no parity error (S7).

In this example, since the information read from the parity control unit 3b corresponding to the local address bus 8b and local data bus 9b indicates the occurrence of a parity error, the CPU 1 detects that a failure has occurred in the local address bus 8b and local data bus 9b. It will be determined that it is the position.

In the above-described embodiment, after reading all the information indicating whether or not a parity error has occurred from each parity control section 3a to 3c, the exception handling shown in FIG. Although the local bus in which the error occurred was identified, the information was read in order from the parity control unit 3a near the CPU 1, and the local bus corresponding to the parity control unit that read the information indicating the occurrence of the parity error first was identified as the local bus in which the error occurred. It may be specified as a local bus.

[0024]

As explained above, the bus parity error occurrence position detection method of the present invention, when detecting the occurrence of a parity error corresponding to each local bus, memorizes the fact and activates the bus error line. Furthermore, when the bus error line becomes active, the address assigned to each parity control means is outputted to the address modifier line to detect the parity error stored in each parity control means. Since this method causes the CPU to execute an exception process of reading out the occurrence state of the fault and specifying the location of the fault based on the read information, it is possible to specify the local bus where the fault has occurred.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the invention.

FIG. 2 is a block diagram showing a configuration example of a parity control section.

FIG. 3 is a diagram for explaining the operation of the embodiment.

FIG. 4 is a flowchart showing an example of exception processing executed by a CPU.

[Explanation of symbols]

1...CPU 2...Parity generation unit 3a-3c...Parity control unit 4a-4c...Transmitter/receiver 5a, 5c...Device 6...Address modifier (AM) line 7...Bus error (BERR) line 8a-8c...Local address bus 9a to 9c...Local data buses 10a to 10c...Address parity lines 11a to 11c...Data parity lines

Claims (3)

[Claims] 1. In an information processing device including a CPU having a bus error line and an address modifier line, and a bus connected to the CPU and configured from a plurality of local buses, during a write cycle of the CPU, , the CPU
parity generation means for generating parity bits for information outputted to the bus; and a parity check provided for each of the local buses based on the parity bits generated by the parity generation means and information on the local bus. and a parity control means for activating the bus error line by detecting a parity error and storing the occurrence of a parity error, and the CPU is configured to: It is characterized by outputting the address assigned to each of the parity control means to the address modifier line, reading out the contents stored in each of the parity control means, and determining the location of the failure based on the read contents. bus parity error occurrence position detection method. 2. When the bus error line becomes active, the CPU outputs an address assigned to each of the parity control means to the address modifier line, and each of the parity control means stores the address. A claim characterized in that the content is read and it is determined that a failure has occurred in a local bus corresponding to the parity control means closest to the CPU among the parity control means whose read content indicates the occurrence of a parity error. The bus parity error occurrence position detection method described in 1. 3. When the bus error line becomes active, the CPU outputs the addresses assigned to each of the parity control means to the address modifier line in order from the parity control means closest to the CPU. A claim characterized in that the content stored in each of the parity control means is read out, and it is determined that a failure has occurred in the local bus corresponding to the parity control means from which information indicating the occurrence of a parity error is first read out. Item 1
Bus parity error occurrence position detection method described.